1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __MACH_IMX_CLK_H 3 #define __MACH_IMX_CLK_H 4 5 #include <linux/bits.h> 6 #include <linux/spinlock.h> 7 #include <linux/clk-provider.h> 8 9 extern spinlock_t imx_ccm_lock; 10 extern bool mcore_booted; 11 12 void imx_check_clocks(struct clk *clks[], unsigned int count); 13 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); 14 #ifndef MODULE 15 void imx_register_uart_clocks(void); 16 #else 17 static inline void imx_register_uart_clocks(void) 18 { 19 } 20 #endif 21 void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn); 22 void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count); 23 24 extern void imx_cscmr1_fixup(u32 *val); 25 26 enum imx_pllv1_type { 27 IMX_PLLV1_IMX1, 28 IMX_PLLV1_IMX21, 29 IMX_PLLV1_IMX25, 30 IMX_PLLV1_IMX27, 31 IMX_PLLV1_IMX31, 32 IMX_PLLV1_IMX35, 33 }; 34 35 enum imx_sscg_pll_type { 36 SCCG_PLL1, 37 SCCG_PLL2, 38 }; 39 40 enum imx_pll14xx_type { 41 PLL_1416X, 42 PLL_1443X, 43 }; 44 45 enum imx_pllv4_type { 46 IMX_PLLV4_IMX7ULP, 47 IMX_PLLV4_IMX8ULP, 48 }; 49 50 enum imx_pfdv2_type { 51 IMX_PFDV2_IMX7ULP, 52 IMX_PFDV2_IMX8ULP, 53 }; 54 55 /* NOTE: Rate table should be kept sorted in descending order. */ 56 struct imx_pll14xx_rate_table { 57 unsigned int rate; 58 unsigned int pdiv; 59 unsigned int mdiv; 60 unsigned int sdiv; 61 unsigned int kdiv; 62 }; 63 64 struct imx_pll14xx_clk { 65 enum imx_pll14xx_type type; 66 const struct imx_pll14xx_rate_table *rate_table; 67 int rate_count; 68 int flags; 69 }; 70 71 extern struct imx_pll14xx_clk imx_1416x_pll; 72 extern struct imx_pll14xx_clk imx_1443x_pll; 73 extern struct imx_pll14xx_clk imx_1443x_dram_pll; 74 75 #define CLK_FRACN_GPPLL_INTEGER BIT(0) 76 #define CLK_FRACN_GPPLL_FRACN BIT(1) 77 78 /* NOTE: Rate table should be kept sorted in descending order. */ 79 struct imx_fracn_gppll_rate_table { 80 unsigned int rate; 81 unsigned int mfi; 82 unsigned int mfn; 83 unsigned int mfd; 84 unsigned int rdiv; 85 unsigned int odiv; 86 }; 87 88 struct imx_fracn_gppll_clk { 89 const struct imx_fracn_gppll_rate_table *rate_table; 90 int rate_count; 91 int flags; 92 }; 93 94 struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, 95 const struct imx_fracn_gppll_clk *pll_clk); 96 struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name, 97 void __iomem *base, 98 const struct imx_fracn_gppll_clk *pll_clk); 99 100 extern struct imx_fracn_gppll_clk imx_fracn_gppll; 101 extern struct imx_fracn_gppll_clk imx_fracn_gppll_integer; 102 103 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ 104 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)) 105 106 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ 107 cgr_val, cgr_mask, clk_gate_flags, lock, share_count) \ 108 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ 109 cgr_val, cgr_mask, clk_gate_flags, lock, share_count)) 110 111 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \ 112 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask)) 113 114 #define imx_clk_pfd(name, parent_name, reg, idx) \ 115 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx)) 116 117 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ 118 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)) 119 120 #define imx_clk_fixed(name, rate) \ 121 to_clk(imx_clk_hw_fixed(name, rate)) 122 123 #define imx_clk_fixed_factor(name, parent, mult, div) \ 124 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div)) 125 126 #define imx_clk_divider(name, parent, reg, shift, width) \ 127 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width)) 128 129 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \ 130 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags)) 131 132 #define imx_clk_gate(name, parent, reg, shift) \ 133 to_clk(imx_clk_hw_gate(name, parent, reg, shift)) 134 135 #define imx_clk_gate_dis(name, parent, reg, shift) \ 136 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift)) 137 138 #define imx_clk_gate2(name, parent, reg, shift) \ 139 to_clk(imx_clk_hw_gate2(name, parent, reg, shift)) 140 141 #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \ 142 to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL)) 143 144 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \ 145 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)) 146 147 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ 148 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents)) 149 150 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ 151 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags)) 152 153 #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ 154 to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags)) 155 156 #define imx_clk_pllv1(type, name, parent, base) \ 157 to_clk(imx_clk_hw_pllv1(type, name, parent, base)) 158 159 #define imx_clk_pllv2(name, parent, base) \ 160 to_clk(imx_clk_hw_pllv2(name, parent, base)) 161 162 #define imx_clk_hw_gate(name, parent, reg, shift) \ 163 imx_clk_hw_gate_flags(name, parent, reg, shift, 0) 164 165 #define imx_clk_hw_gate2(name, parent, reg, shift) \ 166 imx_clk_hw_gate2_flags(name, parent, reg, shift, 0) 167 168 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \ 169 imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0) 170 171 #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \ 172 __imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE) 173 174 #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \ 175 __imx_clk_hw_gate(name, parent, reg, shift, flags, 0) 176 177 #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \ 178 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL) 179 180 #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \ 181 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count) 182 183 #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \ 184 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count) 185 186 #define imx_clk_hw_gate3(name, parent, reg, shift) \ 187 imx_clk_hw_gate3_flags(name, parent, reg, shift, 0) 188 189 #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \ 190 __imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0) 191 192 #define imx_clk_hw_gate4(name, parent, reg, shift) \ 193 imx_clk_hw_gate4_flags(name, parent, reg, shift, 0) 194 195 #define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \ 196 imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE) 197 198 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \ 199 imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0) 200 201 #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \ 202 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0) 203 204 #define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ 205 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags, 0) 206 207 #define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \ 208 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY) 209 210 #define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ 211 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0) 212 213 #define imx_clk_hw_divider(name, parent, reg, shift, width) \ 214 __imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT) 215 216 #define imx_clk_hw_divider2(name, parent, reg, shift, width) \ 217 __imx_clk_hw_divider(name, parent, reg, shift, width, \ 218 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE) 219 220 #define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \ 221 __imx_clk_hw_divider(name, parent, reg, shift, width, flags) 222 223 #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \ 224 imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk) 225 226 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, 227 const char *parent_name, void __iomem *base, 228 const struct imx_pll14xx_clk *pll_clk); 229 230 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name, 231 const char *parent, void __iomem *base); 232 233 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent, 234 void __iomem *base); 235 236 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name, 237 void __iomem *base); 238 239 struct clk_hw *imx_clk_hw_sscg_pll(const char *name, 240 const char * const *parent_names, 241 u8 num_parents, 242 u8 parent, u8 bypass1, u8 bypass2, 243 void __iomem *base, 244 unsigned long flags); 245 246 enum imx_pllv3_type { 247 IMX_PLLV3_GENERIC, 248 IMX_PLLV3_SYS, 249 IMX_PLLV3_USB, 250 IMX_PLLV3_USB_VF610, 251 IMX_PLLV3_AV, 252 IMX_PLLV3_ENET, 253 IMX_PLLV3_ENET_IMX7, 254 IMX_PLLV3_SYS_VF610, 255 IMX_PLLV3_DDR_IMX7, 256 IMX_PLLV3_AV_IMX7, 257 }; 258 259 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, 260 const char *parent_name, void __iomem *base, u32 div_mask); 261 262 #define PLL_1416X_RATE(_rate, _m, _p, _s) \ 263 { \ 264 .rate = (_rate), \ 265 .mdiv = (_m), \ 266 .pdiv = (_p), \ 267 .sdiv = (_s), \ 268 } 269 270 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ 271 { \ 272 .rate = (_rate), \ 273 .mdiv = (_m), \ 274 .pdiv = (_p), \ 275 .sdiv = (_s), \ 276 .kdiv = (_k), \ 277 } 278 279 struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name, 280 const char *parent_name, void __iomem *base); 281 282 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, 283 const char *parent_name, unsigned long flags, 284 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask, 285 u8 clk_gate_flags, spinlock_t *lock, 286 unsigned int *share_count); 287 288 struct clk * imx_obtain_fixed_clock( 289 const char *name, unsigned long rate); 290 291 struct clk_hw *imx_obtain_fixed_clock_hw( 292 const char *name, unsigned long rate); 293 294 struct clk_hw *imx_obtain_fixed_of_clock(struct device_node *np, 295 const char *name, unsigned long rate); 296 297 struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name); 298 299 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent, 300 void __iomem *reg, u8 shift, u32 exclusive_mask); 301 302 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name, 303 void __iomem *reg, u8 idx); 304 305 struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name, 306 const char *parent_name, void __iomem *reg, u8 idx); 307 308 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name, 309 void __iomem *reg, u8 shift, u8 width, 310 void __iomem *busy_reg, u8 busy_shift); 311 312 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift, 313 u8 width, void __iomem *busy_reg, u8 busy_shift, 314 const char * const *parent_names, int num_parents); 315 316 struct clk_hw *imx7ulp_clk_hw_composite(const char *name, 317 const char * const *parent_names, 318 int num_parents, bool mux_present, 319 bool rate_present, bool gate_present, 320 void __iomem *reg); 321 322 struct clk_hw *imx8ulp_clk_hw_composite(const char *name, 323 const char * const *parent_names, 324 int num_parents, bool mux_present, 325 bool rate_present, bool gate_present, 326 void __iomem *reg, bool has_swrst); 327 328 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent, 329 void __iomem *reg, u8 shift, u8 width, 330 void (*fixup)(u32 *val)); 331 332 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg, 333 u8 shift, u8 width, const char * const *parents, 334 int num_parents, void (*fixup)(u32 *val)); 335 336 static inline struct clk *to_clk(struct clk_hw *hw) 337 { 338 if (IS_ERR_OR_NULL(hw)) 339 return ERR_CAST(hw); 340 return hw->clk; 341 } 342 343 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate) 344 { 345 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); 346 } 347 348 static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name, 349 const char *parent, unsigned int mult, unsigned int div) 350 { 351 return clk_hw_register_fixed_factor(NULL, name, parent, 352 CLK_SET_RATE_PARENT, mult, div); 353 } 354 355 static inline struct clk_hw *imx_clk_hw_divider_closest(const char *name, 356 const char *parent, 357 void __iomem *reg, u8 shift, 358 u8 width) 359 { 360 return clk_hw_register_divider(NULL, name, parent, 0, 361 reg, shift, width, CLK_DIVIDER_ROUND_CLOSEST, &imx_ccm_lock); 362 } 363 364 static inline struct clk_hw *__imx_clk_hw_divider(const char *name, 365 const char *parent, 366 void __iomem *reg, u8 shift, 367 u8 width, unsigned long flags) 368 { 369 return clk_hw_register_divider(NULL, name, parent, flags, 370 reg, shift, width, 0, &imx_ccm_lock); 371 } 372 373 static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent, 374 void __iomem *reg, u8 shift, 375 unsigned long flags, 376 unsigned long clk_gate_flags) 377 { 378 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 379 shift, clk_gate_flags, &imx_ccm_lock); 380 } 381 382 static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent, 383 void __iomem *reg, u8 shift, u8 cgr_val, 384 unsigned long flags, 385 unsigned int *share_count) 386 { 387 return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 388 shift, cgr_val, 0x3, 0, &imx_ccm_lock, share_count); 389 } 390 391 static inline struct clk_hw *__imx_clk_hw_mux(const char *name, void __iomem *reg, 392 u8 shift, u8 width, const char * const *parents, 393 int num_parents, unsigned long flags, unsigned long clk_mux_flags) 394 { 395 return clk_hw_register_mux(NULL, name, parents, num_parents, 396 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, 397 width, clk_mux_flags, &imx_ccm_lock); 398 } 399 400 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, 401 struct clk *div, struct clk *mux, struct clk *pll, 402 struct clk *step); 403 404 #define IMX_COMPOSITE_CORE BIT(0) 405 #define IMX_COMPOSITE_BUS BIT(1) 406 #define IMX_COMPOSITE_FW_MANAGED BIT(2) 407 408 #define IMX_COMPOSITE_CLK_FLAGS_DEFAULT \ 409 (CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) 410 #define IMX_COMPOSITE_CLK_FLAGS_CRITICAL \ 411 (IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_IS_CRITICAL) 412 #define IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE \ 413 (IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_GET_RATE_NOCACHE) 414 #define IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE \ 415 (IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE | CLK_IS_CRITICAL) 416 417 struct clk_hw *__imx8m_clk_hw_composite(const char *name, 418 const char * const *parent_names, 419 int num_parents, 420 void __iomem *reg, 421 u32 composite_flags, 422 unsigned long flags); 423 424 #define _imx8m_clk_hw_composite(name, parent_names, reg, composite_flags, flags) \ 425 __imx8m_clk_hw_composite(name, parent_names, \ 426 ARRAY_SIZE(parent_names), reg, composite_flags, flags) 427 428 #define imx8m_clk_hw_composite(name, parent_names, reg) \ 429 _imx8m_clk_hw_composite(name, parent_names, reg, \ 430 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT) 431 432 #define imx8m_clk_hw_composite_flags(name, parent_names, reg, flags) \ 433 _imx8m_clk_hw_composite(name, parent_names, reg, \ 434 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT | flags) 435 436 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \ 437 _imx8m_clk_hw_composite(name, parent_names, reg, \ 438 0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL) 439 440 #define imx8m_clk_hw_composite_bus(name, parent_names, reg) \ 441 _imx8m_clk_hw_composite(name, parent_names, reg, \ 442 IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_DEFAULT) 443 444 #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \ 445 _imx8m_clk_hw_composite(name, parent_names, reg, \ 446 IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_CRITICAL) 447 448 #define imx8m_clk_hw_composite_core(name, parent_names, reg) \ 449 _imx8m_clk_hw_composite(name, parent_names, reg, \ 450 IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT) 451 452 #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \ 453 _imx8m_clk_hw_composite(name, parent_names, reg, \ 454 IMX_COMPOSITE_FW_MANAGED, \ 455 IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE) 456 457 #define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \ 458 _imx8m_clk_hw_composite(name, parent_names, reg, \ 459 IMX_COMPOSITE_FW_MANAGED, \ 460 IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE) 461 462 struct clk_hw *imx93_clk_composite_flags(const char *name, 463 const char * const *parent_names, 464 int num_parents, 465 void __iomem *reg, 466 u32 domain_id, 467 unsigned long flags); 468 #define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \ 469 imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \ 470 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) 471 472 struct clk_hw *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name, 473 unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val, 474 u32 mask, u32 domain_id, unsigned int *share_count); 475 476 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name, 477 unsigned long flags, void __iomem *reg, u8 shift, u8 width, 478 u8 clk_divider_flags, const struct clk_div_table *table, 479 spinlock_t *lock); 480 481 struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible, 482 u32 reg, const char **parent_names, 483 u8 num_parents, const u32 *mux_table, u32 mask); 484 485 #endif 486