1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2018-2021 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7 #ifndef __IMX_CLK_SCU_H 8 #define __IMX_CLK_SCU_H 9 10 #include <linux/firmware/imx/sci.h> 11 #include <linux/of.h> 12 13 #define IMX_SCU_GPR_CLK_GATE BIT(0) 14 #define IMX_SCU_GPR_CLK_DIV BIT(1) 15 #define IMX_SCU_GPR_CLK_MUX BIT(2) 16 17 struct imx_clk_scu_rsrc_table { 18 const u32 *rsrc; 19 u8 num; 20 }; 21 22 extern struct list_head imx_scu_clks[]; 23 extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops; 24 extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl; 25 extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp; 26 extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm; 27 28 int __init imx_clk_scu_module_init(void); 29 void __exit imx_clk_scu_module_exit(void); 30 int imx_clk_scu_init(struct device_node *np, 31 const struct imx_clk_scu_rsrc_table *data); 32 struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec, 33 void *data); 34 struct clk_hw *imx_clk_scu_alloc_dev(const char *name, 35 const char * const *parents, 36 int num_parents, u32 rsrc_id, u8 clk_type); 37 38 struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, 39 const char * const *parents, int num_parents, 40 u32 rsrc_id, u8 clk_type); 41 42 void imx_clk_scu_unregister(void); 43 44 struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name, 45 const char *parent_name, unsigned long flags, 46 void __iomem *reg, u8 bit_idx, bool hw_gate); 47 void imx_clk_lpcg_scu_unregister(struct clk_hw *hw); 48 49 struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name, 50 int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags, 51 bool invert); 52 53 static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id, 54 u8 clk_type) 55 { 56 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); 57 } 58 59 static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents, 60 int num_parents, u32 rsrc_id, u8 clk_type) 61 { 62 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); 63 } 64 65 static inline struct clk_hw *imx_clk_lpcg_scu_dev(struct device *dev, const char *name, 66 const char *parent_name, unsigned long flags, 67 void __iomem *reg, u8 bit_idx, bool hw_gate) 68 { 69 return __imx_clk_lpcg_scu(dev, name, parent_name, flags, reg, 70 bit_idx, hw_gate); 71 } 72 73 static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name, 74 unsigned long flags, void __iomem *reg, 75 u8 bit_idx, bool hw_gate) 76 { 77 return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg, 78 bit_idx, hw_gate); 79 } 80 81 static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name, 82 u32 rsrc_id, u8 gpr_id, bool invert) 83 { 84 return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id, 85 IMX_SCU_GPR_CLK_GATE, invert); 86 } 87 88 static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name, 89 u32 rsrc_id, u8 gpr_id) 90 { 91 return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id, 92 IMX_SCU_GPR_CLK_DIV, 0); 93 } 94 95 static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names, 96 int num_parents, u32 rsrc_id, u8 gpr_id) 97 { 98 return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id, 99 gpr_id, IMX_SCU_GPR_CLK_MUX, 0); 100 } 101 #endif 102