1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2018-2021 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7 #include <dt-bindings/firmware/imx/rsrc.h> 8 #include <linux/arm-smccc.h> 9 #include <linux/bsearch.h> 10 #include <linux/clk-provider.h> 11 #include <linux/err.h> 12 #include <linux/of.h> 13 #include <linux/firmware/imx/svc/rm.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_domain.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/slab.h> 18 #include <xen/xen.h> 19 20 #include "clk-scu.h" 21 22 #define IMX_SIP_CPUFREQ 0xC2000001 23 #define IMX_SIP_SET_CPUFREQ 0x00 24 25 static struct imx_sc_ipc *ccm_ipc_handle; 26 static struct device_node *pd_np; 27 static struct platform_driver imx_clk_scu_driver; 28 static const struct imx_clk_scu_rsrc_table *rsrc_table; 29 30 struct imx_scu_clk_node { 31 const char *name; 32 u32 rsrc; 33 u8 clk_type; 34 const char * const *parents; 35 int num_parents; 36 37 struct clk_hw *hw; 38 struct list_head node; 39 }; 40 41 struct list_head imx_scu_clks[IMX_SC_R_LAST]; 42 43 /* 44 * struct clk_scu - Description of one SCU clock 45 * @hw: the common clk_hw 46 * @rsrc_id: resource ID of this SCU clock 47 * @clk_type: type of this clock resource 48 */ 49 struct clk_scu { 50 struct clk_hw hw; 51 u16 rsrc_id; 52 u8 clk_type; 53 54 /* for state save&restore */ 55 struct clk_hw *parent; 56 u8 parent_index; 57 bool is_enabled; 58 u32 rate; 59 }; 60 61 /* 62 * struct clk_gpr_scu - Description of one SCU GPR clock 63 * @hw: the common clk_hw 64 * @rsrc_id: resource ID of this SCU clock 65 * @gpr_id: GPR ID index to control the divider 66 */ 67 struct clk_gpr_scu { 68 struct clk_hw hw; 69 u16 rsrc_id; 70 u8 gpr_id; 71 u8 flags; 72 bool gate_invert; 73 }; 74 75 #define to_clk_gpr_scu(_hw) container_of(_hw, struct clk_gpr_scu, hw) 76 77 /* 78 * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol 79 * @hdr: SCU protocol header 80 * @rate: rate to set 81 * @resource: clock resource to set rate 82 * @clk: clk type of this resource 83 * 84 * This structure describes the SCU protocol of clock rate set 85 */ 86 struct imx_sc_msg_req_set_clock_rate { 87 struct imx_sc_rpc_msg hdr; 88 __le32 rate; 89 __le16 resource; 90 u8 clk; 91 } __packed __aligned(4); 92 93 struct req_get_clock_rate { 94 __le16 resource; 95 u8 clk; 96 } __packed __aligned(4); 97 98 struct resp_get_clock_rate { 99 __le32 rate; 100 }; 101 102 /* 103 * struct imx_sc_msg_get_clock_rate - clock get rate protocol 104 * @hdr: SCU protocol header 105 * @req: get rate request protocol 106 * @resp: get rate response protocol 107 * 108 * This structure describes the SCU protocol of clock rate get 109 */ 110 struct imx_sc_msg_get_clock_rate { 111 struct imx_sc_rpc_msg hdr; 112 union { 113 struct req_get_clock_rate req; 114 struct resp_get_clock_rate resp; 115 } data; 116 }; 117 118 /* 119 * struct imx_sc_msg_get_clock_parent - clock get parent protocol 120 * @hdr: SCU protocol header 121 * @req: get parent request protocol 122 * @resp: get parent response protocol 123 * 124 * This structure describes the SCU protocol of clock get parent 125 */ 126 struct imx_sc_msg_get_clock_parent { 127 struct imx_sc_rpc_msg hdr; 128 union { 129 struct req_get_clock_parent { 130 __le16 resource; 131 u8 clk; 132 } __packed __aligned(4) req; 133 struct resp_get_clock_parent { 134 u8 parent; 135 } resp; 136 } data; 137 }; 138 139 /* 140 * struct imx_sc_msg_set_clock_parent - clock set parent protocol 141 * @hdr: SCU protocol header 142 * @req: set parent request protocol 143 * 144 * This structure describes the SCU protocol of clock set parent 145 */ 146 struct imx_sc_msg_set_clock_parent { 147 struct imx_sc_rpc_msg hdr; 148 __le16 resource; 149 u8 clk; 150 u8 parent; 151 } __packed; 152 153 /* 154 * struct imx_sc_msg_req_clock_enable - clock gate protocol 155 * @hdr: SCU protocol header 156 * @resource: clock resource to gate 157 * @clk: clk type of this resource 158 * @enable: whether gate off the clock 159 * @autog: HW auto gate enable 160 * 161 * This structure describes the SCU protocol of clock gate 162 */ 163 struct imx_sc_msg_req_clock_enable { 164 struct imx_sc_rpc_msg hdr; 165 __le16 resource; 166 u8 clk; 167 u8 enable; 168 u8 autog; 169 } __packed __aligned(4); 170 171 static inline struct clk_scu *to_clk_scu(struct clk_hw *hw) 172 { 173 return container_of(hw, struct clk_scu, hw); 174 } 175 176 static inline int imx_scu_clk_search_cmp(const void *rsrc, const void *rsrc_p) 177 { 178 return *(u32 *)rsrc - *(u32 *)rsrc_p; 179 } 180 181 static bool imx_scu_clk_is_valid(u32 rsrc_id) 182 { 183 void *p; 184 185 if (!rsrc_table) 186 return true; 187 188 p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num, 189 sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp); 190 191 return p != NULL; 192 } 193 194 int __init imx_clk_scu_module_init(void) 195 { 196 return platform_driver_register(&imx_clk_scu_driver); 197 } 198 199 void __exit imx_clk_scu_module_exit(void) 200 { 201 return platform_driver_unregister(&imx_clk_scu_driver); 202 } 203 204 int imx_clk_scu_init(struct device_node *np, 205 const struct imx_clk_scu_rsrc_table *data) 206 { 207 u32 clk_cells; 208 int ret, i; 209 210 ret = imx_scu_get_handle(&ccm_ipc_handle); 211 if (ret) 212 return ret; 213 214 of_property_read_u32(np, "#clock-cells", &clk_cells); 215 216 if (clk_cells == 2) { 217 for (i = 0; i < IMX_SC_R_LAST; i++) 218 INIT_LIST_HEAD(&imx_scu_clks[i]); 219 220 /* pd_np will be used to attach power domains later */ 221 pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd"); 222 if (!pd_np) 223 return -EINVAL; 224 225 rsrc_table = data; 226 } 227 228 return 0; 229 } 230 231 /* 232 * clk_scu_recalc_rate - Get clock rate for a SCU clock 233 * @hw: clock to get rate for 234 * @parent_rate: parent rate provided by common clock framework, not used 235 * 236 * Gets the current clock rate of a SCU clock. Returns the current 237 * clock rate, or zero in failure. 238 */ 239 static unsigned long clk_scu_recalc_rate(struct clk_hw *hw, 240 unsigned long parent_rate) 241 { 242 struct clk_scu *clk = to_clk_scu(hw); 243 struct imx_sc_msg_get_clock_rate msg; 244 struct imx_sc_rpc_msg *hdr = &msg.hdr; 245 int ret; 246 247 hdr->ver = IMX_SC_RPC_VERSION; 248 hdr->svc = IMX_SC_RPC_SVC_PM; 249 hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_RATE; 250 hdr->size = 2; 251 252 msg.data.req.resource = cpu_to_le16(clk->rsrc_id); 253 msg.data.req.clk = clk->clk_type; 254 255 ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true); 256 if (ret) { 257 pr_err("%s: failed to get clock rate %d\n", 258 clk_hw_get_name(hw), ret); 259 return 0; 260 } 261 262 return le32_to_cpu(msg.data.resp.rate); 263 } 264 265 static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate, 266 unsigned long parent_rate) 267 { 268 struct clk_scu *clk = to_clk_scu(hw); 269 struct arm_smccc_res res; 270 unsigned long cluster_id; 271 272 if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53) 273 cluster_id = 0; 274 else if (clk->rsrc_id == IMX_SC_R_A72) 275 cluster_id = 1; 276 else 277 return -EINVAL; 278 279 /* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */ 280 arm_smccc_smc(IMX_SIP_CPUFREQ, IMX_SIP_SET_CPUFREQ, 281 cluster_id, rate, 0, 0, 0, 0, &res); 282 283 return 0; 284 } 285 286 /* 287 * clk_scu_set_rate - Set rate for a SCU clock 288 * @hw: clock to change rate for 289 * @rate: target rate for the clock 290 * @parent_rate: rate of the clock parent, not used for SCU clocks 291 * 292 * Sets a clock frequency for a SCU clock. Returns the SCU 293 * protocol status. 294 */ 295 static int clk_scu_set_rate(struct clk_hw *hw, unsigned long rate, 296 unsigned long parent_rate) 297 { 298 struct clk_scu *clk = to_clk_scu(hw); 299 struct imx_sc_msg_req_set_clock_rate msg; 300 struct imx_sc_rpc_msg *hdr = &msg.hdr; 301 302 hdr->ver = IMX_SC_RPC_VERSION; 303 hdr->svc = IMX_SC_RPC_SVC_PM; 304 hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_RATE; 305 hdr->size = 3; 306 307 msg.rate = cpu_to_le32(rate); 308 msg.resource = cpu_to_le16(clk->rsrc_id); 309 msg.clk = clk->clk_type; 310 311 return imx_scu_call_rpc(ccm_ipc_handle, &msg, true); 312 } 313 314 static u8 clk_scu_get_parent(struct clk_hw *hw) 315 { 316 struct clk_scu *clk = to_clk_scu(hw); 317 struct imx_sc_msg_get_clock_parent msg; 318 struct imx_sc_rpc_msg *hdr = &msg.hdr; 319 int ret; 320 321 hdr->ver = IMX_SC_RPC_VERSION; 322 hdr->svc = IMX_SC_RPC_SVC_PM; 323 hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_PARENT; 324 hdr->size = 2; 325 326 msg.data.req.resource = cpu_to_le16(clk->rsrc_id); 327 msg.data.req.clk = clk->clk_type; 328 329 ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true); 330 if (ret) { 331 pr_err("%s: failed to get clock parent %d\n", 332 clk_hw_get_name(hw), ret); 333 return 0; 334 } 335 336 clk->parent_index = msg.data.resp.parent; 337 338 return msg.data.resp.parent; 339 } 340 341 static int clk_scu_set_parent(struct clk_hw *hw, u8 index) 342 { 343 struct clk_scu *clk = to_clk_scu(hw); 344 struct imx_sc_msg_set_clock_parent msg; 345 struct imx_sc_rpc_msg *hdr = &msg.hdr; 346 int ret; 347 348 hdr->ver = IMX_SC_RPC_VERSION; 349 hdr->svc = IMX_SC_RPC_SVC_PM; 350 hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_PARENT; 351 hdr->size = 2; 352 353 msg.resource = cpu_to_le16(clk->rsrc_id); 354 msg.clk = clk->clk_type; 355 msg.parent = index; 356 357 ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true); 358 if (ret) { 359 pr_err("%s: failed to set clock parent %d\n", 360 clk_hw_get_name(hw), ret); 361 return ret; 362 } 363 364 clk->parent_index = index; 365 366 return 0; 367 } 368 369 static int sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource, 370 u8 clk, bool enable, bool autog) 371 { 372 struct imx_sc_msg_req_clock_enable msg; 373 struct imx_sc_rpc_msg *hdr = &msg.hdr; 374 375 hdr->ver = IMX_SC_RPC_VERSION; 376 hdr->svc = IMX_SC_RPC_SVC_PM; 377 hdr->func = IMX_SC_PM_FUNC_CLOCK_ENABLE; 378 hdr->size = 3; 379 380 msg.resource = cpu_to_le16(resource); 381 msg.clk = clk; 382 msg.enable = enable; 383 msg.autog = autog; 384 385 return imx_scu_call_rpc(ccm_ipc_handle, &msg, true); 386 } 387 388 /* 389 * clk_scu_prepare - Enable a SCU clock 390 * @hw: clock to enable 391 * 392 * Enable the clock at the DSC slice level 393 */ 394 static int clk_scu_prepare(struct clk_hw *hw) 395 { 396 struct clk_scu *clk = to_clk_scu(hw); 397 398 return sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id, 399 clk->clk_type, true, false); 400 } 401 402 /* 403 * clk_scu_unprepare - Disable a SCU clock 404 * @hw: clock to enable 405 * 406 * Disable the clock at the DSC slice level 407 */ 408 static void clk_scu_unprepare(struct clk_hw *hw) 409 { 410 struct clk_scu *clk = to_clk_scu(hw); 411 int ret; 412 413 ret = sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id, 414 clk->clk_type, false, false); 415 if (ret) 416 pr_warn("%s: clk unprepare failed %d\n", clk_hw_get_name(hw), 417 ret); 418 } 419 420 static const struct clk_ops clk_scu_ops = { 421 .recalc_rate = clk_scu_recalc_rate, 422 .determine_rate = clk_determine_rate_noop, 423 .set_rate = clk_scu_set_rate, 424 .get_parent = clk_scu_get_parent, 425 .set_parent = clk_scu_set_parent, 426 .prepare = clk_scu_prepare, 427 .unprepare = clk_scu_unprepare, 428 }; 429 430 static const struct clk_ops clk_scu_cpu_ops = { 431 .recalc_rate = clk_scu_recalc_rate, 432 .determine_rate = clk_determine_rate_noop, 433 .set_rate = clk_scu_atf_set_cpu_rate, 434 .prepare = clk_scu_prepare, 435 .unprepare = clk_scu_unprepare, 436 }; 437 438 static const struct clk_ops clk_scu_pi_ops = { 439 .recalc_rate = clk_scu_recalc_rate, 440 .determine_rate = clk_determine_rate_noop, 441 .set_rate = clk_scu_set_rate, 442 }; 443 444 struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, 445 const char * const *parents, int num_parents, 446 u32 rsrc_id, u8 clk_type) 447 { 448 struct clk_init_data init; 449 struct clk_scu *clk; 450 struct clk_hw *hw; 451 int ret; 452 453 clk = kzalloc_obj(*clk); 454 if (!clk) 455 return ERR_PTR(-ENOMEM); 456 457 clk->rsrc_id = rsrc_id; 458 clk->clk_type = clk_type; 459 460 init.name = name; 461 if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53 || rsrc_id == IMX_SC_R_A72) 462 init.ops = &clk_scu_cpu_ops; 463 else if (rsrc_id == IMX_SC_R_PI_0_PLL) 464 init.ops = &clk_scu_pi_ops; 465 else 466 init.ops = &clk_scu_ops; 467 init.parent_names = parents; 468 init.num_parents = num_parents; 469 470 /* 471 * Note on MX8, the clocks are tightly coupled with power domain 472 * that once the power domain is off, the clock status may be 473 * lost. So we make it NOCACHE to let user to retrieve the real 474 * clock status from HW instead of using the possible invalid 475 * cached rate. 476 */ 477 init.flags = CLK_GET_RATE_NOCACHE; 478 clk->hw.init = &init; 479 480 hw = &clk->hw; 481 ret = clk_hw_register(dev, hw); 482 if (ret) { 483 kfree(clk); 484 hw = ERR_PTR(ret); 485 return hw; 486 } 487 488 if (dev) 489 dev_set_drvdata(dev, clk); 490 491 return hw; 492 } 493 494 struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec, 495 void *data) 496 { 497 unsigned int rsrc = clkspec->args[0]; 498 unsigned int idx = clkspec->args[1]; 499 struct list_head *scu_clks = data; 500 struct imx_scu_clk_node *clk; 501 502 list_for_each_entry(clk, &scu_clks[rsrc], node) { 503 if (clk->clk_type == idx) 504 return clk->hw; 505 } 506 507 return ERR_PTR(-ENODEV); 508 } 509 510 static int imx_clk_scu_probe(struct platform_device *pdev) 511 { 512 struct device *dev = &pdev->dev; 513 struct imx_scu_clk_node *clk = dev_get_platdata(dev); 514 struct clk_hw *hw; 515 int ret; 516 517 if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) || 518 (clk->rsrc == IMX_SC_R_A72))) { 519 pm_runtime_set_suspended(dev); 520 pm_runtime_set_autosuspend_delay(dev, 50); 521 pm_runtime_use_autosuspend(&pdev->dev); 522 pm_runtime_enable(dev); 523 524 ret = pm_runtime_resume_and_get(dev); 525 if (ret) { 526 pm_genpd_remove_device(dev); 527 pm_runtime_disable(dev); 528 return ret; 529 } 530 } 531 532 hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents, 533 clk->rsrc, clk->clk_type); 534 if (IS_ERR(hw)) { 535 pm_runtime_disable(dev); 536 return PTR_ERR(hw); 537 } 538 539 clk->hw = hw; 540 list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]); 541 542 if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) || 543 (clk->rsrc == IMX_SC_R_A72))) { 544 pm_runtime_put_autosuspend(&pdev->dev); 545 } 546 547 dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc, 548 clk->clk_type); 549 550 return 0; 551 } 552 553 static int __maybe_unused imx_clk_scu_suspend(struct device *dev) 554 { 555 struct clk_scu *clk = dev_get_drvdata(dev); 556 u32 rsrc_id = clk->rsrc_id; 557 558 if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) || 559 (rsrc_id == IMX_SC_R_A72)) 560 return 0; 561 562 clk->parent = clk_hw_get_parent(&clk->hw); 563 564 /* DC SS needs to handle bypass clock using non-cached clock rate */ 565 if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 || 566 clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 || 567 clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 || 568 clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1) 569 clk->rate = clk_scu_recalc_rate(&clk->hw, 0); 570 else 571 clk->rate = clk_hw_get_rate(&clk->hw); 572 clk->is_enabled = clk_hw_is_prepared(&clk->hw); 573 574 if (clk->parent) 575 dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent), 576 clk->parent_index); 577 578 if (clk->rate) 579 dev_dbg(dev, "save rate %d\n", clk->rate); 580 581 if (clk->is_enabled) 582 dev_dbg(dev, "save enabled state\n"); 583 584 return 0; 585 } 586 587 static int __maybe_unused imx_clk_scu_resume(struct device *dev) 588 { 589 struct clk_scu *clk = dev_get_drvdata(dev); 590 u32 rsrc_id = clk->rsrc_id; 591 int ret = 0; 592 593 if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) || 594 (rsrc_id == IMX_SC_R_A72)) 595 return 0; 596 597 if (clk->parent) { 598 ret = clk_scu_set_parent(&clk->hw, clk->parent_index); 599 dev_dbg(dev, "restore parent %s idx %u %s\n", 600 clk_hw_get_name(clk->parent), 601 clk->parent_index, !ret ? "success" : "failed"); 602 } 603 604 if (clk->rate) { 605 ret = clk_scu_set_rate(&clk->hw, clk->rate, 0); 606 dev_dbg(dev, "restore rate %d %s\n", clk->rate, 607 !ret ? "success" : "failed"); 608 } 609 610 if (clk->is_enabled && rsrc_id != IMX_SC_R_PI_0_PLL) { 611 ret = clk_scu_prepare(&clk->hw); 612 dev_dbg(dev, "restore enabled state %s\n", 613 !ret ? "success" : "failed"); 614 } 615 616 return ret; 617 } 618 619 static const struct dev_pm_ops imx_clk_scu_pm_ops = { 620 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_clk_scu_suspend, 621 imx_clk_scu_resume) 622 }; 623 624 static struct platform_driver imx_clk_scu_driver = { 625 .driver = { 626 .name = "imx-scu-clk", 627 .suppress_bind_attrs = true, 628 .pm = &imx_clk_scu_pm_ops, 629 }, 630 .probe = imx_clk_scu_probe, 631 }; 632 633 static int imx_clk_scu_attach_pd(struct device *dev, u32 rsrc_id) 634 { 635 struct of_phandle_args genpdspec = { 636 .np = pd_np, 637 .args_count = 1, 638 .args[0] = rsrc_id, 639 }; 640 641 if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53 || 642 rsrc_id == IMX_SC_R_A72) 643 return 0; 644 645 return of_genpd_add_device(&genpdspec, dev); 646 } 647 648 static bool imx_clk_is_resource_owned(u32 rsrc) 649 { 650 /* 651 * A-core resources are special. SCFW reports they are not "owned" by 652 * current partition but linux can still adjust them for cpufreq. 653 */ 654 if (rsrc == IMX_SC_R_A53 || rsrc == IMX_SC_R_A72 || rsrc == IMX_SC_R_A35) 655 return true; 656 657 return imx_sc_rm_is_resource_owned(ccm_ipc_handle, rsrc); 658 } 659 660 struct clk_hw *imx_clk_scu_alloc_dev(const char *name, 661 const char * const *parents, 662 int num_parents, u32 rsrc_id, u8 clk_type) 663 { 664 struct imx_scu_clk_node clk = { 665 .name = name, 666 .rsrc = rsrc_id, 667 .clk_type = clk_type, 668 .parents = parents, 669 .num_parents = num_parents, 670 }; 671 struct platform_device *pdev; 672 int ret; 673 674 if (!imx_scu_clk_is_valid(rsrc_id)) 675 return ERR_PTR(-EINVAL); 676 677 if (!imx_clk_is_resource_owned(rsrc_id)) 678 return NULL; 679 680 pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE); 681 if (!pdev) { 682 pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n", 683 name, rsrc_id, clk_type); 684 return ERR_PTR(-ENOMEM); 685 } 686 687 ret = platform_device_add_data(pdev, &clk, sizeof(clk)); 688 if (ret) 689 goto put_device; 690 691 ret = device_set_driver_override(&pdev->dev, "imx-scu-clk"); 692 if (ret) 693 goto put_device; 694 695 ret = imx_clk_scu_attach_pd(&pdev->dev, rsrc_id); 696 if (ret) 697 pr_warn("%s: failed to attached the power domain %d\n", 698 name, ret); 699 700 ret = platform_device_add(pdev); 701 if (ret) 702 goto put_device; 703 704 /* For API backwards compatibility, simply return NULL for success */ 705 return NULL; 706 707 put_device: 708 platform_device_put(pdev); 709 return ERR_PTR(ret); 710 } 711 712 void imx_clk_scu_unregister(void) 713 { 714 struct imx_scu_clk_node *clk, *n; 715 int i; 716 717 for (i = 0; i < IMX_SC_R_LAST; i++) { 718 list_for_each_entry_safe(clk, n, &imx_scu_clks[i], node) { 719 clk_hw_unregister(clk->hw); 720 kfree(clk); 721 } 722 } 723 } 724 725 static unsigned long clk_gpr_div_scu_recalc_rate(struct clk_hw *hw, 726 unsigned long parent_rate) 727 { 728 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); 729 unsigned long rate = 0; 730 u32 val; 731 int err; 732 733 err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id, 734 clk->gpr_id, &val); 735 736 rate = val ? parent_rate / 2 : parent_rate; 737 738 return err ? 0 : rate; 739 } 740 741 static int clk_gpr_div_scu_determine_rate(struct clk_hw *hw, 742 struct clk_rate_request *req) 743 { 744 if (req->rate < req->best_parent_rate) 745 req->rate = req->best_parent_rate / 2; 746 else 747 req->rate = req->best_parent_rate; 748 749 return 0; 750 } 751 752 static int clk_gpr_div_scu_set_rate(struct clk_hw *hw, unsigned long rate, 753 unsigned long parent_rate) 754 { 755 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); 756 uint32_t val; 757 int err; 758 759 val = (rate < parent_rate) ? 1 : 0; 760 err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id, 761 clk->gpr_id, val); 762 763 return err ? -EINVAL : 0; 764 } 765 766 static const struct clk_ops clk_gpr_div_scu_ops = { 767 .recalc_rate = clk_gpr_div_scu_recalc_rate, 768 .determine_rate = clk_gpr_div_scu_determine_rate, 769 .set_rate = clk_gpr_div_scu_set_rate, 770 }; 771 772 static u8 clk_gpr_mux_scu_get_parent(struct clk_hw *hw) 773 { 774 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); 775 u32 val = 0; 776 777 imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id, 778 clk->gpr_id, &val); 779 780 return (u8)val; 781 } 782 783 static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index) 784 { 785 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); 786 787 return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id, 788 clk->gpr_id, index); 789 } 790 791 static const struct clk_ops clk_gpr_mux_scu_ops = { 792 .determine_rate = clk_hw_determine_rate_no_reparent, 793 .get_parent = clk_gpr_mux_scu_get_parent, 794 .set_parent = clk_gpr_mux_scu_set_parent, 795 }; 796 797 static int clk_gpr_gate_scu_prepare(struct clk_hw *hw) 798 { 799 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); 800 801 return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id, 802 clk->gpr_id, !clk->gate_invert); 803 } 804 805 static void clk_gpr_gate_scu_unprepare(struct clk_hw *hw) 806 { 807 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); 808 int ret; 809 810 ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id, 811 clk->gpr_id, clk->gate_invert); 812 if (ret) 813 pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw), 814 ret); 815 } 816 817 static int clk_gpr_gate_scu_is_prepared(struct clk_hw *hw) 818 { 819 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); 820 int ret; 821 u32 val; 822 823 ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id, 824 clk->gpr_id, &val); 825 if (ret) 826 return ret; 827 828 return clk->gate_invert ? !val : val; 829 } 830 831 static const struct clk_ops clk_gpr_gate_scu_ops = { 832 .prepare = clk_gpr_gate_scu_prepare, 833 .unprepare = clk_gpr_gate_scu_unprepare, 834 .is_prepared = clk_gpr_gate_scu_is_prepared, 835 }; 836 837 struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name, 838 int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags, 839 bool invert) 840 { 841 struct imx_scu_clk_node *clk_node; 842 struct clk_gpr_scu *clk; 843 struct clk_hw *hw; 844 struct clk_init_data init; 845 int ret; 846 847 if (rsrc_id >= IMX_SC_R_LAST || gpr_id >= IMX_SC_C_LAST) 848 return ERR_PTR(-EINVAL); 849 850 clk_node = kzalloc_obj(*clk_node); 851 if (!clk_node) 852 return ERR_PTR(-ENOMEM); 853 854 if (!imx_scu_clk_is_valid(rsrc_id)) { 855 kfree(clk_node); 856 return ERR_PTR(-EINVAL); 857 } 858 859 if (!imx_clk_is_resource_owned(rsrc_id)) { 860 kfree(clk_node); 861 return NULL; 862 } 863 864 clk = kzalloc_obj(*clk); 865 if (!clk) { 866 kfree(clk_node); 867 return ERR_PTR(-ENOMEM); 868 } 869 870 clk->rsrc_id = rsrc_id; 871 clk->gpr_id = gpr_id; 872 clk->flags = flags; 873 clk->gate_invert = invert; 874 875 if (flags & IMX_SCU_GPR_CLK_GATE) 876 init.ops = &clk_gpr_gate_scu_ops; 877 878 if (flags & IMX_SCU_GPR_CLK_DIV) 879 init.ops = &clk_gpr_div_scu_ops; 880 881 if (flags & IMX_SCU_GPR_CLK_MUX) 882 init.ops = &clk_gpr_mux_scu_ops; 883 884 init.flags = 0; 885 init.name = name; 886 init.parent_names = parent_name; 887 init.num_parents = num_parents; 888 889 clk->hw.init = &init; 890 891 hw = &clk->hw; 892 ret = clk_hw_register(NULL, hw); 893 if (ret) { 894 kfree(clk); 895 kfree(clk_node); 896 hw = ERR_PTR(ret); 897 } else { 898 clk_node->hw = hw; 899 clk_node->clk_type = gpr_id; 900 list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]); 901 } 902 903 return hw; 904 } 905