1d9a8f950SA.s. Dong // SPDX-License-Identifier: GPL-2.0+
2d9a8f950SA.s. Dong /*
3d9a8f950SA.s. Dong * Copyright (C) 2016 Freescale Semiconductor, Inc.
4d9a8f950SA.s. Dong * Copyright 2017~2018 NXP
5d9a8f950SA.s. Dong *
6d9a8f950SA.s. Dong * Author: Dong Aisheng <aisheng.dong@nxp.com>
7d9a8f950SA.s. Dong *
8d9a8f950SA.s. Dong */
9d9a8f950SA.s. Dong
107d6b5e4fSAnson Huang #include <linux/bits.h>
11d9a8f950SA.s. Dong #include <linux/clk-provider.h>
12d9a8f950SA.s. Dong #include <linux/err.h>
1362e59c4eSStephen Boyd #include <linux/io.h>
14d9a8f950SA.s. Dong #include <linux/iopoll.h>
15d9a8f950SA.s. Dong #include <linux/slab.h>
16d9a8f950SA.s. Dong
17d9a8f950SA.s. Dong #include "clk.h"
18d9a8f950SA.s. Dong
19d9a8f950SA.s. Dong /* PLL Control Status Register (xPLLCSR) */
20d9a8f950SA.s. Dong #define PLL_CSR_OFFSET 0x0
21d9a8f950SA.s. Dong #define PLL_VLD BIT(24)
22d9a8f950SA.s. Dong #define PLL_EN BIT(0)
23d9a8f950SA.s. Dong
24d9a8f950SA.s. Dong /* PLL Configuration Register (xPLLCFG) */
25d9a8f950SA.s. Dong #define PLL_CFG_OFFSET 0x08
265f0601c4SJacky Bai #define IMX8ULP_PLL_CFG_OFFSET 0x10
27d9a8f950SA.s. Dong #define BP_PLL_MULT 16
28d9a8f950SA.s. Dong #define BM_PLL_MULT (0x7f << 16)
29d9a8f950SA.s. Dong
30d9a8f950SA.s. Dong /* PLL Numerator Register (xPLLNUM) */
31d9a8f950SA.s. Dong #define PLL_NUM_OFFSET 0x10
325f0601c4SJacky Bai #define IMX8ULP_PLL_NUM_OFFSET 0x1c
33d9a8f950SA.s. Dong
34d9a8f950SA.s. Dong /* PLL Denominator Register (xPLLDENOM) */
35d9a8f950SA.s. Dong #define PLL_DENOM_OFFSET 0x14
365f0601c4SJacky Bai #define IMX8ULP_PLL_DENOM_OFFSET 0x18
37d9a8f950SA.s. Dong
38a048fe99SAnson Huang #define MAX_MFD 0x3fffffff
39a048fe99SAnson Huang #define DEFAULT_MFD 1000000
40a048fe99SAnson Huang
41d9a8f950SA.s. Dong struct clk_pllv4 {
42d9a8f950SA.s. Dong struct clk_hw hw;
43d9a8f950SA.s. Dong void __iomem *base;
445f0601c4SJacky Bai u32 cfg_offset;
455f0601c4SJacky Bai u32 num_offset;
465f0601c4SJacky Bai u32 denom_offset;
47*3f0cdb94SYe Li bool use_mult_range;
48d9a8f950SA.s. Dong };
49d9a8f950SA.s. Dong
50d9a8f950SA.s. Dong /* Valid PLL MULT Table */
51d9a8f950SA.s. Dong static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16};
52d9a8f950SA.s. Dong
53*3f0cdb94SYe Li /* Valid PLL MULT range, (max, min) */
54*3f0cdb94SYe Li static const int pllv4_mult_range[] = {54, 27};
55*3f0cdb94SYe Li
56d9a8f950SA.s. Dong #define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
57d9a8f950SA.s. Dong
58d9a8f950SA.s. Dong #define LOCK_TIMEOUT_US USEC_PER_MSEC
59d9a8f950SA.s. Dong
clk_pllv4_wait_lock(struct clk_pllv4 * pll)60d9a8f950SA.s. Dong static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
61d9a8f950SA.s. Dong {
62d9a8f950SA.s. Dong u32 csr;
63d9a8f950SA.s. Dong
64d9a8f950SA.s. Dong return readl_poll_timeout(pll->base + PLL_CSR_OFFSET,
65d9a8f950SA.s. Dong csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US);
66d9a8f950SA.s. Dong }
67d9a8f950SA.s. Dong
clk_pllv4_is_prepared(struct clk_hw * hw)68d678d83cSPeng Fan static int clk_pllv4_is_prepared(struct clk_hw *hw)
69d9a8f950SA.s. Dong {
70d9a8f950SA.s. Dong struct clk_pllv4 *pll = to_clk_pllv4(hw);
71d9a8f950SA.s. Dong
72d9a8f950SA.s. Dong if (readl_relaxed(pll->base) & PLL_EN)
73d9a8f950SA.s. Dong return 1;
74d9a8f950SA.s. Dong
75d9a8f950SA.s. Dong return 0;
76d9a8f950SA.s. Dong }
77d9a8f950SA.s. Dong
clk_pllv4_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)78d9a8f950SA.s. Dong static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw,
79d9a8f950SA.s. Dong unsigned long parent_rate)
80d9a8f950SA.s. Dong {
81d9a8f950SA.s. Dong struct clk_pllv4 *pll = to_clk_pllv4(hw);
82a048fe99SAnson Huang u32 mult, mfn, mfd;
83a048fe99SAnson Huang u64 temp64;
84d9a8f950SA.s. Dong
855f0601c4SJacky Bai mult = readl_relaxed(pll->base + pll->cfg_offset);
86a048fe99SAnson Huang mult &= BM_PLL_MULT;
87a048fe99SAnson Huang mult >>= BP_PLL_MULT;
88d9a8f950SA.s. Dong
895f0601c4SJacky Bai mfn = readl_relaxed(pll->base + pll->num_offset);
905f0601c4SJacky Bai mfd = readl_relaxed(pll->base + pll->denom_offset);
91a048fe99SAnson Huang temp64 = parent_rate;
92a048fe99SAnson Huang temp64 *= mfn;
93a048fe99SAnson Huang do_div(temp64, mfd);
94a048fe99SAnson Huang
95a048fe99SAnson Huang return (parent_rate * mult) + (u32)temp64;
96d9a8f950SA.s. Dong }
97d9a8f950SA.s. Dong
clk_pllv4_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)98d9a8f950SA.s. Dong static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
99d9a8f950SA.s. Dong unsigned long *prate)
100d9a8f950SA.s. Dong {
101*3f0cdb94SYe Li struct clk_pllv4 *pll = to_clk_pllv4(hw);
102d9a8f950SA.s. Dong unsigned long parent_rate = *prate;
103d9a8f950SA.s. Dong unsigned long round_rate, i;
104a048fe99SAnson Huang u32 mfn, mfd = DEFAULT_MFD;
105a048fe99SAnson Huang bool found = false;
106a048fe99SAnson Huang u64 temp64;
107*3f0cdb94SYe Li u32 mult;
108d9a8f950SA.s. Dong
109*3f0cdb94SYe Li if (pll->use_mult_range) {
110*3f0cdb94SYe Li temp64 = (u64)rate;
111*3f0cdb94SYe Li do_div(temp64, parent_rate);
112*3f0cdb94SYe Li mult = temp64;
113*3f0cdb94SYe Li if (mult >= pllv4_mult_range[1] &&
114*3f0cdb94SYe Li mult <= pllv4_mult_range[0]) {
115*3f0cdb94SYe Li round_rate = parent_rate * mult;
116*3f0cdb94SYe Li found = true;
117*3f0cdb94SYe Li }
118*3f0cdb94SYe Li } else {
119d9a8f950SA.s. Dong for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
120d9a8f950SA.s. Dong round_rate = parent_rate * pllv4_mult_table[i];
121a048fe99SAnson Huang if (rate >= round_rate) {
122a048fe99SAnson Huang found = true;
123a048fe99SAnson Huang break;
124a048fe99SAnson Huang }
125d9a8f950SA.s. Dong }
126*3f0cdb94SYe Li }
127d9a8f950SA.s. Dong
128a048fe99SAnson Huang if (!found) {
129a048fe99SAnson Huang pr_warn("%s: unable to round rate %lu, parent rate %lu\n",
130a048fe99SAnson Huang clk_hw_get_name(hw), rate, parent_rate);
131a048fe99SAnson Huang return 0;
132a048fe99SAnson Huang }
133a048fe99SAnson Huang
134a048fe99SAnson Huang if (parent_rate <= MAX_MFD)
135a048fe99SAnson Huang mfd = parent_rate;
136a048fe99SAnson Huang
137a048fe99SAnson Huang temp64 = (u64)(rate - round_rate);
138a048fe99SAnson Huang temp64 *= mfd;
139a048fe99SAnson Huang do_div(temp64, parent_rate);
140a048fe99SAnson Huang mfn = temp64;
141a048fe99SAnson Huang
142a048fe99SAnson Huang /*
143a048fe99SAnson Huang * NOTE: The value of numerator must always be configured to be
144a048fe99SAnson Huang * less than the value of the denominator. If we can't get a proper
145a048fe99SAnson Huang * pair of mfn/mfd, we simply return the round_rate without using
146a048fe99SAnson Huang * the frac part.
147a048fe99SAnson Huang */
148a048fe99SAnson Huang if (mfn >= mfd)
149d9a8f950SA.s. Dong return round_rate;
150a048fe99SAnson Huang
151a048fe99SAnson Huang temp64 = (u64)parent_rate;
152a048fe99SAnson Huang temp64 *= mfn;
153a048fe99SAnson Huang do_div(temp64, mfd);
154a048fe99SAnson Huang
155a048fe99SAnson Huang return round_rate + (u32)temp64;
156d9a8f950SA.s. Dong }
157d9a8f950SA.s. Dong
clk_pllv4_is_valid_mult(struct clk_pllv4 * pll,unsigned int mult)158*3f0cdb94SYe Li static bool clk_pllv4_is_valid_mult(struct clk_pllv4 *pll, unsigned int mult)
159d9a8f950SA.s. Dong {
160d9a8f950SA.s. Dong int i;
161d9a8f950SA.s. Dong
162d9a8f950SA.s. Dong /* check if mult is in valid MULT table */
163*3f0cdb94SYe Li if (pll->use_mult_range) {
164*3f0cdb94SYe Li if (mult >= pllv4_mult_range[1] &&
165*3f0cdb94SYe Li mult <= pllv4_mult_range[0])
166*3f0cdb94SYe Li return true;
167*3f0cdb94SYe Li } else {
168d9a8f950SA.s. Dong for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
169d9a8f950SA.s. Dong if (pllv4_mult_table[i] == mult)
170d9a8f950SA.s. Dong return true;
171d9a8f950SA.s. Dong }
172*3f0cdb94SYe Li }
173d9a8f950SA.s. Dong
174d9a8f950SA.s. Dong return false;
175d9a8f950SA.s. Dong }
176d9a8f950SA.s. Dong
clk_pllv4_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)177d9a8f950SA.s. Dong static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
178d9a8f950SA.s. Dong unsigned long parent_rate)
179d9a8f950SA.s. Dong {
180d9a8f950SA.s. Dong struct clk_pllv4 *pll = to_clk_pllv4(hw);
181a048fe99SAnson Huang u32 val, mult, mfn, mfd = DEFAULT_MFD;
182a048fe99SAnson Huang u64 temp64;
183d9a8f950SA.s. Dong
184d9a8f950SA.s. Dong mult = rate / parent_rate;
185d9a8f950SA.s. Dong
186*3f0cdb94SYe Li if (!clk_pllv4_is_valid_mult(pll, mult))
187d9a8f950SA.s. Dong return -EINVAL;
188d9a8f950SA.s. Dong
189a048fe99SAnson Huang if (parent_rate <= MAX_MFD)
190a048fe99SAnson Huang mfd = parent_rate;
191a048fe99SAnson Huang
192a048fe99SAnson Huang temp64 = (u64)(rate - mult * parent_rate);
193a048fe99SAnson Huang temp64 *= mfd;
194a048fe99SAnson Huang do_div(temp64, parent_rate);
195a048fe99SAnson Huang mfn = temp64;
196a048fe99SAnson Huang
1975f0601c4SJacky Bai val = readl_relaxed(pll->base + pll->cfg_offset);
198d9a8f950SA.s. Dong val &= ~BM_PLL_MULT;
199d9a8f950SA.s. Dong val |= mult << BP_PLL_MULT;
2005f0601c4SJacky Bai writel_relaxed(val, pll->base + pll->cfg_offset);
201d9a8f950SA.s. Dong
2025f0601c4SJacky Bai writel_relaxed(mfn, pll->base + pll->num_offset);
2035f0601c4SJacky Bai writel_relaxed(mfd, pll->base + pll->denom_offset);
204a048fe99SAnson Huang
205d9a8f950SA.s. Dong return 0;
206d9a8f950SA.s. Dong }
207d9a8f950SA.s. Dong
clk_pllv4_prepare(struct clk_hw * hw)208d678d83cSPeng Fan static int clk_pllv4_prepare(struct clk_hw *hw)
209d9a8f950SA.s. Dong {
210d9a8f950SA.s. Dong u32 val;
211d9a8f950SA.s. Dong struct clk_pllv4 *pll = to_clk_pllv4(hw);
212d9a8f950SA.s. Dong
213d9a8f950SA.s. Dong val = readl_relaxed(pll->base);
214d9a8f950SA.s. Dong val |= PLL_EN;
215d9a8f950SA.s. Dong writel_relaxed(val, pll->base);
216d9a8f950SA.s. Dong
217d9a8f950SA.s. Dong return clk_pllv4_wait_lock(pll);
218d9a8f950SA.s. Dong }
219d9a8f950SA.s. Dong
clk_pllv4_unprepare(struct clk_hw * hw)220d678d83cSPeng Fan static void clk_pllv4_unprepare(struct clk_hw *hw)
221d9a8f950SA.s. Dong {
222d9a8f950SA.s. Dong u32 val;
223d9a8f950SA.s. Dong struct clk_pllv4 *pll = to_clk_pllv4(hw);
224d9a8f950SA.s. Dong
225d9a8f950SA.s. Dong val = readl_relaxed(pll->base);
226d9a8f950SA.s. Dong val &= ~PLL_EN;
227d9a8f950SA.s. Dong writel_relaxed(val, pll->base);
228d9a8f950SA.s. Dong }
229d9a8f950SA.s. Dong
230d9a8f950SA.s. Dong static const struct clk_ops clk_pllv4_ops = {
231d9a8f950SA.s. Dong .recalc_rate = clk_pllv4_recalc_rate,
232d9a8f950SA.s. Dong .round_rate = clk_pllv4_round_rate,
233d9a8f950SA.s. Dong .set_rate = clk_pllv4_set_rate,
234d678d83cSPeng Fan .prepare = clk_pllv4_prepare,
235d678d83cSPeng Fan .unprepare = clk_pllv4_unprepare,
236d678d83cSPeng Fan .is_prepared = clk_pllv4_is_prepared,
237d9a8f950SA.s. Dong };
238d9a8f950SA.s. Dong
imx_clk_hw_pllv4(enum imx_pllv4_type type,const char * name,const char * parent_name,void __iomem * base)2395f0601c4SJacky Bai struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name,
2405f0601c4SJacky Bai const char *parent_name, void __iomem *base)
241d9a8f950SA.s. Dong {
242d9a8f950SA.s. Dong struct clk_pllv4 *pll;
243d9a8f950SA.s. Dong struct clk_hw *hw;
244d9a8f950SA.s. Dong struct clk_init_data init;
245d9a8f950SA.s. Dong int ret;
246d9a8f950SA.s. Dong
247d9a8f950SA.s. Dong pll = kzalloc(sizeof(*pll), GFP_KERNEL);
248d9a8f950SA.s. Dong if (!pll)
249d9a8f950SA.s. Dong return ERR_PTR(-ENOMEM);
250d9a8f950SA.s. Dong
251d9a8f950SA.s. Dong pll->base = base;
252d9a8f950SA.s. Dong
253*3f0cdb94SYe Li if (type == IMX_PLLV4_IMX8ULP ||
254*3f0cdb94SYe Li type == IMX_PLLV4_IMX8ULP_1GHZ) {
2555f0601c4SJacky Bai pll->cfg_offset = IMX8ULP_PLL_CFG_OFFSET;
2565f0601c4SJacky Bai pll->num_offset = IMX8ULP_PLL_NUM_OFFSET;
2575f0601c4SJacky Bai pll->denom_offset = IMX8ULP_PLL_DENOM_OFFSET;
258*3f0cdb94SYe Li if (type == IMX_PLLV4_IMX8ULP_1GHZ)
259*3f0cdb94SYe Li pll->use_mult_range = true;
2605f0601c4SJacky Bai } else {
2615f0601c4SJacky Bai pll->cfg_offset = PLL_CFG_OFFSET;
2625f0601c4SJacky Bai pll->num_offset = PLL_NUM_OFFSET;
2635f0601c4SJacky Bai pll->denom_offset = PLL_DENOM_OFFSET;
2645f0601c4SJacky Bai }
2655f0601c4SJacky Bai
266d9a8f950SA.s. Dong init.name = name;
267d9a8f950SA.s. Dong init.ops = &clk_pllv4_ops;
268d9a8f950SA.s. Dong init.parent_names = &parent_name;
269d9a8f950SA.s. Dong init.num_parents = 1;
270d9a8f950SA.s. Dong init.flags = CLK_SET_RATE_GATE;
271d9a8f950SA.s. Dong
272d9a8f950SA.s. Dong pll->hw.init = &init;
273d9a8f950SA.s. Dong
274d9a8f950SA.s. Dong hw = &pll->hw;
275d9a8f950SA.s. Dong ret = clk_hw_register(NULL, hw);
276d9a8f950SA.s. Dong if (ret) {
277d9a8f950SA.s. Dong kfree(pll);
278d9a8f950SA.s. Dong hw = ERR_PTR(ret);
279d9a8f950SA.s. Dong }
280d9a8f950SA.s. Dong
281d9a8f950SA.s. Dong return hw;
282d9a8f950SA.s. Dong }
283d4e6c054SJacky Bai EXPORT_SYMBOL_GPL(imx_clk_hw_pllv4);
284