1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2012 Freescale Semiconductor, Inc. 4 * Copyright 2012 Linaro Ltd. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/slab.h> 13 #include <linux/jiffies.h> 14 #include <linux/err.h> 15 #include "clk.h" 16 17 #define PLL_NUM_OFFSET 0x10 18 #define PLL_DENOM_OFFSET 0x20 19 #define PLL_IMX7_NUM_OFFSET 0x20 20 #define PLL_IMX7_DENOM_OFFSET 0x30 21 22 #define PLL_VF610_NUM_OFFSET 0x20 23 #define PLL_VF610_DENOM_OFFSET 0x30 24 25 #define BM_PLL_POWER (0x1 << 12) 26 #define BM_PLL_LOCK (0x1 << 31) 27 #define IMX7_ENET_PLL_POWER (0x1 << 5) 28 #define IMX7_DDR_PLL_POWER (0x1 << 20) 29 30 #define PLL_LOCK_TIMEOUT 10000 31 32 /** 33 * struct clk_pllv3 - IMX PLL clock version 3 34 * @hw: clock source 35 * @base: base address of PLL registers 36 * @power_bit: pll power bit mask 37 * @powerup_set: set power_bit to power up the PLL 38 * @div_mask: mask of divider bits 39 * @div_shift: shift of divider bits 40 * @ref_clock: reference clock rate 41 * @num_offset: num register offset 42 * @denom_offset: denom register offset 43 * 44 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 45 * is actually a multiplier, and always sits at bit 0. 46 */ 47 struct clk_pllv3 { 48 struct clk_hw hw; 49 void __iomem *base; 50 u32 power_bit; 51 bool powerup_set; 52 u32 div_mask; 53 u32 div_shift; 54 unsigned long ref_clock; 55 u32 num_offset; 56 u32 denom_offset; 57 }; 58 59 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) 60 61 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) 62 { 63 u32 val = readl_relaxed(pll->base) & pll->power_bit; 64 65 /* No need to wait for lock when pll is not powered up */ 66 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) 67 return 0; 68 69 return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK, 70 500, PLL_LOCK_TIMEOUT); 71 } 72 73 static int clk_pllv3_prepare(struct clk_hw *hw) 74 { 75 struct clk_pllv3 *pll = to_clk_pllv3(hw); 76 u32 val; 77 78 val = readl_relaxed(pll->base); 79 if (pll->powerup_set) 80 val |= pll->power_bit; 81 else 82 val &= ~pll->power_bit; 83 writel_relaxed(val, pll->base); 84 85 return clk_pllv3_wait_lock(pll); 86 } 87 88 static void clk_pllv3_unprepare(struct clk_hw *hw) 89 { 90 struct clk_pllv3 *pll = to_clk_pllv3(hw); 91 u32 val; 92 93 val = readl_relaxed(pll->base); 94 if (pll->powerup_set) 95 val &= ~pll->power_bit; 96 else 97 val |= pll->power_bit; 98 writel_relaxed(val, pll->base); 99 } 100 101 static int clk_pllv3_is_prepared(struct clk_hw *hw) 102 { 103 struct clk_pllv3 *pll = to_clk_pllv3(hw); 104 105 if (readl_relaxed(pll->base) & BM_PLL_LOCK) 106 return 1; 107 108 return 0; 109 } 110 111 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, 112 unsigned long parent_rate) 113 { 114 struct clk_pllv3 *pll = to_clk_pllv3(hw); 115 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; 116 117 return (div == 1) ? parent_rate * 22 : parent_rate * 20; 118 } 119 120 static int clk_pllv3_determine_rate(struct clk_hw *hw, 121 struct clk_rate_request *req) 122 { 123 unsigned long parent_rate = req->best_parent_rate; 124 125 req->rate = (req->rate >= parent_rate * 22) ? parent_rate * 22 : parent_rate * 20; 126 127 return 0; 128 } 129 130 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, 131 unsigned long parent_rate) 132 { 133 struct clk_pllv3 *pll = to_clk_pllv3(hw); 134 u32 val, div; 135 136 if (rate == parent_rate * 22) 137 div = 1; 138 else if (rate == parent_rate * 20) 139 div = 0; 140 else 141 return -EINVAL; 142 143 val = readl_relaxed(pll->base); 144 val &= ~(pll->div_mask << pll->div_shift); 145 val |= (div << pll->div_shift); 146 writel_relaxed(val, pll->base); 147 148 return clk_pllv3_wait_lock(pll); 149 } 150 151 static const struct clk_ops clk_pllv3_ops = { 152 .prepare = clk_pllv3_prepare, 153 .unprepare = clk_pllv3_unprepare, 154 .is_prepared = clk_pllv3_is_prepared, 155 .recalc_rate = clk_pllv3_recalc_rate, 156 .determine_rate = clk_pllv3_determine_rate, 157 .set_rate = clk_pllv3_set_rate, 158 }; 159 160 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw, 161 unsigned long parent_rate) 162 { 163 struct clk_pllv3 *pll = to_clk_pllv3(hw); 164 u32 div = readl_relaxed(pll->base) & pll->div_mask; 165 166 return parent_rate * div / 2; 167 } 168 169 static int clk_pllv3_sys_determine_rate(struct clk_hw *hw, 170 struct clk_rate_request *req) 171 { 172 unsigned long parent_rate = req->best_parent_rate; 173 unsigned long min_rate = parent_rate * 54 / 2; 174 unsigned long max_rate = parent_rate * 108 / 2; 175 u32 div; 176 177 if (req->rate > max_rate) 178 req->rate = max_rate; 179 else if (req->rate < min_rate) 180 req->rate = min_rate; 181 div = req->rate * 2 / parent_rate; 182 183 req->rate = parent_rate * div / 2; 184 185 return 0; 186 } 187 188 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, 189 unsigned long parent_rate) 190 { 191 struct clk_pllv3 *pll = to_clk_pllv3(hw); 192 unsigned long min_rate = parent_rate * 54 / 2; 193 unsigned long max_rate = parent_rate * 108 / 2; 194 u32 val, div; 195 196 if (rate < min_rate || rate > max_rate) 197 return -EINVAL; 198 199 div = rate * 2 / parent_rate; 200 val = readl_relaxed(pll->base); 201 val &= ~pll->div_mask; 202 val |= div; 203 writel_relaxed(val, pll->base); 204 205 return clk_pllv3_wait_lock(pll); 206 } 207 208 static const struct clk_ops clk_pllv3_sys_ops = { 209 .prepare = clk_pllv3_prepare, 210 .unprepare = clk_pllv3_unprepare, 211 .is_prepared = clk_pllv3_is_prepared, 212 .recalc_rate = clk_pllv3_sys_recalc_rate, 213 .determine_rate = clk_pllv3_sys_determine_rate, 214 .set_rate = clk_pllv3_sys_set_rate, 215 }; 216 217 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, 218 unsigned long parent_rate) 219 { 220 struct clk_pllv3 *pll = to_clk_pllv3(hw); 221 u32 mfn = readl_relaxed(pll->base + pll->num_offset); 222 u32 mfd = readl_relaxed(pll->base + pll->denom_offset); 223 u32 div = readl_relaxed(pll->base) & pll->div_mask; 224 u64 temp64 = (u64)parent_rate; 225 226 temp64 *= mfn; 227 do_div(temp64, mfd); 228 229 return parent_rate * div + (unsigned long)temp64; 230 } 231 232 static int clk_pllv3_av_determine_rate(struct clk_hw *hw, 233 struct clk_rate_request *req) 234 { 235 unsigned long parent_rate = req->best_parent_rate; 236 unsigned long min_rate = parent_rate * 27; 237 unsigned long max_rate = parent_rate * 54; 238 u32 div; 239 u32 mfn, mfd = 1000000; 240 u32 max_mfd = 0x3FFFFFFF; 241 u64 temp64; 242 243 if (req->rate > max_rate) 244 req->rate = max_rate; 245 else if (req->rate < min_rate) 246 req->rate = min_rate; 247 248 if (parent_rate <= max_mfd) 249 mfd = parent_rate; 250 251 div = req->rate / parent_rate; 252 temp64 = (u64) (req->rate - div * parent_rate); 253 temp64 *= mfd; 254 temp64 = div64_ul(temp64, parent_rate); 255 mfn = temp64; 256 257 temp64 = (u64)parent_rate; 258 temp64 *= mfn; 259 do_div(temp64, mfd); 260 261 req->rate = parent_rate * div + (unsigned long)temp64; 262 263 return 0; 264 } 265 266 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, 267 unsigned long parent_rate) 268 { 269 struct clk_pllv3 *pll = to_clk_pllv3(hw); 270 unsigned long min_rate = parent_rate * 27; 271 unsigned long max_rate = parent_rate * 54; 272 u32 val, div; 273 u32 mfn, mfd = 1000000; 274 u32 max_mfd = 0x3FFFFFFF; 275 u64 temp64; 276 277 if (rate < min_rate || rate > max_rate) 278 return -EINVAL; 279 280 if (parent_rate <= max_mfd) 281 mfd = parent_rate; 282 283 div = rate / parent_rate; 284 temp64 = (u64) (rate - div * parent_rate); 285 temp64 *= mfd; 286 temp64 = div64_ul(temp64, parent_rate); 287 mfn = temp64; 288 289 val = readl_relaxed(pll->base); 290 val &= ~pll->div_mask; 291 val |= div; 292 writel_relaxed(val, pll->base); 293 writel_relaxed(mfn, pll->base + pll->num_offset); 294 writel_relaxed(mfd, pll->base + pll->denom_offset); 295 296 return clk_pllv3_wait_lock(pll); 297 } 298 299 static const struct clk_ops clk_pllv3_av_ops = { 300 .prepare = clk_pllv3_prepare, 301 .unprepare = clk_pllv3_unprepare, 302 .is_prepared = clk_pllv3_is_prepared, 303 .recalc_rate = clk_pllv3_av_recalc_rate, 304 .determine_rate = clk_pllv3_av_determine_rate, 305 .set_rate = clk_pllv3_av_set_rate, 306 }; 307 308 struct clk_pllv3_vf610_mf { 309 u32 mfi; /* integer part, can be 20 or 22 */ 310 u32 mfn; /* numerator, 30-bit value */ 311 u32 mfd; /* denominator, 30-bit value, must be less than mfn */ 312 }; 313 314 static unsigned long clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate, 315 struct clk_pllv3_vf610_mf mf) 316 { 317 u64 temp64; 318 319 temp64 = parent_rate; 320 temp64 *= mf.mfn; 321 do_div(temp64, mf.mfd); 322 323 return (parent_rate * mf.mfi) + temp64; 324 } 325 326 static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf( 327 unsigned long parent_rate, unsigned long rate) 328 { 329 struct clk_pllv3_vf610_mf mf; 330 u64 temp64; 331 332 mf.mfi = (rate >= 22 * parent_rate) ? 22 : 20; 333 mf.mfd = 0x3fffffff; /* use max supported value for best accuracy */ 334 335 if (rate <= parent_rate * mf.mfi) 336 mf.mfn = 0; 337 else if (rate >= parent_rate * (mf.mfi + 1)) 338 mf.mfn = mf.mfd - 1; 339 else { 340 /* rate = parent_rate * (mfi + mfn/mfd) */ 341 temp64 = rate - parent_rate * mf.mfi; 342 temp64 *= mf.mfd; 343 temp64 = div64_ul(temp64, parent_rate); 344 mf.mfn = temp64; 345 } 346 347 return mf; 348 } 349 350 static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw, 351 unsigned long parent_rate) 352 { 353 struct clk_pllv3 *pll = to_clk_pllv3(hw); 354 struct clk_pllv3_vf610_mf mf; 355 356 mf.mfn = readl_relaxed(pll->base + pll->num_offset); 357 mf.mfd = readl_relaxed(pll->base + pll->denom_offset); 358 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20; 359 360 return clk_pllv3_vf610_mf_to_rate(parent_rate, mf); 361 } 362 363 static int clk_pllv3_vf610_determine_rate(struct clk_hw *hw, 364 struct clk_rate_request *req) 365 { 366 struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(req->best_parent_rate, 367 req->rate); 368 369 req->rate = clk_pllv3_vf610_mf_to_rate(req->best_parent_rate, mf); 370 371 return 0; 372 } 373 374 static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate, 375 unsigned long parent_rate) 376 { 377 struct clk_pllv3 *pll = to_clk_pllv3(hw); 378 struct clk_pllv3_vf610_mf mf = 379 clk_pllv3_vf610_rate_to_mf(parent_rate, rate); 380 u32 val; 381 382 val = readl_relaxed(pll->base); 383 if (mf.mfi == 20) 384 val &= ~pll->div_mask; /* clear bit for mfi=20 */ 385 else 386 val |= pll->div_mask; /* set bit for mfi=22 */ 387 writel_relaxed(val, pll->base); 388 389 writel_relaxed(mf.mfn, pll->base + pll->num_offset); 390 writel_relaxed(mf.mfd, pll->base + pll->denom_offset); 391 392 return clk_pllv3_wait_lock(pll); 393 } 394 395 static const struct clk_ops clk_pllv3_vf610_ops = { 396 .prepare = clk_pllv3_prepare, 397 .unprepare = clk_pllv3_unprepare, 398 .is_prepared = clk_pllv3_is_prepared, 399 .recalc_rate = clk_pllv3_vf610_recalc_rate, 400 .determine_rate = clk_pllv3_vf610_determine_rate, 401 .set_rate = clk_pllv3_vf610_set_rate, 402 }; 403 404 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, 405 unsigned long parent_rate) 406 { 407 struct clk_pllv3 *pll = to_clk_pllv3(hw); 408 409 return pll->ref_clock; 410 } 411 412 static const struct clk_ops clk_pllv3_enet_ops = { 413 .prepare = clk_pllv3_prepare, 414 .unprepare = clk_pllv3_unprepare, 415 .is_prepared = clk_pllv3_is_prepared, 416 .recalc_rate = clk_pllv3_enet_recalc_rate, 417 }; 418 419 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, 420 const char *parent_name, void __iomem *base, 421 u32 div_mask) 422 { 423 struct clk_pllv3 *pll; 424 const struct clk_ops *ops; 425 struct clk_hw *hw; 426 struct clk_init_data init; 427 int ret; 428 429 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 430 if (!pll) 431 return ERR_PTR(-ENOMEM); 432 433 pll->power_bit = BM_PLL_POWER; 434 pll->num_offset = PLL_NUM_OFFSET; 435 pll->denom_offset = PLL_DENOM_OFFSET; 436 437 switch (type) { 438 case IMX_PLLV3_SYS: 439 ops = &clk_pllv3_sys_ops; 440 break; 441 case IMX_PLLV3_SYS_VF610: 442 ops = &clk_pllv3_vf610_ops; 443 pll->num_offset = PLL_VF610_NUM_OFFSET; 444 pll->denom_offset = PLL_VF610_DENOM_OFFSET; 445 break; 446 case IMX_PLLV3_USB_VF610: 447 pll->div_shift = 1; 448 fallthrough; 449 case IMX_PLLV3_USB: 450 ops = &clk_pllv3_ops; 451 pll->powerup_set = true; 452 break; 453 case IMX_PLLV3_AV_IMX7: 454 pll->num_offset = PLL_IMX7_NUM_OFFSET; 455 pll->denom_offset = PLL_IMX7_DENOM_OFFSET; 456 fallthrough; 457 case IMX_PLLV3_AV: 458 ops = &clk_pllv3_av_ops; 459 break; 460 case IMX_PLLV3_ENET_IMX7: 461 pll->power_bit = IMX7_ENET_PLL_POWER; 462 pll->ref_clock = 1000000000; 463 ops = &clk_pllv3_enet_ops; 464 break; 465 case IMX_PLLV3_ENET: 466 pll->ref_clock = 500000000; 467 ops = &clk_pllv3_enet_ops; 468 break; 469 case IMX_PLLV3_DDR_IMX7: 470 pll->power_bit = IMX7_DDR_PLL_POWER; 471 pll->num_offset = PLL_IMX7_NUM_OFFSET; 472 pll->denom_offset = PLL_IMX7_DENOM_OFFSET; 473 ops = &clk_pllv3_av_ops; 474 break; 475 default: 476 ops = &clk_pllv3_ops; 477 } 478 pll->base = base; 479 pll->div_mask = div_mask; 480 481 init.name = name; 482 init.ops = ops; 483 init.flags = 0; 484 init.parent_names = &parent_name; 485 init.num_parents = 1; 486 487 pll->hw.init = &init; 488 hw = &pll->hw; 489 490 ret = clk_hw_register(NULL, hw); 491 if (ret) { 492 kfree(pll); 493 return ERR_PTR(ret); 494 } 495 496 return hw; 497 } 498 EXPORT_SYMBOL_GPL(imx_clk_hw_pllv3); 499