1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * Copyright 2012 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/delay.h> 16 #include <linux/io.h> 17 #include <linux/slab.h> 18 #include <linux/jiffies.h> 19 #include <linux/err.h> 20 #include "clk.h" 21 22 #define PLL_NUM_OFFSET 0x10 23 #define PLL_DENOM_OFFSET 0x20 24 25 #define BM_PLL_POWER (0x1 << 12) 26 #define BM_PLL_LOCK (0x1 << 31) 27 #define IMX7_ENET_PLL_POWER (0x1 << 5) 28 29 /** 30 * struct clk_pllv3 - IMX PLL clock version 3 31 * @clk_hw: clock source 32 * @base: base address of PLL registers 33 * @powerup_set: set POWER bit to power up the PLL 34 * @powerdown: pll powerdown offset bit 35 * @div_mask: mask of divider bits 36 * @div_shift: shift of divider bits 37 * 38 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 39 * is actually a multiplier, and always sits at bit 0. 40 */ 41 struct clk_pllv3 { 42 struct clk_hw hw; 43 void __iomem *base; 44 bool powerup_set; 45 u32 powerdown; 46 u32 div_mask; 47 u32 div_shift; 48 }; 49 50 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) 51 52 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) 53 { 54 unsigned long timeout = jiffies + msecs_to_jiffies(10); 55 u32 val = readl_relaxed(pll->base) & pll->powerdown; 56 57 /* No need to wait for lock when pll is not powered up */ 58 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) 59 return 0; 60 61 /* Wait for PLL to lock */ 62 do { 63 if (readl_relaxed(pll->base) & BM_PLL_LOCK) 64 break; 65 if (time_after(jiffies, timeout)) 66 break; 67 usleep_range(50, 500); 68 } while (1); 69 70 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; 71 } 72 73 static int clk_pllv3_prepare(struct clk_hw *hw) 74 { 75 struct clk_pllv3 *pll = to_clk_pllv3(hw); 76 u32 val; 77 78 val = readl_relaxed(pll->base); 79 if (pll->powerup_set) 80 val |= BM_PLL_POWER; 81 else 82 val &= ~BM_PLL_POWER; 83 writel_relaxed(val, pll->base); 84 85 return clk_pllv3_wait_lock(pll); 86 } 87 88 static void clk_pllv3_unprepare(struct clk_hw *hw) 89 { 90 struct clk_pllv3 *pll = to_clk_pllv3(hw); 91 u32 val; 92 93 val = readl_relaxed(pll->base); 94 if (pll->powerup_set) 95 val &= ~BM_PLL_POWER; 96 else 97 val |= BM_PLL_POWER; 98 writel_relaxed(val, pll->base); 99 } 100 101 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, 102 unsigned long parent_rate) 103 { 104 struct clk_pllv3 *pll = to_clk_pllv3(hw); 105 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; 106 107 return (div == 1) ? parent_rate * 22 : parent_rate * 20; 108 } 109 110 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate, 111 unsigned long *prate) 112 { 113 unsigned long parent_rate = *prate; 114 115 return (rate >= parent_rate * 22) ? parent_rate * 22 : 116 parent_rate * 20; 117 } 118 119 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, 120 unsigned long parent_rate) 121 { 122 struct clk_pllv3 *pll = to_clk_pllv3(hw); 123 u32 val, div; 124 125 if (rate == parent_rate * 22) 126 div = 1; 127 else if (rate == parent_rate * 20) 128 div = 0; 129 else 130 return -EINVAL; 131 132 val = readl_relaxed(pll->base); 133 val &= ~(pll->div_mask << pll->div_shift); 134 val |= (div << pll->div_shift); 135 writel_relaxed(val, pll->base); 136 137 return clk_pllv3_wait_lock(pll); 138 } 139 140 static const struct clk_ops clk_pllv3_ops = { 141 .prepare = clk_pllv3_prepare, 142 .unprepare = clk_pllv3_unprepare, 143 .recalc_rate = clk_pllv3_recalc_rate, 144 .round_rate = clk_pllv3_round_rate, 145 .set_rate = clk_pllv3_set_rate, 146 }; 147 148 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw, 149 unsigned long parent_rate) 150 { 151 struct clk_pllv3 *pll = to_clk_pllv3(hw); 152 u32 div = readl_relaxed(pll->base) & pll->div_mask; 153 154 return parent_rate * div / 2; 155 } 156 157 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate, 158 unsigned long *prate) 159 { 160 unsigned long parent_rate = *prate; 161 unsigned long min_rate = parent_rate * 54 / 2; 162 unsigned long max_rate = parent_rate * 108 / 2; 163 u32 div; 164 165 if (rate > max_rate) 166 rate = max_rate; 167 else if (rate < min_rate) 168 rate = min_rate; 169 div = rate * 2 / parent_rate; 170 171 return parent_rate * div / 2; 172 } 173 174 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, 175 unsigned long parent_rate) 176 { 177 struct clk_pllv3 *pll = to_clk_pllv3(hw); 178 unsigned long min_rate = parent_rate * 54 / 2; 179 unsigned long max_rate = parent_rate * 108 / 2; 180 u32 val, div; 181 182 if (rate < min_rate || rate > max_rate) 183 return -EINVAL; 184 185 div = rate * 2 / parent_rate; 186 val = readl_relaxed(pll->base); 187 val &= ~pll->div_mask; 188 val |= div; 189 writel_relaxed(val, pll->base); 190 191 return clk_pllv3_wait_lock(pll); 192 } 193 194 static const struct clk_ops clk_pllv3_sys_ops = { 195 .prepare = clk_pllv3_prepare, 196 .unprepare = clk_pllv3_unprepare, 197 .recalc_rate = clk_pllv3_sys_recalc_rate, 198 .round_rate = clk_pllv3_sys_round_rate, 199 .set_rate = clk_pllv3_sys_set_rate, 200 }; 201 202 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, 203 unsigned long parent_rate) 204 { 205 struct clk_pllv3 *pll = to_clk_pllv3(hw); 206 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); 207 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); 208 u32 div = readl_relaxed(pll->base) & pll->div_mask; 209 210 return (parent_rate * div) + ((parent_rate / mfd) * mfn); 211 } 212 213 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, 214 unsigned long *prate) 215 { 216 unsigned long parent_rate = *prate; 217 unsigned long min_rate = parent_rate * 27; 218 unsigned long max_rate = parent_rate * 54; 219 u32 div; 220 u32 mfn, mfd = 1000000; 221 u64 temp64; 222 223 if (rate > max_rate) 224 rate = max_rate; 225 else if (rate < min_rate) 226 rate = min_rate; 227 228 div = rate / parent_rate; 229 temp64 = (u64) (rate - div * parent_rate); 230 temp64 *= mfd; 231 do_div(temp64, parent_rate); 232 mfn = temp64; 233 234 return parent_rate * div + parent_rate / mfd * mfn; 235 } 236 237 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, 238 unsigned long parent_rate) 239 { 240 struct clk_pllv3 *pll = to_clk_pllv3(hw); 241 unsigned long min_rate = parent_rate * 27; 242 unsigned long max_rate = parent_rate * 54; 243 u32 val, div; 244 u32 mfn, mfd = 1000000; 245 u64 temp64; 246 247 if (rate < min_rate || rate > max_rate) 248 return -EINVAL; 249 250 div = rate / parent_rate; 251 temp64 = (u64) (rate - div * parent_rate); 252 temp64 *= mfd; 253 do_div(temp64, parent_rate); 254 mfn = temp64; 255 256 val = readl_relaxed(pll->base); 257 val &= ~pll->div_mask; 258 val |= div; 259 writel_relaxed(val, pll->base); 260 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); 261 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); 262 263 return clk_pllv3_wait_lock(pll); 264 } 265 266 static const struct clk_ops clk_pllv3_av_ops = { 267 .prepare = clk_pllv3_prepare, 268 .unprepare = clk_pllv3_unprepare, 269 .recalc_rate = clk_pllv3_av_recalc_rate, 270 .round_rate = clk_pllv3_av_round_rate, 271 .set_rate = clk_pllv3_av_set_rate, 272 }; 273 274 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, 275 unsigned long parent_rate) 276 { 277 return 500000000; 278 } 279 280 static const struct clk_ops clk_pllv3_enet_ops = { 281 .prepare = clk_pllv3_prepare, 282 .unprepare = clk_pllv3_unprepare, 283 .recalc_rate = clk_pllv3_enet_recalc_rate, 284 }; 285 286 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 287 const char *parent_name, void __iomem *base, 288 u32 div_mask) 289 { 290 struct clk_pllv3 *pll; 291 const struct clk_ops *ops; 292 struct clk *clk; 293 struct clk_init_data init; 294 295 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 296 if (!pll) 297 return ERR_PTR(-ENOMEM); 298 299 pll->powerdown = BM_PLL_POWER; 300 301 switch (type) { 302 case IMX_PLLV3_SYS: 303 ops = &clk_pllv3_sys_ops; 304 break; 305 case IMX_PLLV3_USB_VF610: 306 pll->div_shift = 1; 307 case IMX_PLLV3_USB: 308 ops = &clk_pllv3_ops; 309 pll->powerup_set = true; 310 break; 311 case IMX_PLLV3_AV: 312 ops = &clk_pllv3_av_ops; 313 break; 314 case IMX_PLLV3_ENET_IMX7: 315 pll->powerdown = IMX7_ENET_PLL_POWER; 316 case IMX_PLLV3_ENET: 317 ops = &clk_pllv3_enet_ops; 318 break; 319 default: 320 ops = &clk_pllv3_ops; 321 } 322 pll->base = base; 323 pll->div_mask = div_mask; 324 325 init.name = name; 326 init.ops = ops; 327 init.flags = 0; 328 init.parent_names = &parent_name; 329 init.num_parents = 1; 330 331 pll->hw.init = &init; 332 333 clk = clk_register(NULL, &pll->hw); 334 if (IS_ERR(clk)) 335 kfree(pll); 336 337 return clk; 338 } 339