1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * Copyright 2012 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/io.h> 16 #include <linux/slab.h> 17 #include <linux/err.h> 18 #include "clk.h" 19 20 /** 21 * struct clk_pfd - IMX PFD clock 22 * @clk_hw: clock source 23 * @reg: PFD register address 24 * @idx: the index of PFD encoded in the register 25 * 26 * PFD clock found on i.MX6 series. Each register for PFD has 4 clk_pfd 27 * data encoded, and member idx is used to specify the one. And each 28 * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc. 29 */ 30 struct clk_pfd { 31 struct clk_hw hw; 32 void __iomem *reg; 33 u8 idx; 34 }; 35 36 #define to_clk_pfd(_hw) container_of(_hw, struct clk_pfd, hw) 37 38 #define SET 0x4 39 #define CLR 0x8 40 #define OTG 0xc 41 42 static int clk_pfd_enable(struct clk_hw *hw) 43 { 44 struct clk_pfd *pfd = to_clk_pfd(hw); 45 46 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); 47 48 return 0; 49 } 50 51 static void clk_pfd_disable(struct clk_hw *hw) 52 { 53 struct clk_pfd *pfd = to_clk_pfd(hw); 54 55 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); 56 } 57 58 static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw, 59 unsigned long parent_rate) 60 { 61 struct clk_pfd *pfd = to_clk_pfd(hw); 62 u64 tmp = parent_rate; 63 u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f; 64 65 tmp *= 18; 66 do_div(tmp, frac); 67 68 return tmp; 69 } 70 71 static long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate, 72 unsigned long *prate) 73 { 74 u64 tmp = *prate; 75 u8 frac; 76 77 tmp = tmp * 18 + rate / 2; 78 do_div(tmp, rate); 79 frac = tmp; 80 if (frac < 12) 81 frac = 12; 82 else if (frac > 35) 83 frac = 35; 84 tmp = *prate; 85 tmp *= 18; 86 do_div(tmp, frac); 87 88 return tmp; 89 } 90 91 static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate, 92 unsigned long parent_rate) 93 { 94 struct clk_pfd *pfd = to_clk_pfd(hw); 95 u64 tmp = parent_rate; 96 u8 frac; 97 98 tmp = tmp * 18 + rate / 2; 99 do_div(tmp, rate); 100 frac = tmp; 101 if (frac < 12) 102 frac = 12; 103 else if (frac > 35) 104 frac = 35; 105 106 writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR); 107 writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET); 108 109 return 0; 110 } 111 112 static int clk_pfd_is_enabled(struct clk_hw *hw) 113 { 114 struct clk_pfd *pfd = to_clk_pfd(hw); 115 116 if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1))) 117 return 0; 118 119 return 1; 120 } 121 122 static const struct clk_ops clk_pfd_ops = { 123 .enable = clk_pfd_enable, 124 .disable = clk_pfd_disable, 125 .recalc_rate = clk_pfd_recalc_rate, 126 .round_rate = clk_pfd_round_rate, 127 .set_rate = clk_pfd_set_rate, 128 .is_enabled = clk_pfd_is_enabled, 129 }; 130 131 struct clk *imx_clk_pfd(const char *name, const char *parent_name, 132 void __iomem *reg, u8 idx) 133 { 134 struct clk_pfd *pfd; 135 struct clk *clk; 136 struct clk_init_data init; 137 138 pfd = kzalloc(sizeof(*pfd), GFP_KERNEL); 139 if (!pfd) 140 return ERR_PTR(-ENOMEM); 141 142 pfd->reg = reg; 143 pfd->idx = idx; 144 145 init.name = name; 146 init.ops = &clk_pfd_ops; 147 init.flags = 0; 148 init.parent_names = &parent_name; 149 init.num_parents = 1; 150 151 pfd->hw.init = &init; 152 153 clk = clk_register(NULL, &pfd->hw); 154 if (IS_ERR(clk)) 155 kfree(pfd); 156 157 return clk; 158 } 159