1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2025 NXP 4 */ 5 6 #include <dt-bindings/clock/imx8ulp-clock.h> 7 8 #include <linux/auxiliary_bus.h> 9 #include <linux/clk-provider.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 #include <linux/slab.h> 16 17 #define SYSCTRL0 0x8 18 19 #define IMX8ULP_HIFI_CLK_GATE(gname, cname, pname, bidx) \ 20 { \ 21 .name = gname "_cg", \ 22 .id = IMX8ULP_CLK_SIM_LPAV_HIFI_##cname, \ 23 .parent = { .fw_name = pname }, \ 24 .bit = bidx, \ 25 } 26 27 struct clk_imx8ulp_sim_lpav_data { 28 spinlock_t lock; /* shared by MUX, clock gate and reset */ 29 unsigned long flags; /* for spinlock usage */ 30 struct clk_hw_onecell_data clk_data; /* keep last */ 31 }; 32 33 struct clk_imx8ulp_sim_lpav_gate { 34 const char *name; 35 int id; 36 const struct clk_parent_data parent; 37 u8 bit; 38 }; 39 40 static struct clk_imx8ulp_sim_lpav_gate gates[] = { 41 IMX8ULP_HIFI_CLK_GATE("hifi_core", CORE, "core", 17), 42 IMX8ULP_HIFI_CLK_GATE("hifi_pbclk", PBCLK, "bus", 18), 43 IMX8ULP_HIFI_CLK_GATE("hifi_plat", PLAT, "plat", 19) 44 }; 45 46 static void clk_imx8ulp_sim_lpav_lock(void *arg) __acquires(&data->lock) 47 { 48 struct clk_imx8ulp_sim_lpav_data *data = dev_get_drvdata(arg); 49 50 spin_lock_irqsave(&data->lock, data->flags); 51 } 52 53 static void clk_imx8ulp_sim_lpav_unlock(void *arg) __releases(&data->lock) 54 { 55 struct clk_imx8ulp_sim_lpav_data *data = dev_get_drvdata(arg); 56 57 spin_unlock_irqrestore(&data->lock, data->flags); 58 } 59 60 static int clk_imx8ulp_sim_lpav_probe(struct platform_device *pdev) 61 { 62 const struct regmap_config regmap_config = { 63 .reg_bits = 32, 64 .val_bits = 32, 65 .reg_stride = 4, 66 .lock = clk_imx8ulp_sim_lpav_lock, 67 .unlock = clk_imx8ulp_sim_lpav_unlock, 68 .lock_arg = &pdev->dev, 69 }; 70 struct clk_imx8ulp_sim_lpav_data *data; 71 struct auxiliary_device *adev; 72 struct regmap *regmap; 73 void __iomem *base; 74 struct clk_hw *hw; 75 int i, ret; 76 77 data = devm_kzalloc(&pdev->dev, 78 struct_size(data, clk_data.hws, ARRAY_SIZE(gates)), 79 GFP_KERNEL); 80 if (!data) 81 return -ENOMEM; 82 83 dev_set_drvdata(&pdev->dev, data); 84 85 /* 86 * this lock is used directly by the clock gate and indirectly 87 * by the reset and mux controller via the regmap API 88 */ 89 spin_lock_init(&data->lock); 90 91 base = devm_platform_ioremap_resource(pdev, 0); 92 if (IS_ERR(base)) 93 return dev_err_probe(&pdev->dev, PTR_ERR(base), 94 "failed to ioremap base\n"); 95 /* 96 * although the clock gate doesn't use the regmap API to modify the 97 * registers, we still need the regmap because of the reset auxiliary 98 * driver and the MUX drivers, which use the parent device's regmap 99 */ 100 regmap = devm_regmap_init_mmio(&pdev->dev, base, ®map_config); 101 if (IS_ERR(regmap)) 102 return dev_err_probe(&pdev->dev, PTR_ERR(regmap), 103 "failed to initialize regmap\n"); 104 105 data->clk_data.num = ARRAY_SIZE(gates); 106 107 for (i = 0; i < ARRAY_SIZE(gates); i++) { 108 hw = devm_clk_hw_register_gate_parent_data(&pdev->dev, 109 gates[i].name, 110 &gates[i].parent, 111 CLK_SET_RATE_PARENT, 112 base + SYSCTRL0, 113 gates[i].bit, 114 0x0, &data->lock); 115 if (IS_ERR(hw)) 116 return dev_err_probe(&pdev->dev, PTR_ERR(hw), 117 "failed to register %s gate\n", 118 gates[i].name); 119 120 data->clk_data.hws[i] = hw; 121 } 122 123 adev = devm_auxiliary_device_create(&pdev->dev, "reset", NULL); 124 if (!adev) 125 return dev_err_probe(&pdev->dev, -ENODEV, 126 "failed to register aux reset\n"); 127 128 ret = devm_of_clk_add_hw_provider(&pdev->dev, 129 of_clk_hw_onecell_get, 130 &data->clk_data); 131 if (ret) 132 return dev_err_probe(&pdev->dev, ret, 133 "failed to register clk hw provider\n"); 134 135 /* used to probe MUX child device */ 136 return devm_of_platform_populate(&pdev->dev); 137 } 138 139 static const struct of_device_id clk_imx8ulp_sim_lpav_of_match[] = { 140 { .compatible = "fsl,imx8ulp-sim-lpav" }, 141 { } 142 }; 143 MODULE_DEVICE_TABLE(of, clk_imx8ulp_sim_lpav_of_match); 144 145 static struct platform_driver clk_imx8ulp_sim_lpav_driver = { 146 .probe = clk_imx8ulp_sim_lpav_probe, 147 .driver = { 148 .name = "clk-imx8ulp-sim-lpav", 149 .of_match_table = clk_imx8ulp_sim_lpav_of_match, 150 }, 151 }; 152 module_platform_driver(clk_imx8ulp_sim_lpav_driver); 153 154 MODULE_LICENSE("GPL"); 155 MODULE_DESCRIPTION("i.MX8ULP LPAV System Integration Module (SIM) clock driver"); 156 MODULE_AUTHOR("Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>"); 157