1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for i.MX8M Plus Audio BLK_CTRL 4 * 5 * Copyright (C) 2022 Marek Vasut <marex@denx.de> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/io.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 17 #include <dt-bindings/clock/imx8mp-clock.h> 18 19 #include "clk.h" 20 21 #define CLKEN0 0x000 22 #define CLKEN1 0x004 23 #define EARC 0x200 24 #define SAI1_MCLK_SEL 0x300 25 #define SAI2_MCLK_SEL 0x304 26 #define SAI3_MCLK_SEL 0x308 27 #define SAI5_MCLK_SEL 0x30C 28 #define SAI6_MCLK_SEL 0x310 29 #define SAI7_MCLK_SEL 0x314 30 #define PDM_SEL 0x318 31 #define SAI_PLL_GNRL_CTL 0x400 32 #define SAI_PLL_FDIVL_CTL0 0x404 33 #define SAI_PLL_FDIVL_CTL1 0x408 34 #define SAI_PLL_SSCG_CTL 0x40C 35 #define SAI_PLL_MNIT_CTL 0x410 36 #define IPG_LP_CTRL 0x504 37 38 #define SAIn_MCLK1_PARENT(n) \ 39 static const struct clk_parent_data \ 40 clk_imx8mp_audiomix_sai##n##_mclk1_parents[] = { \ 41 { \ 42 .fw_name = "sai"__stringify(n), \ 43 .name = "sai"__stringify(n) \ 44 }, { \ 45 .fw_name = "sai"__stringify(n)"_mclk", \ 46 .name = "sai"__stringify(n)"_mclk" \ 47 }, \ 48 } 49 50 SAIn_MCLK1_PARENT(1); 51 SAIn_MCLK1_PARENT(2); 52 SAIn_MCLK1_PARENT(3); 53 SAIn_MCLK1_PARENT(5); 54 SAIn_MCLK1_PARENT(6); 55 SAIn_MCLK1_PARENT(7); 56 57 static const struct clk_parent_data clk_imx8mp_audiomix_sai_mclk2_parents[] = { 58 { .fw_name = "sai1", .name = "sai1" }, 59 { .fw_name = "sai2", .name = "sai2" }, 60 { .fw_name = "sai3", .name = "sai3" }, 61 { .name = "dummy" }, 62 { .fw_name = "sai5", .name = "sai5" }, 63 { .fw_name = "sai6", .name = "sai6" }, 64 { .fw_name = "sai7", .name = "sai7" }, 65 { .fw_name = "sai1_mclk", .name = "sai1_mclk" }, 66 { .fw_name = "sai2_mclk", .name = "sai2_mclk" }, 67 { .fw_name = "sai3_mclk", .name = "sai3_mclk" }, 68 { .name = "dummy" }, 69 { .fw_name = "sai5_mclk", .name = "sai5_mclk" }, 70 { .fw_name = "sai6_mclk", .name = "sai6_mclk" }, 71 { .fw_name = "sai7_mclk", .name = "sai7_mclk" }, 72 { .fw_name = "spdif_extclk", .name = "spdif_extclk" }, 73 { .name = "dummy" }, 74 }; 75 76 static const struct clk_parent_data clk_imx8mp_audiomix_pdm_parents[] = { 77 { .fw_name = "pdm", .name = "pdm" }, 78 { .name = "sai_pll_out_div2" }, 79 { .fw_name = "sai1_mclk", .name = "sai1_mclk" }, 80 { .name = "dummy" }, 81 }; 82 83 84 static const struct clk_parent_data clk_imx8mp_audiomix_pll_parents[] = { 85 { .fw_name = "osc_24m", .name = "osc_24m" }, 86 { .name = "dummy" }, 87 { .name = "dummy" }, 88 { .name = "dummy" }, 89 }; 90 91 static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = { 92 { .fw_name = "sai_pll", .name = "sai_pll" }, 93 { .fw_name = "sai_pll_ref_sel", .name = "sai_pll_ref_sel" }, 94 }; 95 96 #define CLK_GATE(gname, cname) \ 97 { \ 98 gname"_cg", \ 99 IMX8MP_CLK_AUDIOMIX_##cname, \ 100 { .fw_name = "ahb", .name = "ahb" }, NULL, 1, \ 101 CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32), \ 102 1, IMX8MP_CLK_AUDIOMIX_##cname % 32 \ 103 } 104 105 #define CLK_SAIn(n) \ 106 { \ 107 "sai"__stringify(n)"_mclk1_sel", \ 108 IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1_SEL, {}, \ 109 clk_imx8mp_audiomix_sai##n##_mclk1_parents, \ 110 ARRAY_SIZE(clk_imx8mp_audiomix_sai##n##_mclk1_parents), \ 111 SAI##n##_MCLK_SEL, 1, 0 \ 112 }, { \ 113 "sai"__stringify(n)"_mclk2_sel", \ 114 IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2_SEL, {}, \ 115 clk_imx8mp_audiomix_sai_mclk2_parents, \ 116 ARRAY_SIZE(clk_imx8mp_audiomix_sai_mclk2_parents), \ 117 SAI##n##_MCLK_SEL, 4, 1 \ 118 }, { \ 119 "sai"__stringify(n)"_ipg_cg", \ 120 IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG, \ 121 { .fw_name = "ahb", .name = "ahb" }, NULL, 1, \ 122 CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG \ 123 }, { \ 124 "sai"__stringify(n)"_mclk1_cg", \ 125 IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1, \ 126 { \ 127 .fw_name = "sai"__stringify(n)"_mclk1_sel", \ 128 .name = "sai"__stringify(n)"_mclk1_sel" \ 129 }, NULL, 1, \ 130 CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1 \ 131 }, { \ 132 "sai"__stringify(n)"_mclk2_cg", \ 133 IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2, \ 134 { \ 135 .fw_name = "sai"__stringify(n)"_mclk2_sel", \ 136 .name = "sai"__stringify(n)"_mclk2_sel" \ 137 }, NULL, 1, \ 138 CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2 \ 139 }, { \ 140 "sai"__stringify(n)"_mclk3_cg", \ 141 IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3, \ 142 { \ 143 .fw_name = "sai_pll_out_div2", \ 144 .name = "sai_pll_out_div2" \ 145 }, NULL, 1, \ 146 CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3 \ 147 } 148 149 #define CLK_PDM \ 150 { \ 151 "pdm_sel", IMX8MP_CLK_AUDIOMIX_PDM_SEL, {}, \ 152 clk_imx8mp_audiomix_pdm_parents, \ 153 ARRAY_SIZE(clk_imx8mp_audiomix_pdm_parents), \ 154 PDM_SEL, 2, 0 \ 155 } 156 157 struct clk_imx8mp_audiomix_sel { 158 const char *name; 159 int clkid; 160 const struct clk_parent_data parent; /* For gate */ 161 const struct clk_parent_data *parents; /* For mux */ 162 int num_parents; 163 u16 reg; 164 u8 width; 165 u8 shift; 166 }; 167 168 static struct clk_imx8mp_audiomix_sel sels[] = { 169 CLK_GATE("asrc", ASRC_IPG), 170 CLK_GATE("pdm", PDM_IPG), 171 CLK_GATE("earc", EARC_IPG), 172 CLK_GATE("ocrama", OCRAMA_IPG), 173 CLK_GATE("aud2htx", AUD2HTX_IPG), 174 CLK_GATE("earc_phy", EARC_PHY), 175 CLK_GATE("sdma2", SDMA2_ROOT), 176 CLK_GATE("sdma3", SDMA3_ROOT), 177 CLK_GATE("spba2", SPBA2_ROOT), 178 CLK_GATE("dsp", DSP_ROOT), 179 CLK_GATE("dspdbg", DSPDBG_ROOT), 180 CLK_GATE("edma", EDMA_ROOT), 181 CLK_GATE("audpll", AUDPLL_ROOT), 182 CLK_GATE("mu2", MU2_ROOT), 183 CLK_GATE("mu3", MU3_ROOT), 184 CLK_PDM, 185 CLK_SAIn(1), 186 CLK_SAIn(2), 187 CLK_SAIn(3), 188 CLK_SAIn(5), 189 CLK_SAIn(6), 190 CLK_SAIn(7) 191 }; 192 193 static const u16 audiomix_regs[] = { 194 CLKEN0, 195 CLKEN1, 196 EARC, 197 SAI1_MCLK_SEL, 198 SAI2_MCLK_SEL, 199 SAI3_MCLK_SEL, 200 SAI5_MCLK_SEL, 201 SAI6_MCLK_SEL, 202 SAI7_MCLK_SEL, 203 PDM_SEL, 204 SAI_PLL_GNRL_CTL, 205 SAI_PLL_FDIVL_CTL0, 206 SAI_PLL_FDIVL_CTL1, 207 SAI_PLL_SSCG_CTL, 208 SAI_PLL_MNIT_CTL, 209 IPG_LP_CTRL, 210 }; 211 212 struct clk_imx8mp_audiomix_priv { 213 void __iomem *base; 214 u32 regs_save[ARRAY_SIZE(audiomix_regs)]; 215 216 /* Must be last */ 217 struct clk_hw_onecell_data clk_data; 218 }; 219 220 static void clk_imx8mp_audiomix_save_restore(struct device *dev, bool save) 221 { 222 struct clk_imx8mp_audiomix_priv *priv = dev_get_drvdata(dev); 223 void __iomem *base = priv->base; 224 int i; 225 226 if (save) { 227 for (i = 0; i < ARRAY_SIZE(audiomix_regs); i++) 228 priv->regs_save[i] = readl(base + audiomix_regs[i]); 229 } else { 230 for (i = 0; i < ARRAY_SIZE(audiomix_regs); i++) 231 writel(priv->regs_save[i], base + audiomix_regs[i]); 232 } 233 } 234 235 static int clk_imx8mp_audiomix_probe(struct platform_device *pdev) 236 { 237 struct clk_imx8mp_audiomix_priv *priv; 238 struct clk_hw_onecell_data *clk_hw_data; 239 struct device *dev = &pdev->dev; 240 void __iomem *base; 241 struct clk_hw *hw; 242 int i, ret; 243 244 priv = devm_kzalloc(dev, 245 struct_size(priv, clk_data.hws, IMX8MP_CLK_AUDIOMIX_END), 246 GFP_KERNEL); 247 if (!priv) 248 return -ENOMEM; 249 250 clk_hw_data = &priv->clk_data; 251 clk_hw_data->num = IMX8MP_CLK_AUDIOMIX_END; 252 253 base = devm_platform_ioremap_resource(pdev, 0); 254 if (IS_ERR(base)) 255 return PTR_ERR(base); 256 257 priv->base = base; 258 dev_set_drvdata(dev, priv); 259 260 /* 261 * pm_runtime_enable needs to be called before clk register. 262 * That is to make core->rpm_enabled to be true for clock 263 * usage. 264 */ 265 pm_runtime_get_noresume(dev); 266 pm_runtime_set_active(dev); 267 pm_runtime_enable(dev); 268 269 for (i = 0; i < ARRAY_SIZE(sels); i++) { 270 if (sels[i].num_parents == 1) { 271 hw = devm_clk_hw_register_gate_parent_data(dev, 272 sels[i].name, &sels[i].parent, 0, 273 base + sels[i].reg, sels[i].shift, 0, NULL); 274 } else { 275 hw = devm_clk_hw_register_mux_parent_data_table(dev, 276 sels[i].name, sels[i].parents, 277 sels[i].num_parents, 0, 278 base + sels[i].reg, 279 sels[i].shift, sels[i].width, 280 0, NULL, NULL); 281 } 282 283 if (IS_ERR(hw)) { 284 ret = PTR_ERR(hw); 285 goto err_clk_register; 286 } 287 288 clk_hw_data->hws[sels[i].clkid] = hw; 289 } 290 291 /* SAI PLL */ 292 hw = devm_clk_hw_register_mux_parent_data_table(dev, 293 "sai_pll_ref_sel", clk_imx8mp_audiomix_pll_parents, 294 ARRAY_SIZE(clk_imx8mp_audiomix_pll_parents), 295 CLK_SET_RATE_NO_REPARENT, base + SAI_PLL_GNRL_CTL, 296 0, 2, 0, NULL, NULL); 297 clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw; 298 299 hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel", 300 base + 0x400, &imx_1443x_pll); 301 if (IS_ERR(hw)) { 302 ret = PTR_ERR(hw); 303 goto err_clk_register; 304 } 305 clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw; 306 307 hw = devm_clk_hw_register_mux_parent_data_table(dev, 308 "sai_pll_bypass", clk_imx8mp_audiomix_pll_bypass_sels, 309 ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels), 310 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, 311 base + SAI_PLL_GNRL_CTL, 16, 1, 0, NULL, NULL); 312 if (IS_ERR(hw)) { 313 ret = PTR_ERR(hw); 314 goto err_clk_register; 315 } 316 317 clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw; 318 319 hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass", 320 0, base + SAI_PLL_GNRL_CTL, 13, 321 0, NULL); 322 if (IS_ERR(hw)) { 323 ret = PTR_ERR(hw); 324 goto err_clk_register; 325 } 326 clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw; 327 328 hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2", 329 "sai_pll_out", 0, 1, 2); 330 if (IS_ERR(hw)) { 331 ret = PTR_ERR(hw); 332 goto err_clk_register; 333 } 334 335 ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, 336 clk_hw_data); 337 if (ret) 338 goto err_clk_register; 339 340 pm_runtime_put_sync(dev); 341 return 0; 342 343 err_clk_register: 344 pm_runtime_put_sync(dev); 345 pm_runtime_disable(dev); 346 return ret; 347 } 348 349 static void clk_imx8mp_audiomix_remove(struct platform_device *pdev) 350 { 351 pm_runtime_disable(&pdev->dev); 352 } 353 354 static int clk_imx8mp_audiomix_runtime_suspend(struct device *dev) 355 { 356 clk_imx8mp_audiomix_save_restore(dev, true); 357 358 return 0; 359 } 360 361 static int clk_imx8mp_audiomix_runtime_resume(struct device *dev) 362 { 363 clk_imx8mp_audiomix_save_restore(dev, false); 364 365 return 0; 366 } 367 368 static const struct dev_pm_ops clk_imx8mp_audiomix_pm_ops = { 369 RUNTIME_PM_OPS(clk_imx8mp_audiomix_runtime_suspend, 370 clk_imx8mp_audiomix_runtime_resume, NULL) 371 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 372 pm_runtime_force_resume) 373 }; 374 375 static const struct of_device_id clk_imx8mp_audiomix_of_match[] = { 376 { .compatible = "fsl,imx8mp-audio-blk-ctrl" }, 377 { /* sentinel */ } 378 }; 379 MODULE_DEVICE_TABLE(of, clk_imx8mp_audiomix_of_match); 380 381 static struct platform_driver clk_imx8mp_audiomix_driver = { 382 .probe = clk_imx8mp_audiomix_probe, 383 .remove_new = clk_imx8mp_audiomix_remove, 384 .driver = { 385 .name = "imx8mp-audio-blk-ctrl", 386 .of_match_table = clk_imx8mp_audiomix_of_match, 387 .pm = pm_ptr(&clk_imx8mp_audiomix_pm_ops), 388 }, 389 }; 390 391 module_platform_driver(clk_imx8mp_audiomix_driver); 392 393 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 394 MODULE_DESCRIPTION("Freescale i.MX8MP Audio Block Controller driver"); 395 MODULE_LICENSE("GPL"); 396