1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for i.MX8M Plus Audio BLK_CTRL 4 * 5 * Copyright (C) 2022 Marek Vasut <marex@denx.de> 6 */ 7 8 #include <linux/auxiliary_bus.h> 9 #include <linux/clk-provider.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/slab.h> 18 19 #include <dt-bindings/clock/imx8mp-clock.h> 20 21 #include "clk.h" 22 23 #define CLKEN0 0x000 24 #define CLKEN1 0x004 25 #define EARC 0x200 26 #define SAI1_MCLK_SEL 0x300 27 #define SAI2_MCLK_SEL 0x304 28 #define SAI3_MCLK_SEL 0x308 29 #define SAI5_MCLK_SEL 0x30C 30 #define SAI6_MCLK_SEL 0x310 31 #define SAI7_MCLK_SEL 0x314 32 #define PDM_SEL 0x318 33 #define SAI_PLL_GNRL_CTL 0x400 34 #define SAI_PLL_FDIVL_CTL0 0x404 35 #define SAI_PLL_FDIVL_CTL1 0x408 36 #define SAI_PLL_SSCG_CTL 0x40C 37 #define SAI_PLL_MNIT_CTL 0x410 38 #define IPG_LP_CTRL 0x504 39 40 #define SAIn_MCLK1_PARENT(n) \ 41 static const struct clk_parent_data \ 42 clk_imx8mp_audiomix_sai##n##_mclk1_parents[] = { \ 43 { \ 44 .fw_name = "sai"__stringify(n), \ 45 .name = "sai"__stringify(n) \ 46 }, { \ 47 .fw_name = "sai"__stringify(n)"_mclk", \ 48 .name = "sai"__stringify(n)"_mclk" \ 49 }, \ 50 } 51 52 SAIn_MCLK1_PARENT(1); 53 SAIn_MCLK1_PARENT(2); 54 SAIn_MCLK1_PARENT(3); 55 SAIn_MCLK1_PARENT(5); 56 SAIn_MCLK1_PARENT(6); 57 SAIn_MCLK1_PARENT(7); 58 59 static const struct clk_parent_data clk_imx8mp_audiomix_sai_mclk2_parents[] = { 60 { .fw_name = "sai1", .name = "sai1" }, 61 { .fw_name = "sai2", .name = "sai2" }, 62 { .fw_name = "sai3", .name = "sai3" }, 63 { .name = "dummy" }, 64 { .fw_name = "sai5", .name = "sai5" }, 65 { .fw_name = "sai6", .name = "sai6" }, 66 { .fw_name = "sai7", .name = "sai7" }, 67 { .fw_name = "sai1_mclk", .name = "sai1_mclk" }, 68 { .fw_name = "sai2_mclk", .name = "sai2_mclk" }, 69 { .fw_name = "sai3_mclk", .name = "sai3_mclk" }, 70 { .name = "dummy" }, 71 { .fw_name = "sai5_mclk", .name = "sai5_mclk" }, 72 { .fw_name = "sai6_mclk", .name = "sai6_mclk" }, 73 { .fw_name = "sai7_mclk", .name = "sai7_mclk" }, 74 { .fw_name = "spdif_extclk", .name = "spdif_extclk" }, 75 { .name = "dummy" }, 76 }; 77 78 static const struct clk_parent_data clk_imx8mp_audiomix_pdm_parents[] = { 79 { .fw_name = "pdm", .name = "pdm" }, 80 { .name = "sai_pll_out_div2" }, 81 { .fw_name = "sai1_mclk", .name = "sai1_mclk" }, 82 { .name = "dummy" }, 83 }; 84 85 86 static const struct clk_parent_data clk_imx8mp_audiomix_pll_parents[] = { 87 { .fw_name = "osc_24m", .name = "osc_24m" }, 88 { .name = "dummy" }, 89 { .name = "dummy" }, 90 { .name = "dummy" }, 91 }; 92 93 static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = { 94 { .fw_name = "sai_pll", .name = "sai_pll" }, 95 { .fw_name = "sai_pll_ref_sel", .name = "sai_pll_ref_sel" }, 96 }; 97 98 #define CLK_GATE(gname, cname) \ 99 { \ 100 gname"_cg", \ 101 IMX8MP_CLK_AUDIOMIX_##cname, \ 102 { .fw_name = "ahb", .name = "ahb" }, NULL, 1, \ 103 CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32), \ 104 1, IMX8MP_CLK_AUDIOMIX_##cname % 32 \ 105 } 106 107 #define CLK_SAIn(n) \ 108 { \ 109 "sai"__stringify(n)"_mclk1_sel", \ 110 IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1_SEL, {}, \ 111 clk_imx8mp_audiomix_sai##n##_mclk1_parents, \ 112 ARRAY_SIZE(clk_imx8mp_audiomix_sai##n##_mclk1_parents), \ 113 SAI##n##_MCLK_SEL, 1, 0 \ 114 }, { \ 115 "sai"__stringify(n)"_mclk2_sel", \ 116 IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2_SEL, {}, \ 117 clk_imx8mp_audiomix_sai_mclk2_parents, \ 118 ARRAY_SIZE(clk_imx8mp_audiomix_sai_mclk2_parents), \ 119 SAI##n##_MCLK_SEL, 4, 1 \ 120 }, { \ 121 "sai"__stringify(n)"_ipg_cg", \ 122 IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG, \ 123 { .fw_name = "ahb", .name = "ahb" }, NULL, 1, \ 124 CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG \ 125 }, { \ 126 "sai"__stringify(n)"_mclk1_cg", \ 127 IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1, \ 128 { \ 129 .fw_name = "sai"__stringify(n)"_mclk1_sel", \ 130 .name = "sai"__stringify(n)"_mclk1_sel" \ 131 }, NULL, 1, \ 132 CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1 \ 133 }, { \ 134 "sai"__stringify(n)"_mclk2_cg", \ 135 IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2, \ 136 { \ 137 .fw_name = "sai"__stringify(n)"_mclk2_sel", \ 138 .name = "sai"__stringify(n)"_mclk2_sel" \ 139 }, NULL, 1, \ 140 CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2 \ 141 }, { \ 142 "sai"__stringify(n)"_mclk3_cg", \ 143 IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3, \ 144 { \ 145 .fw_name = "sai_pll_out_div2", \ 146 .name = "sai_pll_out_div2" \ 147 }, NULL, 1, \ 148 CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3 \ 149 } 150 151 #define CLK_PDM \ 152 { \ 153 "pdm_sel", IMX8MP_CLK_AUDIOMIX_PDM_SEL, {}, \ 154 clk_imx8mp_audiomix_pdm_parents, \ 155 ARRAY_SIZE(clk_imx8mp_audiomix_pdm_parents), \ 156 PDM_SEL, 2, 0 \ 157 } 158 159 #define CLK_GATE_PARENT(gname, cname, pname) \ 160 { \ 161 gname"_cg", \ 162 IMX8MP_CLK_AUDIOMIX_##cname, \ 163 { .fw_name = pname, .name = pname }, NULL, 1, \ 164 CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32), \ 165 1, IMX8MP_CLK_AUDIOMIX_##cname % 32 \ 166 } 167 168 struct clk_imx8mp_audiomix_sel { 169 const char *name; 170 int clkid; 171 const struct clk_parent_data parent; /* For gate */ 172 const struct clk_parent_data *parents; /* For mux */ 173 int num_parents; 174 u16 reg; 175 u8 width; 176 u8 shift; 177 }; 178 179 static struct clk_imx8mp_audiomix_sel sels[] = { 180 CLK_GATE("asrc", ASRC_IPG), 181 CLK_GATE("pdm", PDM_IPG), 182 CLK_GATE("earc", EARC_IPG), 183 CLK_GATE("ocrama", OCRAMA_IPG), 184 CLK_GATE("aud2htx", AUD2HTX_IPG), 185 CLK_GATE_PARENT("earc_phy", EARC_PHY, "sai_pll_out_div2"), 186 CLK_GATE("sdma2", SDMA2_ROOT), 187 CLK_GATE("sdma3", SDMA3_ROOT), 188 CLK_GATE("spba2", SPBA2_ROOT), 189 CLK_GATE("dsp", DSP_ROOT), 190 CLK_GATE("dspdbg", DSPDBG_ROOT), 191 CLK_GATE("edma", EDMA_ROOT), 192 CLK_GATE_PARENT("audpll", AUDPLL_ROOT, "osc_24m"), 193 CLK_GATE("mu2", MU2_ROOT), 194 CLK_GATE("mu3", MU3_ROOT), 195 CLK_PDM, 196 CLK_SAIn(1), 197 CLK_SAIn(2), 198 CLK_SAIn(3), 199 CLK_SAIn(5), 200 CLK_SAIn(6), 201 CLK_SAIn(7) 202 }; 203 204 static const u16 audiomix_regs[] = { 205 CLKEN0, 206 CLKEN1, 207 EARC, 208 SAI1_MCLK_SEL, 209 SAI2_MCLK_SEL, 210 SAI3_MCLK_SEL, 211 SAI5_MCLK_SEL, 212 SAI6_MCLK_SEL, 213 SAI7_MCLK_SEL, 214 PDM_SEL, 215 SAI_PLL_GNRL_CTL, 216 SAI_PLL_FDIVL_CTL0, 217 SAI_PLL_FDIVL_CTL1, 218 SAI_PLL_SSCG_CTL, 219 SAI_PLL_MNIT_CTL, 220 IPG_LP_CTRL, 221 }; 222 223 struct clk_imx8mp_audiomix_priv { 224 void __iomem *base; 225 u32 regs_save[ARRAY_SIZE(audiomix_regs)]; 226 227 /* Must be last */ 228 struct clk_hw_onecell_data clk_data; 229 }; 230 231 #if IS_ENABLED(CONFIG_RESET_CONTROLLER) 232 233 static void clk_imx8mp_audiomix_reset_unregister_adev(void *_adev) 234 { 235 struct auxiliary_device *adev = _adev; 236 237 auxiliary_device_delete(adev); 238 auxiliary_device_uninit(adev); 239 } 240 241 static void clk_imx8mp_audiomix_reset_adev_release(struct device *dev) 242 { 243 struct auxiliary_device *adev = to_auxiliary_dev(dev); 244 245 kfree(adev); 246 } 247 248 static int clk_imx8mp_audiomix_reset_controller_register(struct device *dev, 249 struct clk_imx8mp_audiomix_priv *priv) 250 { 251 struct auxiliary_device *adev __free(kfree) = NULL; 252 int ret; 253 254 if (!of_property_present(dev->of_node, "#reset-cells")) 255 return 0; 256 257 adev = kzalloc(sizeof(*adev), GFP_KERNEL); 258 if (!adev) 259 return -ENOMEM; 260 261 adev->name = "reset"; 262 adev->dev.parent = dev; 263 adev->dev.release = clk_imx8mp_audiomix_reset_adev_release; 264 265 ret = auxiliary_device_init(adev); 266 if (ret) 267 return ret; 268 269 ret = auxiliary_device_add(adev); 270 if (ret) { 271 auxiliary_device_uninit(adev); 272 return ret; 273 } 274 275 return devm_add_action_or_reset(dev, clk_imx8mp_audiomix_reset_unregister_adev, 276 no_free_ptr(adev)); 277 } 278 279 #else /* !CONFIG_RESET_CONTROLLER */ 280 281 static int clk_imx8mp_audiomix_reset_controller_register(struct device *dev, 282 struct clk_imx8mp_audiomix_priv *priv) 283 { 284 return 0; 285 } 286 287 #endif /* !CONFIG_RESET_CONTROLLER */ 288 289 static void clk_imx8mp_audiomix_save_restore(struct device *dev, bool save) 290 { 291 struct clk_imx8mp_audiomix_priv *priv = dev_get_drvdata(dev); 292 void __iomem *base = priv->base; 293 int i; 294 295 if (save) { 296 for (i = 0; i < ARRAY_SIZE(audiomix_regs); i++) 297 priv->regs_save[i] = readl(base + audiomix_regs[i]); 298 } else { 299 for (i = 0; i < ARRAY_SIZE(audiomix_regs); i++) 300 writel(priv->regs_save[i], base + audiomix_regs[i]); 301 } 302 } 303 304 static int clk_imx8mp_audiomix_probe(struct platform_device *pdev) 305 { 306 struct clk_imx8mp_audiomix_priv *priv; 307 struct clk_hw_onecell_data *clk_hw_data; 308 struct device *dev = &pdev->dev; 309 void __iomem *base; 310 struct clk_hw *hw; 311 int i, ret; 312 313 priv = devm_kzalloc(dev, 314 struct_size(priv, clk_data.hws, IMX8MP_CLK_AUDIOMIX_END), 315 GFP_KERNEL); 316 if (!priv) 317 return -ENOMEM; 318 319 clk_hw_data = &priv->clk_data; 320 clk_hw_data->num = IMX8MP_CLK_AUDIOMIX_END; 321 322 base = devm_platform_ioremap_resource(pdev, 0); 323 if (IS_ERR(base)) 324 return PTR_ERR(base); 325 326 priv->base = base; 327 dev_set_drvdata(dev, priv); 328 329 /* 330 * pm_runtime_enable needs to be called before clk register. 331 * That is to make core->rpm_enabled to be true for clock 332 * usage. 333 */ 334 pm_runtime_get_noresume(dev); 335 pm_runtime_set_active(dev); 336 pm_runtime_enable(dev); 337 338 for (i = 0; i < ARRAY_SIZE(sels); i++) { 339 if (sels[i].num_parents == 1) { 340 hw = devm_clk_hw_register_gate_parent_data(dev, 341 sels[i].name, &sels[i].parent, CLK_SET_RATE_PARENT, 342 base + sels[i].reg, sels[i].shift, 0, NULL); 343 } else { 344 hw = devm_clk_hw_register_mux_parent_data_table(dev, 345 sels[i].name, sels[i].parents, 346 sels[i].num_parents, CLK_SET_RATE_PARENT, 347 base + sels[i].reg, 348 sels[i].shift, sels[i].width, 349 0, NULL, NULL); 350 } 351 352 if (IS_ERR(hw)) { 353 ret = PTR_ERR(hw); 354 goto err_clk_register; 355 } 356 357 clk_hw_data->hws[sels[i].clkid] = hw; 358 } 359 360 /* SAI PLL */ 361 hw = devm_clk_hw_register_mux_parent_data_table(dev, 362 "sai_pll_ref_sel", clk_imx8mp_audiomix_pll_parents, 363 ARRAY_SIZE(clk_imx8mp_audiomix_pll_parents), 364 CLK_SET_RATE_NO_REPARENT, base + SAI_PLL_GNRL_CTL, 365 0, 2, 0, NULL, NULL); 366 clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw; 367 368 hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel", 369 base + 0x400, &imx_1443x_pll); 370 if (IS_ERR(hw)) { 371 ret = PTR_ERR(hw); 372 goto err_clk_register; 373 } 374 clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw; 375 376 hw = devm_clk_hw_register_mux_parent_data_table(dev, 377 "sai_pll_bypass", clk_imx8mp_audiomix_pll_bypass_sels, 378 ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels), 379 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, 380 base + SAI_PLL_GNRL_CTL, 16, 1, 0, NULL, NULL); 381 if (IS_ERR(hw)) { 382 ret = PTR_ERR(hw); 383 goto err_clk_register; 384 } 385 386 clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw; 387 388 hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass", 389 CLK_SET_RATE_PARENT, 390 base + SAI_PLL_GNRL_CTL, 13, 391 0, NULL); 392 if (IS_ERR(hw)) { 393 ret = PTR_ERR(hw); 394 goto err_clk_register; 395 } 396 clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw; 397 398 hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2", 399 "sai_pll_out", 400 CLK_SET_RATE_PARENT, 1, 2); 401 if (IS_ERR(hw)) { 402 ret = PTR_ERR(hw); 403 goto err_clk_register; 404 } 405 406 ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, 407 clk_hw_data); 408 if (ret) 409 goto err_clk_register; 410 411 ret = clk_imx8mp_audiomix_reset_controller_register(dev, priv); 412 if (ret) 413 goto err_clk_register; 414 415 pm_runtime_put_sync(dev); 416 return 0; 417 418 err_clk_register: 419 pm_runtime_put_sync(dev); 420 pm_runtime_disable(dev); 421 return ret; 422 } 423 424 static void clk_imx8mp_audiomix_remove(struct platform_device *pdev) 425 { 426 pm_runtime_disable(&pdev->dev); 427 } 428 429 static int clk_imx8mp_audiomix_runtime_suspend(struct device *dev) 430 { 431 clk_imx8mp_audiomix_save_restore(dev, true); 432 433 return 0; 434 } 435 436 static int clk_imx8mp_audiomix_runtime_resume(struct device *dev) 437 { 438 clk_imx8mp_audiomix_save_restore(dev, false); 439 440 return 0; 441 } 442 443 static const struct dev_pm_ops clk_imx8mp_audiomix_pm_ops = { 444 RUNTIME_PM_OPS(clk_imx8mp_audiomix_runtime_suspend, 445 clk_imx8mp_audiomix_runtime_resume, NULL) 446 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 447 pm_runtime_force_resume) 448 }; 449 450 static const struct of_device_id clk_imx8mp_audiomix_of_match[] = { 451 { .compatible = "fsl,imx8mp-audio-blk-ctrl" }, 452 { /* sentinel */ } 453 }; 454 MODULE_DEVICE_TABLE(of, clk_imx8mp_audiomix_of_match); 455 456 static struct platform_driver clk_imx8mp_audiomix_driver = { 457 .probe = clk_imx8mp_audiomix_probe, 458 .remove = clk_imx8mp_audiomix_remove, 459 .driver = { 460 .name = "imx8mp-audio-blk-ctrl", 461 .of_match_table = clk_imx8mp_audiomix_of_match, 462 .pm = pm_ptr(&clk_imx8mp_audiomix_pm_ops), 463 }, 464 }; 465 466 module_platform_driver(clk_imx8mp_audiomix_driver); 467 468 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 469 MODULE_DESCRIPTION("Freescale i.MX8MP Audio Block Controller driver"); 470 MODULE_LICENSE("GPL"); 471