1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright 2023 NXP 4 // 5 6 #include <dt-bindings/clock/imx8-clock.h> 7 #include <linux/clk-provider.h> 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_domain.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/slab.h> 18 19 #include "clk.h" 20 21 /** 22 * struct clk_imx_acm_pm_domains - structure for multi power domain 23 * @pd_dev: power domain device 24 * @pd_dev_link: power domain device link 25 * @num_domains: power domain nummber 26 */ 27 struct clk_imx_acm_pm_domains { 28 struct device **pd_dev; 29 struct device_link **pd_dev_link; 30 int num_domains; 31 }; 32 33 /** 34 * struct clk_imx8_acm_sel - for clock mux 35 * @name: clock name 36 * @clkid: clock id 37 * @parents: clock parents 38 * @num_parents: clock parents number 39 * @reg: register offset 40 * @shift: bit shift in register 41 * @width: bits width 42 */ 43 struct clk_imx8_acm_sel { 44 const char *name; 45 int clkid; 46 const struct clk_parent_data *parents; /* For mux */ 47 int num_parents; 48 u32 reg; 49 u8 shift; 50 u8 width; 51 }; 52 53 /** 54 * struct imx8_acm_soc_data - soc specific data 55 * @sels: pointer to struct clk_imx8_acm_sel 56 * @num_sels: numbers of items 57 * @mclk_sels: pointer to imx8qm/qxp/dxl_mclk_sels 58 */ 59 struct imx8_acm_soc_data { 60 struct clk_imx8_acm_sel *sels; 61 unsigned int num_sels; 62 struct clk_parent_data *mclk_sels; 63 }; 64 65 /** 66 * struct imx8_acm_priv - private structure 67 * @dev_pm: multi power domain 68 * @soc_data: pointer to soc data 69 * @reg: base address of registers 70 * @regs: save registers for suspend 71 */ 72 struct imx8_acm_priv { 73 struct clk_imx_acm_pm_domains dev_pm; 74 const struct imx8_acm_soc_data *soc_data; 75 void __iomem *reg; 76 u32 regs[IMX_ADMA_ACM_CLK_END]; 77 }; 78 79 static const struct clk_parent_data imx8qm_aud_clk_sels[] = { 80 { .fw_name = "aud_rec_clk0_lpcg_clk" }, 81 { .fw_name = "aud_rec_clk1_lpcg_clk" }, 82 { .fw_name = "dummy" }, 83 { .fw_name = "hdmi_rx_mclk" }, 84 { .fw_name = "ext_aud_mclk0" }, 85 { .fw_name = "ext_aud_mclk1" }, 86 { .fw_name = "esai0_rx_clk" }, 87 { .fw_name = "esai0_rx_hf_clk" }, 88 { .fw_name = "esai0_tx_clk" }, 89 { .fw_name = "esai0_tx_hf_clk" }, 90 { .fw_name = "esai1_rx_clk" }, 91 { .fw_name = "esai1_rx_hf_clk" }, 92 { .fw_name = "esai1_tx_clk" }, 93 { .fw_name = "esai1_tx_hf_clk" }, 94 { .fw_name = "spdif0_rx" }, 95 { .fw_name = "spdif1_rx" }, 96 { .fw_name = "sai0_rx_bclk" }, 97 { .fw_name = "sai0_tx_bclk" }, 98 { .fw_name = "sai1_rx_bclk" }, 99 { .fw_name = "sai1_tx_bclk" }, 100 { .fw_name = "sai2_rx_bclk" }, 101 { .fw_name = "sai3_rx_bclk" }, 102 { .fw_name = "sai4_rx_bclk" }, 103 }; 104 105 static const struct clk_parent_data imx8qm_mclk_out_sels[] = { 106 { .fw_name = "aud_rec_clk0_lpcg_clk" }, 107 { .fw_name = "aud_rec_clk1_lpcg_clk" }, 108 { .fw_name = "dummy" }, 109 { .fw_name = "hdmi_rx_mclk" }, 110 { .fw_name = "spdif0_rx" }, 111 { .fw_name = "spdif1_rx" }, 112 { .fw_name = "sai4_rx_bclk" }, 113 { .fw_name = "sai6_rx_bclk" }, 114 }; 115 116 #define ACM_AUD_CLK0_SEL_INDEX 2 117 #define ACM_AUD_CLK1_SEL_INDEX 3 118 119 static struct clk_parent_data imx8qm_mclk_sels[] = { 120 { .fw_name = "aud_pll_div_clk0_lpcg_clk" }, 121 { .fw_name = "aud_pll_div_clk1_lpcg_clk" }, 122 { }, /* clk_hw pointer of "acm_aud_clk0_sel" */ 123 { }, /* clk_hw pointer of "acm_aud_clk1_sel" */ 124 }; 125 126 static const struct clk_parent_data imx8qm_asrc_mux_clk_sels[] = { 127 { .fw_name = "sai4_rx_bclk" }, 128 { .fw_name = "sai5_tx_bclk" }, 129 { .index = -1 }, 130 { .fw_name = "dummy" }, 131 132 }; 133 134 static struct clk_imx8_acm_sel imx8qm_sels[] = { 135 { "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x000000, 0, 5 }, 136 { "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x010000, 0, 5 }, 137 { "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x020000, 0, 3 }, 138 { "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x030000, 0, 3 }, 139 { "acm_asrc0_mclk_sel", IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL, imx8qm_asrc_mux_clk_sels, ARRAY_SIZE(imx8qm_asrc_mux_clk_sels), 0x040000, 0, 2 }, 140 { "acm_esai0_mclk_sel", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x060000, 0, 2 }, 141 { "acm_esai1_mclk_sel", IMX_ADMA_ACM_ESAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x070000, 0, 2 }, 142 { "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0E0000, 0, 2 }, 143 { "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0F0000, 0, 2 }, 144 { "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x100000, 0, 2 }, 145 { "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x110000, 0, 2 }, 146 { "acm_sai4_mclk_sel", IMX_ADMA_ACM_SAI4_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x120000, 0, 2 }, 147 { "acm_sai5_mclk_sel", IMX_ADMA_ACM_SAI5_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x130000, 0, 2 }, 148 { "acm_sai6_mclk_sel", IMX_ADMA_ACM_SAI6_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x140000, 0, 2 }, 149 { "acm_sai7_mclk_sel", IMX_ADMA_ACM_SAI7_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x150000, 0, 2 }, 150 { "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1A0000, 0, 2 }, 151 { "acm_spdif1_mclk_sel", IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1B0000, 0, 2 }, 152 { "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1C0000, 0, 2 }, 153 }; 154 155 static const struct clk_parent_data imx8qxp_aud_clk_sels[] = { 156 { .fw_name = "aud_rec_clk0_lpcg_clk" }, 157 { .fw_name = "aud_rec_clk1_lpcg_clk" }, 158 { .fw_name = "ext_aud_mclk0" }, 159 { .fw_name = "ext_aud_mclk1" }, 160 { .fw_name = "esai0_rx_clk" }, 161 { .fw_name = "esai0_rx_hf_clk" }, 162 { .fw_name = "esai0_tx_clk" }, 163 { .fw_name = "esai0_tx_hf_clk" }, 164 { .fw_name = "spdif0_rx" }, 165 { .fw_name = "sai0_rx_bclk" }, 166 { .fw_name = "sai0_tx_bclk" }, 167 { .fw_name = "sai1_rx_bclk" }, 168 { .fw_name = "sai1_tx_bclk" }, 169 { .fw_name = "sai2_rx_bclk" }, 170 { .fw_name = "sai3_rx_bclk" }, 171 }; 172 173 static const struct clk_parent_data imx8qxp_mclk_out_sels[] = { 174 { .fw_name = "aud_rec_clk0_lpcg_clk" }, 175 { .fw_name = "aud_rec_clk1_lpcg_clk" }, 176 { .index = -1 }, 177 { .index = -1 }, 178 { .fw_name = "spdif0_rx" }, 179 { .index = -1 }, 180 { .index = -1 }, 181 { .fw_name = "sai4_rx_bclk" }, 182 }; 183 184 static struct clk_parent_data imx8qxp_mclk_sels[] = { 185 { .fw_name = "aud_pll_div_clk0_lpcg_clk" }, 186 { .fw_name = "aud_pll_div_clk1_lpcg_clk" }, 187 { }, /* clk_hw pointer of "acm_aud_clk0_sel" */ 188 { }, /* clk_hw pointer of "acm_aud_clk1_sel" */ 189 }; 190 191 static struct clk_imx8_acm_sel imx8qxp_sels[] = { 192 { "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qxp_aud_clk_sels, ARRAY_SIZE(imx8qxp_aud_clk_sels), 0x000000, 0, 5 }, 193 { "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qxp_aud_clk_sels, ARRAY_SIZE(imx8qxp_aud_clk_sels), 0x010000, 0, 5 }, 194 { "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8qxp_mclk_out_sels, ARRAY_SIZE(imx8qxp_mclk_out_sels), 0x020000, 0, 3 }, 195 { "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8qxp_mclk_out_sels, ARRAY_SIZE(imx8qxp_mclk_out_sels), 0x030000, 0, 3 }, 196 { "acm_esai0_mclk_sel", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x060000, 0, 2 }, 197 { "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x0E0000, 0, 2 }, 198 { "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x0F0000, 0, 2 }, 199 { "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x100000, 0, 2 }, 200 { "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x110000, 0, 2 }, 201 { "acm_sai4_mclk_sel", IMX_ADMA_ACM_SAI4_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x140000, 0, 2 }, 202 { "acm_sai5_mclk_sel", IMX_ADMA_ACM_SAI5_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x150000, 0, 2 }, 203 { "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x1A0000, 0, 2 }, 204 { "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x1C0000, 0, 2 }, 205 }; 206 207 static const struct clk_parent_data imx8dxl_aud_clk_sels[] = { 208 { .fw_name = "aud_rec_clk0_lpcg_clk" }, 209 { .fw_name = "aud_rec_clk1_lpcg_clk" }, 210 { .fw_name = "ext_aud_mclk0" }, 211 { .fw_name = "ext_aud_mclk1" }, 212 { .index = -1 }, 213 { .index = -1 }, 214 { .index = -1 }, 215 { .index = -1 }, 216 { .fw_name = "spdif0_rx" }, 217 { .fw_name = "sai0_rx_bclk" }, 218 { .fw_name = "sai0_tx_bclk" }, 219 { .fw_name = "sai1_rx_bclk" }, 220 { .fw_name = "sai1_tx_bclk" }, 221 { .fw_name = "sai2_rx_bclk" }, 222 { .fw_name = "sai3_rx_bclk" }, 223 }; 224 225 static const struct clk_parent_data imx8dxl_mclk_out_sels[] = { 226 { .fw_name = "aud_rec_clk0_lpcg_clk" }, 227 { .fw_name = "aud_rec_clk1_lpcg_clk" }, 228 { .index = -1 }, 229 { .index = -1 }, 230 { .fw_name = "spdif0_rx" }, 231 { .index = -1 }, 232 { .index = -1 }, 233 { .index = -1 }, 234 }; 235 236 static struct clk_parent_data imx8dxl_mclk_sels[] = { 237 { .fw_name = "aud_pll_div_clk0_lpcg_clk" }, 238 { .fw_name = "aud_pll_div_clk1_lpcg_clk" }, 239 { }, /* clk_hw pointer of "acm_aud_clk0_sel" */ 240 { }, /* clk_hw pointer of "acm_aud_clk1_sel" */ 241 }; 242 243 static struct clk_imx8_acm_sel imx8dxl_sels[] = { 244 { "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8dxl_aud_clk_sels, ARRAY_SIZE(imx8dxl_aud_clk_sels), 0x000000, 0, 5 }, 245 { "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8dxl_aud_clk_sels, ARRAY_SIZE(imx8dxl_aud_clk_sels), 0x010000, 0, 5 }, 246 { "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8dxl_mclk_out_sels, ARRAY_SIZE(imx8dxl_mclk_out_sels), 0x020000, 0, 3 }, 247 { "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8dxl_mclk_out_sels, ARRAY_SIZE(imx8dxl_mclk_out_sels), 0x030000, 0, 3 }, 248 { "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x0E0000, 0, 2 }, 249 { "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x0F0000, 0, 2 }, 250 { "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x100000, 0, 2 }, 251 { "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x110000, 0, 2 }, 252 { "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x1A0000, 0, 2 }, 253 { "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x1C0000, 0, 2 }, 254 }; 255 256 /** 257 * clk_imx_acm_attach_pm_domains: attach multi power domains 258 * @dev: device pointer 259 * @dev_pm: power domains for device 260 */ 261 static int clk_imx_acm_attach_pm_domains(struct device *dev, 262 struct clk_imx_acm_pm_domains *dev_pm) 263 { 264 int ret; 265 int i; 266 267 dev_pm->num_domains = of_count_phandle_with_args(dev->of_node, "power-domains", 268 "#power-domain-cells"); 269 if (dev_pm->num_domains <= 1) 270 return 0; 271 272 dev_pm->pd_dev = devm_kmalloc_array(dev, dev_pm->num_domains, 273 sizeof(*dev_pm->pd_dev), 274 GFP_KERNEL); 275 if (!dev_pm->pd_dev) 276 return -ENOMEM; 277 278 dev_pm->pd_dev_link = devm_kmalloc_array(dev, 279 dev_pm->num_domains, 280 sizeof(*dev_pm->pd_dev_link), 281 GFP_KERNEL); 282 if (!dev_pm->pd_dev_link) 283 return -ENOMEM; 284 285 for (i = 0; i < dev_pm->num_domains; i++) { 286 dev_pm->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i); 287 if (IS_ERR(dev_pm->pd_dev[i])) { 288 ret = PTR_ERR(dev_pm->pd_dev[i]); 289 goto detach_pm; 290 } 291 292 dev_pm->pd_dev_link[i] = device_link_add(dev, 293 dev_pm->pd_dev[i], 294 DL_FLAG_STATELESS | 295 DL_FLAG_PM_RUNTIME | 296 DL_FLAG_RPM_ACTIVE); 297 if (IS_ERR(dev_pm->pd_dev_link[i])) { 298 dev_pm_domain_detach(dev_pm->pd_dev[i], false); 299 ret = PTR_ERR(dev_pm->pd_dev_link[i]); 300 goto detach_pm; 301 } 302 } 303 return 0; 304 305 detach_pm: 306 while (--i >= 0) { 307 device_link_del(dev_pm->pd_dev_link[i]); 308 dev_pm_domain_detach(dev_pm->pd_dev[i], false); 309 } 310 return ret; 311 } 312 313 /** 314 * clk_imx_acm_detach_pm_domains: detach multi power domains 315 * @dev: deivice pointer 316 * @dev_pm: multi power domain for device 317 */ 318 static void clk_imx_acm_detach_pm_domains(struct device *dev, 319 struct clk_imx_acm_pm_domains *dev_pm) 320 { 321 int i; 322 323 if (dev_pm->num_domains <= 1) 324 return; 325 326 for (i = 0; i < dev_pm->num_domains; i++) { 327 device_link_del(dev_pm->pd_dev_link[i]); 328 dev_pm_domain_detach(dev_pm->pd_dev[i], false); 329 } 330 } 331 332 static int imx8_acm_clk_probe(struct platform_device *pdev) 333 { 334 struct clk_hw_onecell_data *clk_hw_data; 335 struct device *dev = &pdev->dev; 336 struct clk_imx8_acm_sel *sels; 337 struct imx8_acm_priv *priv; 338 struct clk_hw **hws; 339 void __iomem *base; 340 int ret; 341 int i; 342 343 base = devm_of_iomap(dev, dev->of_node, 0, NULL); 344 if (WARN_ON(IS_ERR(base))) 345 return PTR_ERR(base); 346 347 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 348 if (!priv) 349 return -ENOMEM; 350 351 priv->reg = base; 352 priv->soc_data = of_device_get_match_data(dev); 353 platform_set_drvdata(pdev, priv); 354 355 clk_hw_data = devm_kzalloc(&pdev->dev, struct_size(clk_hw_data, hws, IMX_ADMA_ACM_CLK_END), 356 GFP_KERNEL); 357 if (!clk_hw_data) 358 return -ENOMEM; 359 360 clk_hw_data->num = IMX_ADMA_ACM_CLK_END; 361 hws = clk_hw_data->hws; 362 363 ret = clk_imx_acm_attach_pm_domains(&pdev->dev, &priv->dev_pm); 364 if (ret) 365 return ret; 366 367 pm_runtime_enable(&pdev->dev); 368 pm_runtime_get_sync(&pdev->dev); 369 370 sels = priv->soc_data->sels; 371 for (i = 0; i < priv->soc_data->num_sels; i++) { 372 hws[sels[i].clkid] = devm_clk_hw_register_mux_parent_data_table(dev, 373 sels[i].name, sels[i].parents, 374 sels[i].num_parents, 0, 375 base + sels[i].reg, 376 sels[i].shift, sels[i].width, 377 0, NULL, NULL); 378 if (IS_ERR(hws[sels[i].clkid])) { 379 ret = PTR_ERR(hws[sels[i].clkid]); 380 imx_check_clk_hws(hws, IMX_ADMA_ACM_CLK_END); 381 goto err_clk_register; 382 } 383 384 /* 385 * The IMX_ADMA_ACM_AUD_CLK0_SEL and IMX_ADMA_ACM_AUD_CLK1_SEL are 386 * registered first. After registration, update the clk_hw pointer 387 * to imx8qm/qxp/dxl_mclk_sels structures. 388 */ 389 if (sels[i].clkid == IMX_ADMA_ACM_AUD_CLK0_SEL) 390 priv->soc_data->mclk_sels[ACM_AUD_CLK0_SEL_INDEX].hw = 391 hws[IMX_ADMA_ACM_AUD_CLK0_SEL]; 392 if (sels[i].clkid == IMX_ADMA_ACM_AUD_CLK1_SEL) 393 priv->soc_data->mclk_sels[ACM_AUD_CLK1_SEL_INDEX].hw = 394 hws[IMX_ADMA_ACM_AUD_CLK1_SEL]; 395 } 396 397 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data); 398 if (ret < 0) { 399 dev_err(dev, "failed to register hws for ACM\n"); 400 goto err_clk_register; 401 } 402 403 pm_runtime_put_sync(&pdev->dev); 404 return 0; 405 406 err_clk_register: 407 pm_runtime_put_sync(&pdev->dev); 408 pm_runtime_disable(&pdev->dev); 409 clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm); 410 411 return ret; 412 } 413 414 static void imx8_acm_clk_remove(struct platform_device *pdev) 415 { 416 struct imx8_acm_priv *priv = dev_get_drvdata(&pdev->dev); 417 418 pm_runtime_disable(&pdev->dev); 419 420 clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm); 421 } 422 423 static const struct imx8_acm_soc_data imx8qm_acm_data = { 424 .sels = imx8qm_sels, 425 .num_sels = ARRAY_SIZE(imx8qm_sels), 426 .mclk_sels = imx8qm_mclk_sels, 427 }; 428 429 static const struct imx8_acm_soc_data imx8qxp_acm_data = { 430 .sels = imx8qxp_sels, 431 .num_sels = ARRAY_SIZE(imx8qxp_sels), 432 .mclk_sels = imx8qxp_mclk_sels, 433 }; 434 435 static const struct imx8_acm_soc_data imx8dxl_acm_data = { 436 .sels = imx8dxl_sels, 437 .num_sels = ARRAY_SIZE(imx8dxl_sels), 438 .mclk_sels = imx8dxl_mclk_sels, 439 }; 440 441 static const struct of_device_id imx8_acm_match[] = { 442 { .compatible = "fsl,imx8qm-acm", .data = &imx8qm_acm_data }, 443 { .compatible = "fsl,imx8qxp-acm", .data = &imx8qxp_acm_data }, 444 { .compatible = "fsl,imx8dxl-acm", .data = &imx8dxl_acm_data }, 445 { /* sentinel */ } 446 }; 447 MODULE_DEVICE_TABLE(of, imx8_acm_match); 448 449 static int __maybe_unused imx8_acm_runtime_suspend(struct device *dev) 450 { 451 struct imx8_acm_priv *priv = dev_get_drvdata(dev); 452 struct clk_imx8_acm_sel *sels; 453 int i; 454 455 sels = priv->soc_data->sels; 456 457 for (i = 0; i < priv->soc_data->num_sels; i++) 458 priv->regs[i] = readl_relaxed(priv->reg + sels[i].reg); 459 460 return 0; 461 } 462 463 static int __maybe_unused imx8_acm_runtime_resume(struct device *dev) 464 { 465 struct imx8_acm_priv *priv = dev_get_drvdata(dev); 466 struct clk_imx8_acm_sel *sels; 467 int i; 468 469 sels = priv->soc_data->sels; 470 471 for (i = 0; i < priv->soc_data->num_sels; i++) 472 writel_relaxed(priv->regs[i], priv->reg + sels[i].reg); 473 474 return 0; 475 } 476 477 static const struct dev_pm_ops imx8_acm_pm_ops = { 478 SET_RUNTIME_PM_OPS(imx8_acm_runtime_suspend, 479 imx8_acm_runtime_resume, NULL) 480 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 481 pm_runtime_force_resume) 482 }; 483 484 static struct platform_driver imx8_acm_clk_driver = { 485 .driver = { 486 .name = "imx8-acm", 487 .of_match_table = imx8_acm_match, 488 .pm = &imx8_acm_pm_ops, 489 }, 490 .probe = imx8_acm_clk_probe, 491 .remove = imx8_acm_clk_remove, 492 }; 493 module_platform_driver(imx8_acm_clk_driver); 494 495 MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>"); 496 MODULE_DESCRIPTION("Freescale i.MX8 Audio Clock Mux driver"); 497 MODULE_LICENSE("GPL"); 498