xref: /linux/drivers/clk/imx/clk-imx8-acm.c (revision ef23d44b7fcbd19773dcedcb50ca2f625107604f)
1d3a0946dSShengjiu Wang // SPDX-License-Identifier: GPL-2.0+
2d3a0946dSShengjiu Wang //
3d3a0946dSShengjiu Wang // Copyright 2023 NXP
4d3a0946dSShengjiu Wang //
5d3a0946dSShengjiu Wang 
6d3a0946dSShengjiu Wang #include <dt-bindings/clock/imx8-clock.h>
7d3a0946dSShengjiu Wang #include <linux/clk-provider.h>
8d3a0946dSShengjiu Wang #include <linux/device.h>
9d3a0946dSShengjiu Wang #include <linux/err.h>
10d3a0946dSShengjiu Wang #include <linux/io.h>
11d3a0946dSShengjiu Wang #include <linux/module.h>
12d3a0946dSShengjiu Wang #include <linux/of.h>
13d3a0946dSShengjiu Wang #include <linux/of_device.h>
14d3a0946dSShengjiu Wang #include <linux/platform_device.h>
15d3a0946dSShengjiu Wang #include <linux/pm_domain.h>
16d3a0946dSShengjiu Wang #include <linux/pm_runtime.h>
17d3a0946dSShengjiu Wang #include <linux/slab.h>
18d3a0946dSShengjiu Wang 
19d3a0946dSShengjiu Wang #include "clk.h"
20d3a0946dSShengjiu Wang 
21d3a0946dSShengjiu Wang /**
22d3a0946dSShengjiu Wang  * struct clk_imx_acm_pm_domains - structure for multi power domain
23d3a0946dSShengjiu Wang  * @pd_dev: power domain device
24d3a0946dSShengjiu Wang  * @pd_dev_link: power domain device link
25d3a0946dSShengjiu Wang  * @num_domains: power domain nummber
26d3a0946dSShengjiu Wang  */
27d3a0946dSShengjiu Wang struct clk_imx_acm_pm_domains {
28d3a0946dSShengjiu Wang 	struct device **pd_dev;
29d3a0946dSShengjiu Wang 	struct device_link **pd_dev_link;
30d3a0946dSShengjiu Wang 	int    num_domains;
31d3a0946dSShengjiu Wang };
32d3a0946dSShengjiu Wang 
33d3a0946dSShengjiu Wang /**
34d3a0946dSShengjiu Wang  * struct clk_imx8_acm_sel - for clock mux
35d3a0946dSShengjiu Wang  * @name: clock name
36d3a0946dSShengjiu Wang  * @clkid: clock id
37d3a0946dSShengjiu Wang  * @parents: clock parents
38d3a0946dSShengjiu Wang  * @num_parents: clock parents number
39d3a0946dSShengjiu Wang  * @reg: register offset
40d3a0946dSShengjiu Wang  * @shift: bit shift in register
41d3a0946dSShengjiu Wang  * @width: bits width
42d3a0946dSShengjiu Wang  */
43d3a0946dSShengjiu Wang struct clk_imx8_acm_sel {
44d3a0946dSShengjiu Wang 	const char			*name;
45d3a0946dSShengjiu Wang 	int				clkid;
46d3a0946dSShengjiu Wang 	const struct clk_parent_data	*parents;	/* For mux */
47d3a0946dSShengjiu Wang 	int				num_parents;
48d3a0946dSShengjiu Wang 	u32				reg;
49d3a0946dSShengjiu Wang 	u8				shift;
50d3a0946dSShengjiu Wang 	u8				width;
51d3a0946dSShengjiu Wang };
52d3a0946dSShengjiu Wang 
53d3a0946dSShengjiu Wang /**
54d3a0946dSShengjiu Wang  * struct imx8_acm_soc_data - soc specific data
55d3a0946dSShengjiu Wang  * @sels: pointer to struct clk_imx8_acm_sel
56d3a0946dSShengjiu Wang  * @num_sels: numbers of items
57d3a0946dSShengjiu Wang  */
58d3a0946dSShengjiu Wang struct imx8_acm_soc_data {
59d3a0946dSShengjiu Wang 	struct clk_imx8_acm_sel *sels;
60d3a0946dSShengjiu Wang 	unsigned int num_sels;
61d3a0946dSShengjiu Wang };
62d3a0946dSShengjiu Wang 
63d3a0946dSShengjiu Wang /**
64d3a0946dSShengjiu Wang  * struct imx8_acm_priv - private structure
65d3a0946dSShengjiu Wang  * @dev_pm: multi power domain
66d3a0946dSShengjiu Wang  * @soc_data: pointer to soc data
67d3a0946dSShengjiu Wang  * @reg: base address of registers
68d3a0946dSShengjiu Wang  * @regs: save registers for suspend
69d3a0946dSShengjiu Wang  */
70d3a0946dSShengjiu Wang struct imx8_acm_priv {
71d3a0946dSShengjiu Wang 	struct clk_imx_acm_pm_domains dev_pm;
72d3a0946dSShengjiu Wang 	const struct imx8_acm_soc_data *soc_data;
73d3a0946dSShengjiu Wang 	void __iomem *reg;
74d3a0946dSShengjiu Wang 	u32 regs[IMX_ADMA_ACM_CLK_END];
75d3a0946dSShengjiu Wang };
76d3a0946dSShengjiu Wang 
77d3a0946dSShengjiu Wang static const struct clk_parent_data imx8qm_aud_clk_sels[] = {
78d3a0946dSShengjiu Wang 	{ .fw_name = "aud_rec_clk0_lpcg_clk" },
79d3a0946dSShengjiu Wang 	{ .fw_name = "aud_rec_clk1_lpcg_clk" },
80d3a0946dSShengjiu Wang 	{ .fw_name = "mlb_clk" },
81d3a0946dSShengjiu Wang 	{ .fw_name = "hdmi_rx_mclk" },
82d3a0946dSShengjiu Wang 	{ .fw_name = "ext_aud_mclk0" },
83d3a0946dSShengjiu Wang 	{ .fw_name = "ext_aud_mclk1" },
84d3a0946dSShengjiu Wang 	{ .fw_name = "esai0_rx_clk" },
85d3a0946dSShengjiu Wang 	{ .fw_name = "esai0_rx_hf_clk" },
86d3a0946dSShengjiu Wang 	{ .fw_name = "esai0_tx_clk" },
87d3a0946dSShengjiu Wang 	{ .fw_name = "esai0_tx_hf_clk" },
88d3a0946dSShengjiu Wang 	{ .fw_name = "esai1_rx_clk" },
89d3a0946dSShengjiu Wang 	{ .fw_name = "esai1_rx_hf_clk" },
90d3a0946dSShengjiu Wang 	{ .fw_name = "esai1_tx_clk" },
91d3a0946dSShengjiu Wang 	{ .fw_name = "esai1_tx_hf_clk" },
92d3a0946dSShengjiu Wang 	{ .fw_name = "spdif0_rx" },
93d3a0946dSShengjiu Wang 	{ .fw_name = "spdif1_rx" },
94d3a0946dSShengjiu Wang 	{ .fw_name = "sai0_rx_bclk" },
95d3a0946dSShengjiu Wang 	{ .fw_name = "sai0_tx_bclk" },
96d3a0946dSShengjiu Wang 	{ .fw_name = "sai1_rx_bclk" },
97d3a0946dSShengjiu Wang 	{ .fw_name = "sai1_tx_bclk" },
98d3a0946dSShengjiu Wang 	{ .fw_name = "sai2_rx_bclk" },
99d3a0946dSShengjiu Wang 	{ .fw_name = "sai3_rx_bclk" },
100d3a0946dSShengjiu Wang 	{ .fw_name = "sai4_rx_bclk" },
101d3a0946dSShengjiu Wang };
102d3a0946dSShengjiu Wang 
103d3a0946dSShengjiu Wang static const struct clk_parent_data imx8qm_mclk_out_sels[] = {
104d3a0946dSShengjiu Wang 	{ .fw_name = "aud_rec_clk0_lpcg_clk" },
105d3a0946dSShengjiu Wang 	{ .fw_name = "aud_rec_clk1_lpcg_clk" },
106d3a0946dSShengjiu Wang 	{ .fw_name = "mlb_clk" },
107d3a0946dSShengjiu Wang 	{ .fw_name = "hdmi_rx_mclk" },
108d3a0946dSShengjiu Wang 	{ .fw_name = "spdif0_rx" },
109d3a0946dSShengjiu Wang 	{ .fw_name = "spdif1_rx" },
110d3a0946dSShengjiu Wang 	{ .fw_name = "sai4_rx_bclk" },
111d3a0946dSShengjiu Wang 	{ .fw_name = "sai6_rx_bclk" },
112d3a0946dSShengjiu Wang };
113d3a0946dSShengjiu Wang 
114d3a0946dSShengjiu Wang static const struct clk_parent_data imx8qm_mclk_sels[] = {
115d3a0946dSShengjiu Wang 	{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
116d3a0946dSShengjiu Wang 	{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
117d3a0946dSShengjiu Wang 	{ .fw_name = "acm_aud_clk0_sel" },
118d3a0946dSShengjiu Wang 	{ .fw_name = "acm_aud_clk1_sel" },
119d3a0946dSShengjiu Wang };
120d3a0946dSShengjiu Wang 
121d3a0946dSShengjiu Wang static const struct clk_parent_data imx8qm_asrc_mux_clk_sels[] = {
122d3a0946dSShengjiu Wang 	{ .fw_name = "sai4_rx_bclk" },
123d3a0946dSShengjiu Wang 	{ .fw_name = "sai5_tx_bclk" },
124d3a0946dSShengjiu Wang 	{ .index = -1 },
125d3a0946dSShengjiu Wang 	{ .fw_name = "mlb_clk" },
126d3a0946dSShengjiu Wang 
127d3a0946dSShengjiu Wang };
128d3a0946dSShengjiu Wang 
129d3a0946dSShengjiu Wang static struct clk_imx8_acm_sel imx8qm_sels[] = {
130d3a0946dSShengjiu Wang 	{ "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x000000, 0, 5 },
131d3a0946dSShengjiu Wang 	{ "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x010000, 0, 5 },
132d3a0946dSShengjiu Wang 	{ "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x020000, 0, 3 },
133d3a0946dSShengjiu Wang 	{ "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x030000, 0, 3 },
134d3a0946dSShengjiu Wang 	{ "acm_asrc0_mclk_sel", IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL, imx8qm_asrc_mux_clk_sels, ARRAY_SIZE(imx8qm_asrc_mux_clk_sels), 0x040000, 0, 2 },
135d3a0946dSShengjiu Wang 	{ "acm_esai0_mclk_sel", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x060000, 0, 2 },
136d3a0946dSShengjiu Wang 	{ "acm_esai1_mclk_sel", IMX_ADMA_ACM_ESAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x070000, 0, 2 },
137d3a0946dSShengjiu Wang 	{ "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0E0000, 0, 2 },
138d3a0946dSShengjiu Wang 	{ "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0F0000, 0, 2 },
139d3a0946dSShengjiu Wang 	{ "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x100000, 0, 2 },
140d3a0946dSShengjiu Wang 	{ "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x110000, 0, 2 },
141d3a0946dSShengjiu Wang 	{ "acm_sai4_mclk_sel", IMX_ADMA_ACM_SAI4_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x120000, 0, 2 },
142d3a0946dSShengjiu Wang 	{ "acm_sai5_mclk_sel", IMX_ADMA_ACM_SAI5_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x130000, 0, 2 },
143d3a0946dSShengjiu Wang 	{ "acm_sai6_mclk_sel", IMX_ADMA_ACM_SAI6_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x140000, 0, 2 },
144d3a0946dSShengjiu Wang 	{ "acm_sai7_mclk_sel", IMX_ADMA_ACM_SAI7_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x150000, 0, 2 },
145d3a0946dSShengjiu Wang 	{ "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1A0000, 0, 2 },
146d3a0946dSShengjiu Wang 	{ "acm_spdif1_mclk_sel", IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1B0000, 0, 2 },
147d3a0946dSShengjiu Wang 	{ "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1C0000, 0, 2 },
148d3a0946dSShengjiu Wang };
149d3a0946dSShengjiu Wang 
150d3a0946dSShengjiu Wang static const struct clk_parent_data imx8qxp_aud_clk_sels[] = {
151d3a0946dSShengjiu Wang 	{ .fw_name = "aud_rec_clk0_lpcg_clk" },
152d3a0946dSShengjiu Wang 	{ .fw_name = "aud_rec_clk1_lpcg_clk" },
153d3a0946dSShengjiu Wang 	{ .fw_name = "ext_aud_mclk0" },
154d3a0946dSShengjiu Wang 	{ .fw_name = "ext_aud_mclk1" },
155d3a0946dSShengjiu Wang 	{ .fw_name = "esai0_rx_clk" },
156d3a0946dSShengjiu Wang 	{ .fw_name = "esai0_rx_hf_clk" },
157d3a0946dSShengjiu Wang 	{ .fw_name = "esai0_tx_clk" },
158d3a0946dSShengjiu Wang 	{ .fw_name = "esai0_tx_hf_clk" },
159d3a0946dSShengjiu Wang 	{ .fw_name = "spdif0_rx" },
160d3a0946dSShengjiu Wang 	{ .fw_name = "sai0_rx_bclk" },
161d3a0946dSShengjiu Wang 	{ .fw_name = "sai0_tx_bclk" },
162d3a0946dSShengjiu Wang 	{ .fw_name = "sai1_rx_bclk" },
163d3a0946dSShengjiu Wang 	{ .fw_name = "sai1_tx_bclk" },
164d3a0946dSShengjiu Wang 	{ .fw_name = "sai2_rx_bclk" },
165d3a0946dSShengjiu Wang 	{ .fw_name = "sai3_rx_bclk" },
166d3a0946dSShengjiu Wang };
167d3a0946dSShengjiu Wang 
168d3a0946dSShengjiu Wang static const struct clk_parent_data imx8qxp_mclk_out_sels[] = {
169d3a0946dSShengjiu Wang 	{ .fw_name = "aud_rec_clk0_lpcg_clk" },
170d3a0946dSShengjiu Wang 	{ .fw_name = "aud_rec_clk1_lpcg_clk" },
171d3a0946dSShengjiu Wang 	{ .index = -1 },
172d3a0946dSShengjiu Wang 	{ .index = -1 },
173d3a0946dSShengjiu Wang 	{ .fw_name = "spdif0_rx" },
174d3a0946dSShengjiu Wang 	{ .index = -1 },
175d3a0946dSShengjiu Wang 	{ .index = -1 },
176d3a0946dSShengjiu Wang 	{ .fw_name = "sai4_rx_bclk" },
177d3a0946dSShengjiu Wang };
178d3a0946dSShengjiu Wang 
179d3a0946dSShengjiu Wang static const struct clk_parent_data imx8qxp_mclk_sels[] = {
180d3a0946dSShengjiu Wang 	{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
181d3a0946dSShengjiu Wang 	{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
182d3a0946dSShengjiu Wang 	{ .fw_name = "acm_aud_clk0_sel" },
183d3a0946dSShengjiu Wang 	{ .fw_name = "acm_aud_clk1_sel" },
184d3a0946dSShengjiu Wang };
185d3a0946dSShengjiu Wang 
186d3a0946dSShengjiu Wang static struct clk_imx8_acm_sel imx8qxp_sels[] = {
187d3a0946dSShengjiu Wang 	{ "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qxp_aud_clk_sels, ARRAY_SIZE(imx8qxp_aud_clk_sels), 0x000000, 0, 5 },
188d3a0946dSShengjiu Wang 	{ "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qxp_aud_clk_sels, ARRAY_SIZE(imx8qxp_aud_clk_sels), 0x010000, 0, 5 },
189d3a0946dSShengjiu Wang 	{ "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8qxp_mclk_out_sels, ARRAY_SIZE(imx8qxp_mclk_out_sels), 0x020000, 0, 3 },
190d3a0946dSShengjiu Wang 	{ "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8qxp_mclk_out_sels, ARRAY_SIZE(imx8qxp_mclk_out_sels), 0x030000, 0, 3 },
191d3a0946dSShengjiu Wang 	{ "acm_esai0_mclk_sel", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x060000, 0, 2 },
192d3a0946dSShengjiu Wang 	{ "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x0E0000, 0, 2 },
193d3a0946dSShengjiu Wang 	{ "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x0F0000, 0, 2 },
194d3a0946dSShengjiu Wang 	{ "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x100000, 0, 2 },
195d3a0946dSShengjiu Wang 	{ "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x110000, 0, 2 },
196d3a0946dSShengjiu Wang 	{ "acm_sai4_mclk_sel", IMX_ADMA_ACM_SAI4_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x140000, 0, 2 },
197d3a0946dSShengjiu Wang 	{ "acm_sai5_mclk_sel", IMX_ADMA_ACM_SAI5_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x150000, 0, 2 },
198d3a0946dSShengjiu Wang 	{ "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x1A0000, 0, 2 },
199d3a0946dSShengjiu Wang 	{ "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x1C0000, 0, 2 },
200d3a0946dSShengjiu Wang };
201d3a0946dSShengjiu Wang 
202d3a0946dSShengjiu Wang static const struct clk_parent_data imx8dxl_aud_clk_sels[] = {
203d3a0946dSShengjiu Wang 	{ .fw_name = "aud_rec_clk0_lpcg_clk" },
204d3a0946dSShengjiu Wang 	{ .fw_name = "aud_rec_clk1_lpcg_clk" },
205d3a0946dSShengjiu Wang 	{ .fw_name = "ext_aud_mclk0" },
206d3a0946dSShengjiu Wang 	{ .fw_name = "ext_aud_mclk1" },
207d3a0946dSShengjiu Wang 	{ .index = -1 },
208d3a0946dSShengjiu Wang 	{ .index = -1 },
209d3a0946dSShengjiu Wang 	{ .index = -1 },
210d3a0946dSShengjiu Wang 	{ .index = -1 },
211d3a0946dSShengjiu Wang 	{ .fw_name = "spdif0_rx" },
212d3a0946dSShengjiu Wang 	{ .fw_name = "sai0_rx_bclk" },
213d3a0946dSShengjiu Wang 	{ .fw_name = "sai0_tx_bclk" },
214d3a0946dSShengjiu Wang 	{ .fw_name = "sai1_rx_bclk" },
215d3a0946dSShengjiu Wang 	{ .fw_name = "sai1_tx_bclk" },
216d3a0946dSShengjiu Wang 	{ .fw_name = "sai2_rx_bclk" },
217d3a0946dSShengjiu Wang 	{ .fw_name = "sai3_rx_bclk" },
218d3a0946dSShengjiu Wang };
219d3a0946dSShengjiu Wang 
220d3a0946dSShengjiu Wang static const struct clk_parent_data imx8dxl_mclk_out_sels[] = {
221d3a0946dSShengjiu Wang 	{ .fw_name = "aud_rec_clk0_lpcg_clk" },
222d3a0946dSShengjiu Wang 	{ .fw_name = "aud_rec_clk1_lpcg_clk" },
223d3a0946dSShengjiu Wang 	{ .index = -1 },
224d3a0946dSShengjiu Wang 	{ .index = -1 },
225d3a0946dSShengjiu Wang 	{ .fw_name = "spdif0_rx" },
226d3a0946dSShengjiu Wang 	{ .index = -1 },
227d3a0946dSShengjiu Wang 	{ .index = -1 },
228d3a0946dSShengjiu Wang 	{ .index = -1 },
229d3a0946dSShengjiu Wang };
230d3a0946dSShengjiu Wang 
231d3a0946dSShengjiu Wang static const struct clk_parent_data imx8dxl_mclk_sels[] = {
232d3a0946dSShengjiu Wang 	{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
233d3a0946dSShengjiu Wang 	{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
234d3a0946dSShengjiu Wang 	{ .fw_name = "acm_aud_clk0_sel" },
235d3a0946dSShengjiu Wang 	{ .fw_name = "acm_aud_clk1_sel" },
236d3a0946dSShengjiu Wang };
237d3a0946dSShengjiu Wang 
238d3a0946dSShengjiu Wang static struct clk_imx8_acm_sel imx8dxl_sels[] = {
239d3a0946dSShengjiu Wang 	{ "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8dxl_aud_clk_sels, ARRAY_SIZE(imx8dxl_aud_clk_sels), 0x000000, 0, 5 },
240d3a0946dSShengjiu Wang 	{ "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8dxl_aud_clk_sels, ARRAY_SIZE(imx8dxl_aud_clk_sels), 0x010000, 0, 5 },
241d3a0946dSShengjiu Wang 	{ "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8dxl_mclk_out_sels, ARRAY_SIZE(imx8dxl_mclk_out_sels), 0x020000, 0, 3 },
242d3a0946dSShengjiu Wang 	{ "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8dxl_mclk_out_sels, ARRAY_SIZE(imx8dxl_mclk_out_sels), 0x030000, 0, 3 },
243d3a0946dSShengjiu Wang 	{ "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x0E0000, 0, 2 },
244d3a0946dSShengjiu Wang 	{ "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x0F0000, 0, 2 },
245d3a0946dSShengjiu Wang 	{ "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x100000, 0, 2 },
246d3a0946dSShengjiu Wang 	{ "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x110000, 0, 2 },
247d3a0946dSShengjiu Wang 	{ "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x1A0000, 0, 2 },
248d3a0946dSShengjiu Wang 	{ "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x1C0000, 0, 2 },
249d3a0946dSShengjiu Wang };
250d3a0946dSShengjiu Wang 
251d3a0946dSShengjiu Wang /**
252d3a0946dSShengjiu Wang  * clk_imx_acm_attach_pm_domains: attach multi power domains
253d3a0946dSShengjiu Wang  * @dev: device pointer
254d3a0946dSShengjiu Wang  * @dev_pm: power domains for device
255d3a0946dSShengjiu Wang  */
256d3a0946dSShengjiu Wang static int clk_imx_acm_attach_pm_domains(struct device *dev,
257d3a0946dSShengjiu Wang 					 struct clk_imx_acm_pm_domains *dev_pm)
258d3a0946dSShengjiu Wang {
259d3a0946dSShengjiu Wang 	int ret;
260d3a0946dSShengjiu Wang 	int i;
261d3a0946dSShengjiu Wang 
262d3a0946dSShengjiu Wang 	dev_pm->num_domains = of_count_phandle_with_args(dev->of_node, "power-domains",
263d3a0946dSShengjiu Wang 							 "#power-domain-cells");
264d3a0946dSShengjiu Wang 	if (dev_pm->num_domains <= 1)
265d3a0946dSShengjiu Wang 		return 0;
266d3a0946dSShengjiu Wang 
267d3a0946dSShengjiu Wang 	dev_pm->pd_dev = devm_kmalloc_array(dev, dev_pm->num_domains,
268d3a0946dSShengjiu Wang 					    sizeof(*dev_pm->pd_dev),
269d3a0946dSShengjiu Wang 					    GFP_KERNEL);
270d3a0946dSShengjiu Wang 	if (!dev_pm->pd_dev)
271d3a0946dSShengjiu Wang 		return -ENOMEM;
272d3a0946dSShengjiu Wang 
273d3a0946dSShengjiu Wang 	dev_pm->pd_dev_link = devm_kmalloc_array(dev,
274d3a0946dSShengjiu Wang 						 dev_pm->num_domains,
275d3a0946dSShengjiu Wang 						 sizeof(*dev_pm->pd_dev_link),
276d3a0946dSShengjiu Wang 						 GFP_KERNEL);
277d3a0946dSShengjiu Wang 	if (!dev_pm->pd_dev_link)
278d3a0946dSShengjiu Wang 		return -ENOMEM;
279d3a0946dSShengjiu Wang 
280d3a0946dSShengjiu Wang 	for (i = 0; i < dev_pm->num_domains; i++) {
281d3a0946dSShengjiu Wang 		dev_pm->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i);
282156624e2SChristophe JAILLET 		if (IS_ERR(dev_pm->pd_dev[i])) {
283156624e2SChristophe JAILLET 			ret = PTR_ERR(dev_pm->pd_dev[i]);
284156624e2SChristophe JAILLET 			goto detach_pm;
285156624e2SChristophe JAILLET 		}
286d3a0946dSShengjiu Wang 
287d3a0946dSShengjiu Wang 		dev_pm->pd_dev_link[i] = device_link_add(dev,
288d3a0946dSShengjiu Wang 							 dev_pm->pd_dev[i],
289d3a0946dSShengjiu Wang 							 DL_FLAG_STATELESS |
290d3a0946dSShengjiu Wang 							 DL_FLAG_PM_RUNTIME |
291d3a0946dSShengjiu Wang 							 DL_FLAG_RPM_ACTIVE);
292d3a0946dSShengjiu Wang 		if (IS_ERR(dev_pm->pd_dev_link[i])) {
293d3a0946dSShengjiu Wang 			dev_pm_domain_detach(dev_pm->pd_dev[i], false);
294d3a0946dSShengjiu Wang 			ret = PTR_ERR(dev_pm->pd_dev_link[i]);
295d3a0946dSShengjiu Wang 			goto detach_pm;
296d3a0946dSShengjiu Wang 		}
297d3a0946dSShengjiu Wang 	}
298d3a0946dSShengjiu Wang 	return 0;
299d3a0946dSShengjiu Wang 
300d3a0946dSShengjiu Wang detach_pm:
301d3a0946dSShengjiu Wang 	while (--i >= 0) {
302d3a0946dSShengjiu Wang 		device_link_del(dev_pm->pd_dev_link[i]);
303d3a0946dSShengjiu Wang 		dev_pm_domain_detach(dev_pm->pd_dev[i], false);
304d3a0946dSShengjiu Wang 	}
305d3a0946dSShengjiu Wang 	return ret;
306d3a0946dSShengjiu Wang }
307d3a0946dSShengjiu Wang 
308d3a0946dSShengjiu Wang /**
309d3a0946dSShengjiu Wang  * clk_imx_acm_detach_pm_domains: detach multi power domains
310d3a0946dSShengjiu Wang  * @dev: deivice pointer
311d3a0946dSShengjiu Wang  * @dev_pm: multi power domain for device
312d3a0946dSShengjiu Wang  */
313d3a0946dSShengjiu Wang static int clk_imx_acm_detach_pm_domains(struct device *dev,
314d3a0946dSShengjiu Wang 					 struct clk_imx_acm_pm_domains *dev_pm)
315d3a0946dSShengjiu Wang {
316d3a0946dSShengjiu Wang 	int i;
317d3a0946dSShengjiu Wang 
318d3a0946dSShengjiu Wang 	if (dev_pm->num_domains <= 1)
319d3a0946dSShengjiu Wang 		return 0;
320d3a0946dSShengjiu Wang 
321d3a0946dSShengjiu Wang 	for (i = 0; i < dev_pm->num_domains; i++) {
322d3a0946dSShengjiu Wang 		device_link_del(dev_pm->pd_dev_link[i]);
323d3a0946dSShengjiu Wang 		dev_pm_domain_detach(dev_pm->pd_dev[i], false);
324d3a0946dSShengjiu Wang 	}
325d3a0946dSShengjiu Wang 
326d3a0946dSShengjiu Wang 	return 0;
327d3a0946dSShengjiu Wang }
328d3a0946dSShengjiu Wang 
329d3a0946dSShengjiu Wang static int imx8_acm_clk_probe(struct platform_device *pdev)
330d3a0946dSShengjiu Wang {
331d3a0946dSShengjiu Wang 	struct clk_hw_onecell_data *clk_hw_data;
332d3a0946dSShengjiu Wang 	struct device *dev = &pdev->dev;
333d3a0946dSShengjiu Wang 	struct clk_imx8_acm_sel *sels;
334d3a0946dSShengjiu Wang 	struct imx8_acm_priv *priv;
335d3a0946dSShengjiu Wang 	struct clk_hw **hws;
336d3a0946dSShengjiu Wang 	void __iomem *base;
337d3a0946dSShengjiu Wang 	int ret;
338d3a0946dSShengjiu Wang 	int i;
339d3a0946dSShengjiu Wang 
340d3a0946dSShengjiu Wang 	base = devm_of_iomap(dev, dev->of_node, 0, NULL);
341d3a0946dSShengjiu Wang 	if (WARN_ON(IS_ERR(base)))
342d3a0946dSShengjiu Wang 		return PTR_ERR(base);
343d3a0946dSShengjiu Wang 
344d3a0946dSShengjiu Wang 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
345d3a0946dSShengjiu Wang 	if (!priv)
346d3a0946dSShengjiu Wang 		return -ENOMEM;
347d3a0946dSShengjiu Wang 
348d3a0946dSShengjiu Wang 	priv->reg = base;
349d3a0946dSShengjiu Wang 	priv->soc_data = of_device_get_match_data(dev);
350d3a0946dSShengjiu Wang 	platform_set_drvdata(pdev, priv);
351d3a0946dSShengjiu Wang 
352d3a0946dSShengjiu Wang 	clk_hw_data = devm_kzalloc(&pdev->dev, struct_size(clk_hw_data, hws, IMX_ADMA_ACM_CLK_END),
353d3a0946dSShengjiu Wang 				   GFP_KERNEL);
354d3a0946dSShengjiu Wang 	if (!clk_hw_data)
355d3a0946dSShengjiu Wang 		return -ENOMEM;
356d3a0946dSShengjiu Wang 
357d3a0946dSShengjiu Wang 	clk_hw_data->num = IMX_ADMA_ACM_CLK_END;
358d3a0946dSShengjiu Wang 	hws = clk_hw_data->hws;
359d3a0946dSShengjiu Wang 
360d3a0946dSShengjiu Wang 	ret = clk_imx_acm_attach_pm_domains(&pdev->dev, &priv->dev_pm);
361d3a0946dSShengjiu Wang 	if (ret)
362d3a0946dSShengjiu Wang 		return ret;
363d3a0946dSShengjiu Wang 
364d3a0946dSShengjiu Wang 	pm_runtime_enable(&pdev->dev);
365d3a0946dSShengjiu Wang 	pm_runtime_get_sync(&pdev->dev);
366d3a0946dSShengjiu Wang 
367d3a0946dSShengjiu Wang 	sels = priv->soc_data->sels;
368d3a0946dSShengjiu Wang 	for (i = 0; i < priv->soc_data->num_sels; i++) {
369d3a0946dSShengjiu Wang 		hws[sels[i].clkid] = devm_clk_hw_register_mux_parent_data_table(dev,
370d3a0946dSShengjiu Wang 										sels[i].name, sels[i].parents,
371d3a0946dSShengjiu Wang 										sels[i].num_parents, 0,
372d3a0946dSShengjiu Wang 										base + sels[i].reg,
373d3a0946dSShengjiu Wang 										sels[i].shift, sels[i].width,
374d3a0946dSShengjiu Wang 										0, NULL, NULL);
375d3a0946dSShengjiu Wang 		if (IS_ERR(hws[sels[i].clkid])) {
3769a0108acSChristophe JAILLET 			ret = PTR_ERR(hws[sels[i].clkid]);
377*ef23d44bSChristophe JAILLET 			imx_check_clk_hws(hws, IMX_ADMA_ACM_CLK_END);
378d3a0946dSShengjiu Wang 			goto err_clk_register;
379d3a0946dSShengjiu Wang 		}
380d3a0946dSShengjiu Wang 	}
381d3a0946dSShengjiu Wang 
382d3a0946dSShengjiu Wang 	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data);
383d3a0946dSShengjiu Wang 	if (ret < 0) {
384d3a0946dSShengjiu Wang 		dev_err(dev, "failed to register hws for ACM\n");
385e9a164e3SChristophe JAILLET 		goto err_clk_register;
386d3a0946dSShengjiu Wang 	}
387d3a0946dSShengjiu Wang 
388d3a0946dSShengjiu Wang 	pm_runtime_put_sync(&pdev->dev);
389e9a164e3SChristophe JAILLET 	return 0;
390e9a164e3SChristophe JAILLET 
391e9a164e3SChristophe JAILLET err_clk_register:
392e9a164e3SChristophe JAILLET 	pm_runtime_put_sync(&pdev->dev);
393e9a164e3SChristophe JAILLET 	pm_runtime_disable(&pdev->dev);
394e9a164e3SChristophe JAILLET 	clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm);
395d3a0946dSShengjiu Wang 
396d3a0946dSShengjiu Wang 	return ret;
397d3a0946dSShengjiu Wang }
398d3a0946dSShengjiu Wang 
399d3a0946dSShengjiu Wang static int imx8_acm_clk_remove(struct platform_device *pdev)
400d3a0946dSShengjiu Wang {
401d3a0946dSShengjiu Wang 	struct imx8_acm_priv *priv = dev_get_drvdata(&pdev->dev);
402d3a0946dSShengjiu Wang 
403d3a0946dSShengjiu Wang 	pm_runtime_disable(&pdev->dev);
404d3a0946dSShengjiu Wang 
405d3a0946dSShengjiu Wang 	clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm);
406d3a0946dSShengjiu Wang 
407d3a0946dSShengjiu Wang 	return 0;
408d3a0946dSShengjiu Wang }
409d3a0946dSShengjiu Wang 
410d3a0946dSShengjiu Wang static const struct imx8_acm_soc_data imx8qm_acm_data = {
411d3a0946dSShengjiu Wang 	.sels = imx8qm_sels,
412d3a0946dSShengjiu Wang 	.num_sels = ARRAY_SIZE(imx8qm_sels),
413d3a0946dSShengjiu Wang };
414d3a0946dSShengjiu Wang 
415d3a0946dSShengjiu Wang static const struct imx8_acm_soc_data imx8qxp_acm_data = {
416d3a0946dSShengjiu Wang 	.sels = imx8qxp_sels,
417d3a0946dSShengjiu Wang 	.num_sels = ARRAY_SIZE(imx8qxp_sels),
418d3a0946dSShengjiu Wang };
419d3a0946dSShengjiu Wang 
420d3a0946dSShengjiu Wang static const struct imx8_acm_soc_data imx8dxl_acm_data = {
421d3a0946dSShengjiu Wang 	.sels = imx8dxl_sels,
422d3a0946dSShengjiu Wang 	.num_sels = ARRAY_SIZE(imx8dxl_sels),
423d3a0946dSShengjiu Wang };
424d3a0946dSShengjiu Wang 
425d3a0946dSShengjiu Wang static const struct of_device_id imx8_acm_match[] = {
426d3a0946dSShengjiu Wang 	{ .compatible = "fsl,imx8qm-acm", .data = &imx8qm_acm_data },
427d3a0946dSShengjiu Wang 	{ .compatible = "fsl,imx8qxp-acm", .data = &imx8qxp_acm_data },
428d3a0946dSShengjiu Wang 	{ .compatible = "fsl,imx8dxl-acm", .data = &imx8dxl_acm_data },
429d3a0946dSShengjiu Wang 	{ /* sentinel */ }
430d3a0946dSShengjiu Wang };
431d3a0946dSShengjiu Wang MODULE_DEVICE_TABLE(of, imx8_acm_match);
432d3a0946dSShengjiu Wang 
433d3a0946dSShengjiu Wang static int __maybe_unused imx8_acm_runtime_suspend(struct device *dev)
434d3a0946dSShengjiu Wang {
435d3a0946dSShengjiu Wang 	struct imx8_acm_priv *priv = dev_get_drvdata(dev);
436d3a0946dSShengjiu Wang 	struct clk_imx8_acm_sel *sels;
437d3a0946dSShengjiu Wang 	int i;
438d3a0946dSShengjiu Wang 
439d3a0946dSShengjiu Wang 	sels = priv->soc_data->sels;
440d3a0946dSShengjiu Wang 
441d3a0946dSShengjiu Wang 	for (i = 0; i < priv->soc_data->num_sels; i++)
442d3a0946dSShengjiu Wang 		priv->regs[i] = readl_relaxed(priv->reg + sels[i].reg);
443d3a0946dSShengjiu Wang 
444d3a0946dSShengjiu Wang 	return 0;
445d3a0946dSShengjiu Wang }
446d3a0946dSShengjiu Wang 
447d3a0946dSShengjiu Wang static int __maybe_unused imx8_acm_runtime_resume(struct device *dev)
448d3a0946dSShengjiu Wang {
449d3a0946dSShengjiu Wang 	struct imx8_acm_priv *priv = dev_get_drvdata(dev);
450d3a0946dSShengjiu Wang 	struct clk_imx8_acm_sel *sels;
451d3a0946dSShengjiu Wang 	int i;
452d3a0946dSShengjiu Wang 
453d3a0946dSShengjiu Wang 	sels = priv->soc_data->sels;
454d3a0946dSShengjiu Wang 
455d3a0946dSShengjiu Wang 	for (i = 0; i < priv->soc_data->num_sels; i++)
456d3a0946dSShengjiu Wang 		writel_relaxed(priv->regs[i], priv->reg + sels[i].reg);
457d3a0946dSShengjiu Wang 
458d3a0946dSShengjiu Wang 	return 0;
459d3a0946dSShengjiu Wang }
460d3a0946dSShengjiu Wang 
461d3a0946dSShengjiu Wang static const struct dev_pm_ops imx8_acm_pm_ops = {
462d3a0946dSShengjiu Wang 	SET_RUNTIME_PM_OPS(imx8_acm_runtime_suspend,
463d3a0946dSShengjiu Wang 			   imx8_acm_runtime_resume, NULL)
464d3a0946dSShengjiu Wang 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
465d3a0946dSShengjiu Wang 				      pm_runtime_force_resume)
466d3a0946dSShengjiu Wang };
467d3a0946dSShengjiu Wang 
468d3a0946dSShengjiu Wang static struct platform_driver imx8_acm_clk_driver = {
469d3a0946dSShengjiu Wang 	.driver = {
470d3a0946dSShengjiu Wang 		.name = "imx8-acm",
471d3a0946dSShengjiu Wang 		.of_match_table = imx8_acm_match,
472d3a0946dSShengjiu Wang 		.pm = &imx8_acm_pm_ops,
473d3a0946dSShengjiu Wang 	},
474d3a0946dSShengjiu Wang 	.probe = imx8_acm_clk_probe,
475d3a0946dSShengjiu Wang 	.remove = imx8_acm_clk_remove,
476d3a0946dSShengjiu Wang };
477d3a0946dSShengjiu Wang module_platform_driver(imx8_acm_clk_driver);
478d3a0946dSShengjiu Wang 
479d3a0946dSShengjiu Wang MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>");
480d3a0946dSShengjiu Wang MODULE_DESCRIPTION("Freescale i.MX8 Audio Clock Mux driver");
481d3a0946dSShengjiu Wang MODULE_LICENSE("GPL");
482