1b1260067SA.s. Dong // SPDX-License-Identifier: GPL-2.0+ 2b1260067SA.s. Dong /* 3b1260067SA.s. Dong * Copyright (C) 2016 Freescale Semiconductor, Inc. 4b1260067SA.s. Dong * Copyright 2017~2018 NXP 5b1260067SA.s. Dong * 6b1260067SA.s. Dong * Author: Dong Aisheng <aisheng.dong@nxp.com> 7b1260067SA.s. Dong * 8b1260067SA.s. Dong */ 9b1260067SA.s. Dong 10b1260067SA.s. Dong #include <dt-bindings/clock/imx7ulp-clock.h> 11836b2513SAnson Huang #include <linux/clk-provider.h> 12b1260067SA.s. Dong #include <linux/err.h> 13b1260067SA.s. Dong #include <linux/init.h> 14b1260067SA.s. Dong #include <linux/io.h> 15b1260067SA.s. Dong #include <linux/of.h> 16b1260067SA.s. Dong #include <linux/of_address.h> 17b1260067SA.s. Dong #include <linux/platform_device.h> 18b1260067SA.s. Dong #include <linux/slab.h> 19b1260067SA.s. Dong 20b1260067SA.s. Dong #include "clk.h" 21b1260067SA.s. Dong 22b1260067SA.s. Dong static const char * const pll_pre_sels[] = { "sosc", "firc", }; 23b1260067SA.s. Dong static const char * const spll_pfd_sels[] = { "spll_pfd0", "spll_pfd1", "spll_pfd2", "spll_pfd3", }; 24b1260067SA.s. Dong static const char * const spll_sels[] = { "spll", "spll_pfd_sel", }; 25b1260067SA.s. Dong static const char * const apll_pfd_sels[] = { "apll_pfd0", "apll_pfd1", "apll_pfd2", "apll_pfd3", }; 26b1260067SA.s. Dong static const char * const apll_sels[] = { "apll", "apll_pfd_sel", }; 2796ac93a7SAnson Huang static const char * const scs_sels[] = { "dummy", "sosc", "sirc", "firc", "dummy", "apll_sel", "spll_sel", "dummy", }; 282e2b928aSAnson Huang static const char * const ddr_sels[] = { "apll_pfd_sel", "dummy", "dummy", "dummy", }; 29b1260067SA.s. Dong static const char * const nic_sels[] = { "firc", "ddr_clk", }; 30b1260067SA.s. Dong static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", }; 3172b2429dSFancy Fang static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", }; 32260dab44SPeng Fan static const char * const arm_sels[] = { "core", "dummy", "dummy", "hsrun_core", }; 33b1260067SA.s. Dong 34b1260067SA.s. Dong /* used by sosc/sirc/firc/ddr/spll/apll dividers */ 35b1260067SA.s. Dong static const struct clk_div_table ulp_div_table[] = { 36b1260067SA.s. Dong { .val = 1, .div = 1, }, 37b1260067SA.s. Dong { .val = 2, .div = 2, }, 38b1260067SA.s. Dong { .val = 3, .div = 4, }, 39b1260067SA.s. Dong { .val = 4, .div = 8, }, 40b1260067SA.s. Dong { .val = 5, .div = 16, }, 41b1260067SA.s. Dong { .val = 6, .div = 32, }, 42b1260067SA.s. Dong { .val = 7, .div = 64, }, 43ed11e317SPeng Fan { /* sentinel */ }, 44b1260067SA.s. Dong }; 45b1260067SA.s. Dong 46b1260067SA.s. Dong static void __init imx7ulp_clk_scg1_init(struct device_node *np) 47b1260067SA.s. Dong { 48b1260067SA.s. Dong struct clk_hw_onecell_data *clk_data; 49955a67f7SAbel Vesa struct clk_hw **hws; 50b1260067SA.s. Dong void __iomem *base; 51b1260067SA.s. Dong 52921e88a4SGustavo A. R. Silva clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SCG1_END), 53921e88a4SGustavo A. R. Silva GFP_KERNEL); 54b1260067SA.s. Dong if (!clk_data) 55b1260067SA.s. Dong return; 56b1260067SA.s. Dong 57b1260067SA.s. Dong clk_data->num = IMX7ULP_CLK_SCG1_END; 58955a67f7SAbel Vesa hws = clk_data->hws; 59b1260067SA.s. Dong 60955a67f7SAbel Vesa hws[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); 61b1260067SA.s. Dong 62955a67f7SAbel Vesa hws[IMX7ULP_CLK_ROSC] = imx_obtain_fixed_clk_hw(np, "rosc"); 63955a67f7SAbel Vesa hws[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc"); 64955a67f7SAbel Vesa hws[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc"); 65955a67f7SAbel Vesa hws[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc"); 66955a67f7SAbel Vesa hws[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll"); 67b1260067SA.s. Dong 68b1260067SA.s. Dong /* SCG1 */ 69b1260067SA.s. Dong base = of_iomap(np, 0); 70b1260067SA.s. Dong WARN_ON(!base); 71b1260067SA.s. Dong 72b1260067SA.s. Dong /* NOTE: xPLL config can't be changed when xPLL is enabled */ 73955a67f7SAbel Vesa hws[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); 74955a67f7SAbel Vesa hws[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); 75b1260067SA.s. Dong 76b1260067SA.s. Dong /* name parent_name reg shift width flags */ 77955a67f7SAbel Vesa hws[IMX7ULP_CLK_APLL_PRE_DIV] = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0x508, 8, 3, CLK_SET_RATE_GATE); 78955a67f7SAbel Vesa hws[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608, 8, 3, CLK_SET_RATE_GATE); 79b1260067SA.s. Dong 80b1260067SA.s. Dong /* name parent_name base */ 815f0601c4SJacky Bai hws[IMX7ULP_CLK_APLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "apll", "apll_pre_div", base + 0x500); 825f0601c4SJacky Bai hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "spll", "spll_pre_div", base + 0x600); 83b1260067SA.s. Dong 84b1260067SA.s. Dong /* APLL PFDs */ 85*9179d239SJacky Bai hws[IMX7ULP_CLK_APLL_PFD0] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd0", "apll", base + 0x50c, 0); 86*9179d239SJacky Bai hws[IMX7ULP_CLK_APLL_PFD1] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd1", "apll", base + 0x50c, 1); 87*9179d239SJacky Bai hws[IMX7ULP_CLK_APLL_PFD2] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd2", "apll", base + 0x50c, 2); 88*9179d239SJacky Bai hws[IMX7ULP_CLK_APLL_PFD3] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd3", "apll", base + 0x50c, 3); 89b1260067SA.s. Dong 90b1260067SA.s. Dong /* SPLL PFDs */ 91*9179d239SJacky Bai hws[IMX7ULP_CLK_SPLL_PFD0] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd0", "spll", base + 0x60C, 0); 92*9179d239SJacky Bai hws[IMX7ULP_CLK_SPLL_PFD1] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd1", "spll", base + 0x60C, 1); 93*9179d239SJacky Bai hws[IMX7ULP_CLK_SPLL_PFD2] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd2", "spll", base + 0x60C, 2); 94*9179d239SJacky Bai hws[IMX7ULP_CLK_SPLL_PFD3] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd3", "spll", base + 0x60C, 3); 95b1260067SA.s. Dong 96b1260067SA.s. Dong /* PLL Mux */ 97955a67f7SAbel Vesa hws[IMX7ULP_CLK_APLL_PFD_SEL] = imx_clk_hw_mux_flags("apll_pfd_sel", base + 0x508, 14, 2, apll_pfd_sels, ARRAY_SIZE(apll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); 98955a67f7SAbel Vesa hws[IMX7ULP_CLK_SPLL_PFD_SEL] = imx_clk_hw_mux_flags("spll_pfd_sel", base + 0x608, 14, 2, spll_pfd_sels, ARRAY_SIZE(spll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); 99955a67f7SAbel Vesa hws[IMX7ULP_CLK_APLL_SEL] = imx_clk_hw_mux_flags("apll_sel", base + 0x508, 1, 1, apll_sels, ARRAY_SIZE(apll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); 100955a67f7SAbel Vesa hws[IMX7ULP_CLK_SPLL_SEL] = imx_clk_hw_mux_flags("spll_sel", base + 0x608, 1, 1, spll_sels, ARRAY_SIZE(spll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); 101b1260067SA.s. Dong 102955a67f7SAbel Vesa hws[IMX7ULP_CLK_SPLL_BUS_CLK] = imx_clk_hw_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, 0, ulp_div_table, &imx_ccm_lock); 103b1260067SA.s. Dong 104b1260067SA.s. Dong /* scs/ddr/nic select different clock source requires that clock to be enabled first */ 105955a67f7SAbel Vesa hws[IMX7ULP_CLK_SYS_SEL] = imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(scs_sels)); 106955a67f7SAbel Vesa hws[IMX7ULP_CLK_HSRUN_SYS_SEL] = imx_clk_hw_mux2("hsrun_scs_sel", base + 0x1c, 24, 4, scs_sels, ARRAY_SIZE(scs_sels)); 107955a67f7SAbel Vesa hws[IMX7ULP_CLK_NIC_SEL] = imx_clk_hw_mux2("nic_sel", base + 0x40, 28, 1, nic_sels, ARRAY_SIZE(nic_sels)); 108955a67f7SAbel Vesa hws[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 2, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); 109b1260067SA.s. Dong 110955a67f7SAbel Vesa hws[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT); 111260dab44SPeng Fan hws[IMX7ULP_CLK_CORE] = imx_clk_hw_cpu("core", "divcore", hws[IMX7ULP_CLK_CORE_DIV]->clk, hws[IMX7ULP_CLK_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk, hws[IMX7ULP_CLK_FIRC]->clk); 112955a67f7SAbel Vesa hws[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT); 113260dab44SPeng Fan hws[IMX7ULP_CLK_HSRUN_CORE] = imx_clk_hw_cpu("hsrun_core", "hsrun_divcore", hws[IMX7ULP_CLK_HSRUN_CORE_DIV]->clk, hws[IMX7ULP_CLK_HSRUN_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk, hws[IMX7ULP_CLK_FIRC]->clk); 114b1260067SA.s. Dong 115955a67f7SAbel Vesa hws[IMX7ULP_CLK_DDR_DIV] = imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3, 116b1260067SA.s. Dong 0, ulp_div_table, &imx_ccm_lock); 117b1260067SA.s. Dong 118955a67f7SAbel Vesa hws[IMX7ULP_CLK_NIC0_DIV] = imx_clk_hw_divider_flags("nic0_clk", "nic_sel", base + 0x40, 24, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 119955a67f7SAbel Vesa hws[IMX7ULP_CLK_NIC1_DIV] = imx_clk_hw_divider_flags("nic1_clk", "nic0_clk", base + 0x40, 16, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 120955a67f7SAbel Vesa hws[IMX7ULP_CLK_NIC1_BUS_DIV] = imx_clk_hw_divider_flags("nic1_bus_clk", "nic0_clk", base + 0x40, 4, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 121b1260067SA.s. Dong 122955a67f7SAbel Vesa hws[IMX7ULP_CLK_GPU_DIV] = imx_clk_hw_divider("gpu_clk", "nic0_clk", base + 0x40, 20, 4); 123b1260067SA.s. Dong 124955a67f7SAbel Vesa hws[IMX7ULP_CLK_SOSC_BUS_CLK] = imx_clk_hw_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8, 3, 125b1260067SA.s. Dong CLK_DIVIDER_READ_ONLY, ulp_div_table, &imx_ccm_lock); 126955a67f7SAbel Vesa hws[IMX7ULP_CLK_FIRC_BUS_CLK] = imx_clk_hw_divider_gate("firc_bus_clk", "firc", 0, base + 0x304, 8, 3, 127b1260067SA.s. Dong CLK_DIVIDER_READ_ONLY, ulp_div_table, &imx_ccm_lock); 128b1260067SA.s. Dong 129955a67f7SAbel Vesa imx_check_clk_hws(hws, clk_data->num); 130b1260067SA.s. Dong 131b1260067SA.s. Dong of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 132b1260067SA.s. Dong } 133b1260067SA.s. Dong CLK_OF_DECLARE(imx7ulp_clk_scg1, "fsl,imx7ulp-scg1", imx7ulp_clk_scg1_init); 134b1260067SA.s. Dong 135b1260067SA.s. Dong static void __init imx7ulp_clk_pcc2_init(struct device_node *np) 136b1260067SA.s. Dong { 137b1260067SA.s. Dong struct clk_hw_onecell_data *clk_data; 138955a67f7SAbel Vesa struct clk_hw **hws; 139b1260067SA.s. Dong void __iomem *base; 140b1260067SA.s. Dong 141921e88a4SGustavo A. R. Silva clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END), 142921e88a4SGustavo A. R. Silva GFP_KERNEL); 143b1260067SA.s. Dong if (!clk_data) 144b1260067SA.s. Dong return; 145b1260067SA.s. Dong 146b1260067SA.s. Dong clk_data->num = IMX7ULP_CLK_PCC2_END; 147955a67f7SAbel Vesa hws = clk_data->hws; 148b1260067SA.s. Dong 149b1260067SA.s. Dong /* PCC2 */ 150b1260067SA.s. Dong base = of_iomap(np, 0); 151b1260067SA.s. Dong WARN_ON(!base); 152b1260067SA.s. Dong 153955a67f7SAbel Vesa hws[IMX7ULP_CLK_DMA1] = imx_clk_hw_gate("dma1", "nic1_clk", base + 0x20, 30); 154955a67f7SAbel Vesa hws[IMX7ULP_CLK_RGPIO2P1] = imx_clk_hw_gate("rgpio2p1", "nic1_bus_clk", base + 0x3c, 30); 155955a67f7SAbel Vesa hws[IMX7ULP_CLK_DMA_MUX1] = imx_clk_hw_gate("dma_mux1", "nic1_bus_clk", base + 0x84, 30); 156955a67f7SAbel Vesa hws[IMX7ULP_CLK_CAAM] = imx_clk_hw_gate("caam", "nic1_clk", base + 0x90, 30); 157955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPTPM4] = imx7ulp_clk_hw_composite("lptpm4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94); 158955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPTPM5] = imx7ulp_clk_hw_composite("lptpm5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98); 159955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPIT1] = imx7ulp_clk_hw_composite("lpit1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c); 160955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPSPI2] = imx7ulp_clk_hw_composite("lpspi2", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa4); 161955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPSPI3] = imx7ulp_clk_hw_composite("lpspi3", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa8); 162955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPI2C4] = imx7ulp_clk_hw_composite("lpi2c4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xac); 163955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPI2C5] = imx7ulp_clk_hw_composite("lpi2c5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb0); 164955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPUART4] = imx7ulp_clk_hw_composite("lpuart4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb4); 165955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPUART5] = imx7ulp_clk_hw_composite("lpuart5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb8); 166955a67f7SAbel Vesa hws[IMX7ULP_CLK_FLEXIO1] = imx7ulp_clk_hw_composite("flexio1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xc4); 167955a67f7SAbel Vesa hws[IMX7ULP_CLK_USB0] = imx7ulp_clk_hw_composite("usb0", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xcc); 168955a67f7SAbel Vesa hws[IMX7ULP_CLK_USB1] = imx7ulp_clk_hw_composite("usb1", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xd0); 169955a67f7SAbel Vesa hws[IMX7ULP_CLK_USB_PHY] = imx_clk_hw_gate("usb_phy", "nic1_bus_clk", base + 0xd4, 30); 170955a67f7SAbel Vesa hws[IMX7ULP_CLK_USDHC0] = imx7ulp_clk_hw_composite("usdhc0", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xdc); 171955a67f7SAbel Vesa hws[IMX7ULP_CLK_USDHC1] = imx7ulp_clk_hw_composite("usdhc1", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xe0); 172955a67f7SAbel Vesa hws[IMX7ULP_CLK_WDG1] = imx7ulp_clk_hw_composite("wdg1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0xf4); 173955a67f7SAbel Vesa hws[IMX7ULP_CLK_WDG2] = imx7ulp_clk_hw_composite("wdg2", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0x10c); 174b1260067SA.s. Dong 175955a67f7SAbel Vesa imx_check_clk_hws(hws, clk_data->num); 176b1260067SA.s. Dong 177b1260067SA.s. Dong of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 178b8734099SAnson Huang 179379c9a24SAdam Ford imx_register_uart_clocks(2); 180b1260067SA.s. Dong } 181b1260067SA.s. Dong CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init); 182b1260067SA.s. Dong 183b1260067SA.s. Dong static void __init imx7ulp_clk_pcc3_init(struct device_node *np) 184b1260067SA.s. Dong { 185b1260067SA.s. Dong struct clk_hw_onecell_data *clk_data; 186955a67f7SAbel Vesa struct clk_hw **hws; 187b1260067SA.s. Dong void __iomem *base; 188b1260067SA.s. Dong 189921e88a4SGustavo A. R. Silva clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END), 190921e88a4SGustavo A. R. Silva GFP_KERNEL); 191b1260067SA.s. Dong if (!clk_data) 192b1260067SA.s. Dong return; 193b1260067SA.s. Dong 194b1260067SA.s. Dong clk_data->num = IMX7ULP_CLK_PCC3_END; 195955a67f7SAbel Vesa hws = clk_data->hws; 196b1260067SA.s. Dong 197b1260067SA.s. Dong /* PCC3 */ 198b1260067SA.s. Dong base = of_iomap(np, 0); 199b1260067SA.s. Dong WARN_ON(!base); 200b1260067SA.s. Dong 201955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPTPM6] = imx7ulp_clk_hw_composite("lptpm6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x84); 202955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPTPM7] = imx7ulp_clk_hw_composite("lptpm7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x88); 203b1260067SA.s. Dong 204955a67f7SAbel Vesa hws[IMX7ULP_CLK_MMDC] = clk_hw_register_gate(NULL, "mmdc", "nic1_clk", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 205b1260067SA.s. Dong base + 0xac, 30, 0, &imx_ccm_lock); 206955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPI2C6] = imx7ulp_clk_hw_composite("lpi2c6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x90); 207955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPI2C7] = imx7ulp_clk_hw_composite("lpi2c7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94); 208955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPUART6] = imx7ulp_clk_hw_composite("lpuart6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98); 209955a67f7SAbel Vesa hws[IMX7ULP_CLK_LPUART7] = imx7ulp_clk_hw_composite("lpuart7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c); 210955a67f7SAbel Vesa hws[IMX7ULP_CLK_DSI] = imx7ulp_clk_hw_composite("dsi", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0xa4); 211955a67f7SAbel Vesa hws[IMX7ULP_CLK_LCDIF] = imx7ulp_clk_hw_composite("lcdif", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xa8); 212b1260067SA.s. Dong 213955a67f7SAbel Vesa hws[IMX7ULP_CLK_VIU] = imx_clk_hw_gate("viu", "nic1_clk", base + 0xa0, 30); 214955a67f7SAbel Vesa hws[IMX7ULP_CLK_PCTLC] = imx_clk_hw_gate("pctlc", "nic1_bus_clk", base + 0xb8, 30); 215955a67f7SAbel Vesa hws[IMX7ULP_CLK_PCTLD] = imx_clk_hw_gate("pctld", "nic1_bus_clk", base + 0xbc, 30); 216955a67f7SAbel Vesa hws[IMX7ULP_CLK_PCTLE] = imx_clk_hw_gate("pctle", "nic1_bus_clk", base + 0xc0, 30); 217955a67f7SAbel Vesa hws[IMX7ULP_CLK_PCTLF] = imx_clk_hw_gate("pctlf", "nic1_bus_clk", base + 0xc4, 30); 218b1260067SA.s. Dong 219955a67f7SAbel Vesa hws[IMX7ULP_CLK_GPU3D] = imx7ulp_clk_hw_composite("gpu3d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140); 220955a67f7SAbel Vesa hws[IMX7ULP_CLK_GPU2D] = imx7ulp_clk_hw_composite("gpu2d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144); 221b1260067SA.s. Dong 222955a67f7SAbel Vesa imx_check_clk_hws(hws, clk_data->num); 223b1260067SA.s. Dong 224b1260067SA.s. Dong of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 225b8734099SAnson Huang 226379c9a24SAdam Ford imx_register_uart_clocks(7); 227b1260067SA.s. Dong } 228b1260067SA.s. Dong CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init); 2297128d7f7SAnson Huang 2307128d7f7SAnson Huang static void __init imx7ulp_clk_smc1_init(struct device_node *np) 2317128d7f7SAnson Huang { 2327128d7f7SAnson Huang struct clk_hw_onecell_data *clk_data; 233955a67f7SAbel Vesa struct clk_hw **hws; 2347128d7f7SAnson Huang void __iomem *base; 2357128d7f7SAnson Huang 236921e88a4SGustavo A. R. Silva clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SMC1_END), 237921e88a4SGustavo A. R. Silva GFP_KERNEL); 2387128d7f7SAnson Huang if (!clk_data) 2397128d7f7SAnson Huang return; 2407128d7f7SAnson Huang 2417128d7f7SAnson Huang clk_data->num = IMX7ULP_CLK_SMC1_END; 242955a67f7SAbel Vesa hws = clk_data->hws; 2437128d7f7SAnson Huang 2447128d7f7SAnson Huang /* SMC1 */ 2457128d7f7SAnson Huang base = of_iomap(np, 0); 2467128d7f7SAnson Huang WARN_ON(!base); 2477128d7f7SAnson Huang 248260dab44SPeng Fan hws[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_sels), CLK_SET_RATE_PARENT); 2497128d7f7SAnson Huang 250955a67f7SAbel Vesa imx_check_clk_hws(hws, clk_data->num); 2517128d7f7SAnson Huang 2527128d7f7SAnson Huang of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 2537128d7f7SAnson Huang } 2547128d7f7SAnson Huang CLK_OF_DECLARE(imx7ulp_clk_smc1, "fsl,imx7ulp-smc1", imx7ulp_clk_smc1_init); 255