1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2011-2013 Freescale Semiconductor, Inc. 4 * Copyright 2011 Linaro Ltd. 5 */ 6 7 #include <linux/init.h> 8 #include <linux/types.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/clkdev.h> 12 #include <linux/clk-provider.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 #include <soc/imx/revision.h> 20 #include <dt-bindings/clock/imx6qdl-clock.h> 21 22 #include "clk.h" 23 24 static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; 25 static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; 26 static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; 27 static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; 28 static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; 29 static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; 30 static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; 31 static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; 32 static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; 33 static const char *gpu_axi_sels[] = { "axi", "ahb", }; 34 static const char *pre_axi_sels[] = { "axi", "ahb", }; 35 static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; 36 static const char *gpu2d_core_sels_2[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m",}; 37 static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; 38 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; 39 static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; 40 static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; 41 static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; 42 static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 43 static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 44 static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 45 static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 46 static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; 47 static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; 48 static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; 49 static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; 50 static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; 51 static const char *pcie_axi_sels[] = { "axi", "ahb", }; 52 static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; 53 static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; 54 static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; 55 static const char *enfc_sels_2[] = {"pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", }; 56 static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; 57 static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 58 static const char *vdo_axi_sels[] = { "axi", "ahb", }; 59 static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 60 static const char *uart_sels[] = { "pll3_80m", "osc", }; 61 static const char *ipg_per_sels[] = { "ipg", "osc", }; 62 static const char *ecspi_sels[] = { "pll3_60m", "osc", }; 63 static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", }; 64 static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", 65 "video_27m", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", 66 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", }; 67 static const char *cko2_sels[] = { 68 "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", 69 "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", 70 "usdhc3", "dummy", "arm", "ipu1", 71 "ipu2", "vdo_axi", "osc", "gpu2d_core", 72 "gpu3d_core", "usdhc2", "ssi1", "ssi2", 73 "ssi3", "gpu3d_shader", "vpu_axi", "can_root", 74 "ldb_di0", "ldb_di1", "esai_extal", "eim_slow", 75 "uart_serial", "spdif", "asrc", "hsi_tx", 76 }; 77 static const char *cko_sels[] = { "cko1", "cko2", }; 78 static const char *lvds_sels[] = { 79 "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", 80 "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", 81 "pcie_ref_125m", "sata_ref_100m", "usbphy1", "usbphy2", 82 "dummy", "dummy", "dummy", "dummy", "osc", 83 }; 84 static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", }; 85 static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; 86 static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", }; 87 static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; 88 static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", }; 89 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", }; 90 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", }; 91 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; 92 93 static struct clk_hw **hws; 94 static struct clk_hw_onecell_data *clk_hw_data; 95 96 static struct clk_div_table clk_enet_ref_table[] = { 97 { .val = 0, .div = 20, }, 98 { .val = 1, .div = 10, }, 99 { .val = 2, .div = 5, }, 100 { .val = 3, .div = 4, }, 101 { /* sentinel */ } 102 }; 103 104 static struct clk_div_table post_div_table[] = { 105 { .val = 2, .div = 1, }, 106 { .val = 1, .div = 2, }, 107 { .val = 0, .div = 4, }, 108 { /* sentinel */ } 109 }; 110 111 static struct clk_div_table video_div_table[] = { 112 { .val = 0, .div = 1, }, 113 { .val = 1, .div = 2, }, 114 { .val = 2, .div = 1, }, 115 { .val = 3, .div = 4, }, 116 { /* sentinel */ } 117 }; 118 119 static const char * enet_ref_sels[] = { "enet_ref", "enet_ref_pad", }; 120 static const u32 enet_ref_sels_table[] = { IMX6Q_GPR1_ENET_CLK_SEL_ANATOP, IMX6Q_GPR1_ENET_CLK_SEL_PAD }; 121 static const u32 enet_ref_sels_table_mask = IMX6Q_GPR1_ENET_CLK_SEL_ANATOP; 122 123 static unsigned int share_count_esai; 124 static unsigned int share_count_asrc; 125 static unsigned int share_count_ssi1; 126 static unsigned int share_count_ssi2; 127 static unsigned int share_count_ssi3; 128 static unsigned int share_count_mipi_core_cfg; 129 static unsigned int share_count_spdif; 130 static unsigned int share_count_prg0; 131 static unsigned int share_count_prg1; 132 133 static inline int clk_on_imx6q(void) 134 { 135 return of_machine_is_compatible("fsl,imx6q"); 136 } 137 138 static inline int clk_on_imx6qp(void) 139 { 140 return of_machine_is_compatible("fsl,imx6qp"); 141 } 142 143 static inline int clk_on_imx6dl(void) 144 { 145 return of_machine_is_compatible("fsl,imx6dl"); 146 } 147 148 static int ldb_di_sel_by_clock_id(int clock_id) 149 { 150 switch (clock_id) { 151 case IMX6QDL_CLK_PLL5_VIDEO_DIV: 152 if (clk_on_imx6q() && 153 imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) 154 return -ENOENT; 155 return 0; 156 case IMX6QDL_CLK_PLL2_PFD0_352M: 157 return 1; 158 case IMX6QDL_CLK_PLL2_PFD2_396M: 159 return 2; 160 case IMX6QDL_CLK_MMDC_CH1_AXI: 161 return 3; 162 case IMX6QDL_CLK_PLL3_USB_OTG: 163 return 4; 164 default: 165 return -ENOENT; 166 } 167 } 168 169 static void of_assigned_ldb_sels(struct device_node *node, 170 unsigned int *ldb_di0_sel, 171 unsigned int *ldb_di1_sel) 172 { 173 struct of_phandle_args clkspec; 174 int index, rc, num_parents; 175 int parent, child, sel; 176 177 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", 178 "#clock-cells"); 179 for (index = 0; index < num_parents; index++) { 180 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", 181 "#clock-cells", index, &clkspec); 182 if (rc < 0) { 183 /* skip empty (null) phandles */ 184 if (rc == -ENOENT) 185 continue; 186 else 187 return; 188 } 189 if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { 190 pr_err("ccm: parent clock %d not in ccm\n", index); 191 of_node_put(clkspec.np); 192 return; 193 } 194 parent = clkspec.args[0]; 195 of_node_put(clkspec.np); 196 197 rc = of_parse_phandle_with_args(node, "assigned-clocks", 198 "#clock-cells", index, &clkspec); 199 if (rc < 0) 200 return; 201 if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { 202 pr_err("ccm: child clock %d not in ccm\n", index); 203 of_node_put(clkspec.np); 204 return; 205 } 206 child = clkspec.args[0]; 207 of_node_put(clkspec.np); 208 209 if (child != IMX6QDL_CLK_LDB_DI0_SEL && 210 child != IMX6QDL_CLK_LDB_DI1_SEL) 211 continue; 212 213 sel = ldb_di_sel_by_clock_id(parent); 214 if (sel < 0) { 215 pr_err("ccm: invalid ldb_di%d parent clock: %d\n", 216 child == IMX6QDL_CLK_LDB_DI1_SEL, parent); 217 continue; 218 } 219 220 if (child == IMX6QDL_CLK_LDB_DI0_SEL) 221 *ldb_di0_sel = sel; 222 if (child == IMX6QDL_CLK_LDB_DI1_SEL) 223 *ldb_di1_sel = sel; 224 } 225 } 226 227 static bool pll6_bypassed(struct device_node *node) 228 { 229 int index, ret, num_clocks; 230 struct of_phandle_args clkspec; 231 232 num_clocks = of_count_phandle_with_args(node, "assigned-clocks", 233 "#clock-cells"); 234 if (num_clocks < 0) 235 return false; 236 237 for (index = 0; index < num_clocks; index++) { 238 ret = of_parse_phandle_with_args(node, "assigned-clocks", 239 "#clock-cells", index, 240 &clkspec); 241 if (ret < 0) 242 return false; 243 244 if (clkspec.np == node && 245 clkspec.args[0] == IMX6QDL_PLL6_BYPASS) { 246 of_node_put(clkspec.np); 247 break; 248 } 249 of_node_put(clkspec.np); 250 } 251 252 /* PLL6 bypass is not part of the assigned clock list */ 253 if (index == num_clocks) 254 return false; 255 256 ret = of_parse_phandle_with_args(node, "assigned-clock-parents", 257 "#clock-cells", index, &clkspec); 258 259 if (!ret) 260 of_node_put(clkspec.np); 261 262 if (clkspec.args[0] != IMX6QDL_CLK_PLL6) 263 return true; 264 265 return false; 266 } 267 268 #define CCM_CCSR 0x0c 269 #define CCM_CS2CDR 0x2c 270 271 #define CCSR_PLL3_SW_CLK_SEL BIT(0) 272 273 #define CS2CDR_LDB_DI0_CLK_SEL_SHIFT 9 274 #define CS2CDR_LDB_DI1_CLK_SEL_SHIFT 12 275 276 /* 277 * The only way to disable the MMDC_CH1 clock is to move it to pll3_sw_clk 278 * via periph2_clk2_sel and then to disable pll3_sw_clk by selecting the 279 * bypass clock source, since there is no CG bit for mmdc_ch1. 280 */ 281 static void mmdc_ch1_disable(void __iomem *ccm_base) 282 { 283 unsigned int reg; 284 285 clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk, 286 hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); 287 288 /* Disable pll3_sw_clk by selecting the bypass clock source */ 289 reg = readl_relaxed(ccm_base + CCM_CCSR); 290 reg |= CCSR_PLL3_SW_CLK_SEL; 291 writel_relaxed(reg, ccm_base + CCM_CCSR); 292 } 293 294 static void mmdc_ch1_reenable(void __iomem *ccm_base) 295 { 296 unsigned int reg; 297 298 /* Enable pll3_sw_clk by disabling the bypass */ 299 reg = readl_relaxed(ccm_base + CCM_CCSR); 300 reg &= ~CCSR_PLL3_SW_CLK_SEL; 301 writel_relaxed(reg, ccm_base + CCM_CCSR); 302 } 303 304 /* 305 * We have to follow a strict procedure when changing the LDB clock source, 306 * otherwise we risk introducing a glitch that can lock up the LDB divider. 307 * Things to keep in mind: 308 * 309 * 1. The current and new parent clock inputs to the mux must be disabled. 310 * 2. The default clock input for ldb_di0/1_clk_sel is mmdc_ch1_axi, which 311 * has no CG bit. 312 * 3. pll2_pfd2_396m can not be gated if it is used as memory clock. 313 * 4. In the RTL implementation of the LDB_DI_CLK_SEL muxes the top four 314 * options are in one mux and the PLL3 option along with three unused 315 * inputs is in a second mux. There is a third mux with two inputs used 316 * to decide between the first and second 4-port mux: 317 * 318 * pll5_video_div 0 --|\ 319 * pll2_pfd0_352m 1 --| |_ 320 * pll2_pfd2_396m 2 --| | `-|\ 321 * mmdc_ch1_axi 3 --|/ | | 322 * | |-- 323 * pll3_usb_otg 4 --|\ | | 324 * 5 --| |_,-|/ 325 * 6 --| | 326 * 7 --|/ 327 * 328 * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time. 329 * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below 330 * switches the parent to the bottom mux first and then manipulates the top 331 * mux to ensure that no glitch will enter the divider. 332 */ 333 static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base) 334 { 335 unsigned int reg; 336 unsigned int sel[2][4]; 337 int i; 338 339 reg = readl_relaxed(ccm_base + CCM_CS2CDR); 340 sel[0][0] = (reg >> CS2CDR_LDB_DI0_CLK_SEL_SHIFT) & 7; 341 sel[1][0] = (reg >> CS2CDR_LDB_DI1_CLK_SEL_SHIFT) & 7; 342 343 sel[0][3] = sel[0][2] = sel[0][1] = sel[0][0]; 344 sel[1][3] = sel[1][2] = sel[1][1] = sel[1][0]; 345 346 of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]); 347 348 for (i = 0; i < 2; i++) { 349 /* Print a notice if a glitch might have been introduced already */ 350 if (sel[i][0] != 3) { 351 pr_notice("ccm: possible glitch: ldb_di%d_sel already changed from reset value: %d\n", 352 i, sel[i][0]); 353 } 354 355 if (sel[i][0] == sel[i][3]) 356 continue; 357 358 /* Only switch to or from pll2_pfd2_396m if it is disabled */ 359 if ((sel[i][0] == 2 || sel[i][3] == 2) && 360 (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == 361 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) { 362 pr_err("ccm: ldb_di%d_sel: couldn't disable pll2_pfd2_396m\n", 363 i); 364 sel[i][3] = sel[i][2] = sel[i][1] = sel[i][0]; 365 continue; 366 } 367 368 /* First switch to the bottom mux */ 369 sel[i][1] = sel[i][0] | 4; 370 371 /* Then configure the top mux before switching back to it */ 372 sel[i][2] = sel[i][3] | 4; 373 374 pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i, 375 sel[i][0], sel[i][1], sel[i][2], sel[i][3]); 376 } 377 378 if (sel[0][0] == sel[0][3] && sel[1][0] == sel[1][3]) 379 return; 380 381 mmdc_ch1_disable(ccm_base); 382 383 for (i = 1; i < 4; i++) { 384 reg = readl_relaxed(ccm_base + CCM_CS2CDR); 385 reg &= ~((7 << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | 386 (7 << CS2CDR_LDB_DI1_CLK_SEL_SHIFT)); 387 reg |= ((sel[0][i] << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | 388 (sel[1][i] << CS2CDR_LDB_DI1_CLK_SEL_SHIFT)); 389 writel_relaxed(reg, ccm_base + CCM_CS2CDR); 390 } 391 392 mmdc_ch1_reenable(ccm_base); 393 } 394 395 #define CCM_ANALOG_PLL_VIDEO 0xa0 396 #define CCM_ANALOG_PFD_480 0xf0 397 #define CCM_ANALOG_PFD_528 0x100 398 399 #define PLL_ENABLE BIT(13) 400 401 #define PFD0_CLKGATE BIT(7) 402 #define PFD1_CLKGATE BIT(15) 403 #define PFD2_CLKGATE BIT(23) 404 #define PFD3_CLKGATE BIT(31) 405 406 static void disable_anatop_clocks(void __iomem *anatop_base) 407 { 408 unsigned int reg; 409 410 /* Make sure PLL2 PFDs 0-2 are gated */ 411 reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528); 412 /* Cannot gate PFD2 if pll2_pfd2_396m is the parent of MMDC clock */ 413 if (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == 414 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk) 415 reg |= PFD0_CLKGATE | PFD1_CLKGATE; 416 else 417 reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE; 418 writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528); 419 420 /* Make sure PLL3 PFDs 0-3 are gated */ 421 reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480); 422 reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE; 423 writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480); 424 425 /* Make sure PLL5 is disabled */ 426 reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO); 427 reg &= ~PLL_ENABLE; 428 writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO); 429 } 430 431 static struct clk_hw * __init imx6q_obtain_fixed_clk_hw(struct device_node *np, 432 const char *name, 433 unsigned long rate) 434 { 435 struct clk *clk = of_clk_get_by_name(np, name); 436 struct clk_hw *hw; 437 438 if (IS_ERR(clk)) 439 hw = imx_obtain_fixed_clock_hw(name, rate); 440 else 441 hw = __clk_get_hw(clk); 442 443 return hw; 444 } 445 446 static void __init imx6q_clocks_init(struct device_node *ccm_node) 447 { 448 struct device_node *np; 449 void __iomem *anatop_base, *base; 450 int ret; 451 452 clk_hw_data = kzalloc_flex(*clk_hw_data, hws, IMX6QDL_CLK_END); 453 if (WARN_ON(!clk_hw_data)) 454 return; 455 456 clk_hw_data->num = IMX6QDL_CLK_END; 457 hws = clk_hw_data->hws; 458 459 hws[IMX6QDL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); 460 461 hws[IMX6QDL_CLK_CKIL] = imx6q_obtain_fixed_clk_hw(ccm_node, "ckil", 0); 462 hws[IMX6QDL_CLK_CKIH] = imx6q_obtain_fixed_clk_hw(ccm_node, "ckih1", 0); 463 hws[IMX6QDL_CLK_OSC] = imx6q_obtain_fixed_clk_hw(ccm_node, "osc", 0); 464 465 /* Clock source from external clock via CLK1/2 PADs */ 466 hws[IMX6QDL_CLK_ANACLK1] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk1", 0); 467 hws[IMX6QDL_CLK_ANACLK2] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk2", 0); 468 469 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); 470 anatop_base = base = of_iomap(np, 0); 471 WARN_ON(!base); 472 of_node_put(np); 473 474 /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ 475 if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { 476 post_div_table[1].div = 1; 477 post_div_table[2].div = 1; 478 video_div_table[1].div = 1; 479 video_div_table[3].div = 1; 480 } 481 482 hws[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 483 hws[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 484 hws[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 485 hws[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 486 hws[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 487 hws[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 488 hws[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 489 490 /* type name parent_name base div_mask */ 491 hws[IMX6QDL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f); 492 hws[IMX6QDL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1); 493 hws[IMX6QDL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3); 494 hws[IMX6QDL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f); 495 hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); 496 hws[IMX6QDL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); 497 hws[IMX6QDL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); 498 499 hws[IMX6QDL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); 500 hws[IMX6QDL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); 501 hws[IMX6QDL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); 502 hws[IMX6QDL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); 503 hws[IMX6QDL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); 504 hws[IMX6QDL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); 505 hws[IMX6QDL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); 506 507 /* Do not bypass PLLs initially */ 508 clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk); 509 clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk); 510 clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk); 511 clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk); 512 clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk); 513 clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk); 514 clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk); 515 516 hws[IMX6QDL_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); 517 hws[IMX6QDL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); 518 hws[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); 519 hws[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); 520 hws[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); 521 hws[IMX6QDL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); 522 hws[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); 523 524 /* 525 * Bit 20 is the reserved and read-only bit, we do this only for: 526 * - Do nothing for usbphy clk_enable/disable 527 * - Keep refcount when do usbphy clk_enable/disable, in that case, 528 * the clk framework may need to enable/disable usbphy's parent 529 */ 530 hws[IMX6QDL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); 531 hws[IMX6QDL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); 532 533 /* 534 * usbphy*_gate needs to be on after system boots up, and software 535 * never needs to control it anymore. 536 */ 537 hws[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6); 538 hws[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6); 539 540 /* 541 * The ENET PLL is special in that is has multiple outputs with 542 * different post-dividers that are all affected by the single bypass 543 * bit, so a single mux bit affects 3 independent branches of the clock 544 * tree. There is no good way to model this in the clock framework and 545 * dynamically changing the bypass bit, will yield unexpected results. 546 * So we treat any configuration that bypasses the ENET PLL as 547 * essentially static with the divider ratios reflecting the bypass 548 * status. 549 * 550 */ 551 if (!pll6_bypassed(ccm_node)) { 552 hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor("sata_ref", "pll6_enet", 1, 5); 553 hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor("pcie_ref", "pll6_enet", 1, 4); 554 hws[IMX6QDL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, 555 base + 0xe0, 0, 2, 0, clk_enet_ref_table, 556 &imx_ccm_lock); 557 } else { 558 hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor("sata_ref", "pll6_enet", 1, 1); 559 hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor("pcie_ref", "pll6_enet", 1, 1); 560 hws[IMX6QDL_CLK_ENET_REF] = imx_clk_hw_fixed_factor("enet_ref", "pll6_enet", 1, 1); 561 } 562 563 hws[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_hw_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); 564 hws[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_hw_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); 565 566 hws[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); 567 hws[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_hw_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); 568 569 /* 570 * lvds1_gate and lvds2_gate are pseudo-gates. Both can be 571 * independently configured as clock inputs or outputs. We treat 572 * the "output_enable" bit as a gate, even though it's really just 573 * enabling clock output. Initially the gate bits are cleared, as 574 * otherwise the exclusive configuration gets locked in the setup done 575 * by software running before the clock driver, with no way to change 576 * it. 577 */ 578 writel(readl(base + 0x160) & ~0x3c00, base + 0x160); 579 hws[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_hw_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12)); 580 hws[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_hw_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13)); 581 582 hws[IMX6QDL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); 583 hws[IMX6QDL_CLK_LVDS2_IN] = imx_clk_hw_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11)); 584 585 /* name parent_name reg idx */ 586 hws[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); 587 hws[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); 588 hws[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); 589 hws[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_hw_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); 590 hws[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_hw_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); 591 hws[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); 592 hws[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); 593 594 /* name parent_name mult div */ 595 hws[IMX6QDL_CLK_PLL2_198M] = imx_clk_hw_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); 596 hws[IMX6QDL_CLK_PLL3_120M] = imx_clk_hw_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); 597 hws[IMX6QDL_CLK_PLL3_80M] = imx_clk_hw_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); 598 hws[IMX6QDL_CLK_PLL3_60M] = imx_clk_hw_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); 599 hws[IMX6QDL_CLK_TWD] = imx_clk_hw_fixed_factor("twd", "arm", 1, 2); 600 hws[IMX6QDL_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc", 1, 8); 601 hws[IMX6QDL_CLK_VIDEO_27M] = imx_clk_hw_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20); 602 if (clk_on_imx6dl() || clk_on_imx6qp()) { 603 hws[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_hw_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); 604 hws[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_hw_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); 605 } 606 607 hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); 608 if (clk_on_imx6q() || clk_on_imx6qp()) 609 hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = imx_clk_hw_fixed_factor("pll4_audio_div", "pll4_post_div", 1, 1); 610 else 611 hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); 612 hws[IMX6QDL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); 613 hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); 614 615 np = ccm_node; 616 base = of_iomap(np, 0); 617 WARN_ON(!base); 618 619 /* name reg shift width parent_names num_parents */ 620 hws[IMX6QDL_CLK_STEP] = imx_clk_hw_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); 621 hws[IMX6QDL_CLK_PLL1_SW] = imx_clk_hw_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); 622 hws[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_hw_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); 623 hws[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); 624 hws[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); 625 hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); 626 hws[IMX6QDL_CLK_AXI_SEL] = imx_clk_hw_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); 627 hws[IMX6QDL_CLK_ESAI_SEL] = imx_clk_hw_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); 628 hws[IMX6QDL_CLK_ASRC_SEL] = imx_clk_hw_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); 629 hws[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); 630 if (clk_on_imx6q()) { 631 hws[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_hw_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 632 hws[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_hw_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 633 } 634 if (clk_on_imx6qp()) { 635 hws[IMX6QDL_CLK_CAN_SEL] = imx_clk_hw_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); 636 hws[IMX6QDL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); 637 hws[IMX6QDL_CLK_IPG_PER_SEL] = imx_clk_hw_mux("ipg_per_sel", base + 0x1c, 6, 1, ipg_per_sels, ARRAY_SIZE(ipg_per_sels)); 638 hws[IMX6QDL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); 639 hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels_2, ARRAY_SIZE(gpu2d_core_sels_2)); 640 } else if (clk_on_imx6dl()) { 641 hws[IMX6QDL_CLK_MLB_SEL] = imx_clk_hw_mux("mlb_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); 642 } else { 643 hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); 644 } 645 hws[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_hw_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); 646 if (clk_on_imx6dl()) 647 hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); 648 else 649 hws[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_hw_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); 650 hws[IMX6QDL_CLK_IPU1_SEL] = imx_clk_hw_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); 651 hws[IMX6QDL_CLK_IPU2_SEL] = imx_clk_hw_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); 652 653 disable_anatop_clocks(anatop_base); 654 655 imx_mmdc_mask_handshake(base, 1); 656 657 if (clk_on_imx6qp()) { 658 hws[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); 659 hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); 660 } else { 661 /* 662 * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware 663 * bug. Set the muxes to the requested values before registering the 664 * ldb_di_sel clocks. 665 */ 666 init_ldb_clks(np, base); 667 668 hws[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); 669 hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); 670 } 671 672 hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 673 hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 674 hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 675 hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 676 hws[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_hw_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); 677 hws[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_hw_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); 678 679 if (clk_on_imx6qp()) { 680 hws[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_hw_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels_2, ARRAY_SIZE(ipu1_di0_sels_2), CLK_SET_RATE_PARENT); 681 hws[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_hw_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels_2, ARRAY_SIZE(ipu1_di1_sels_2), CLK_SET_RATE_PARENT); 682 hws[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_hw_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels_2, ARRAY_SIZE(ipu2_di0_sels_2), CLK_SET_RATE_PARENT); 683 hws[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_hw_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels_2, ARRAY_SIZE(ipu2_di1_sels_2), CLK_SET_RATE_PARENT); 684 hws[IMX6QDL_CLK_SSI1_SEL] = imx_clk_hw_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 685 hws[IMX6QDL_CLK_SSI2_SEL] = imx_clk_hw_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 686 hws[IMX6QDL_CLK_SSI3_SEL] = imx_clk_hw_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 687 hws[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 688 hws[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 689 hws[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_hw_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 690 hws[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_hw_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 691 hws[IMX6QDL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels_2, ARRAY_SIZE(enfc_sels_2)); 692 hws[IMX6QDL_CLK_EIM_SEL] = imx_clk_hw_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels)); 693 hws[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_hw_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); 694 hws[IMX6QDL_CLK_PRE_AXI] = imx_clk_hw_mux("pre_axi", base + 0x18, 1, 1, pre_axi_sels, ARRAY_SIZE(pre_axi_sels)); 695 } else { 696 hws[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_hw_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); 697 hws[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_hw_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); 698 hws[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_hw_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); 699 hws[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_hw_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); 700 hws[IMX6QDL_CLK_SSI1_SEL] = imx_clk_hw_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 701 hws[IMX6QDL_CLK_SSI2_SEL] = imx_clk_hw_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 702 hws[IMX6QDL_CLK_SSI3_SEL] = imx_clk_hw_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 703 hws[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_hw_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 704 hws[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_hw_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 705 hws[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_hw_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 706 hws[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_hw_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 707 hws[IMX6QDL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); 708 hws[IMX6QDL_CLK_EIM_SEL] = imx_clk_hw_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup); 709 hws[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_hw_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup); 710 } 711 712 hws[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_hw_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); 713 hws[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_hw_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); 714 hws[IMX6QDL_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); 715 hws[IMX6QDL_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); 716 hws[IMX6QDL_CLK_CKO] = imx_clk_hw_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); 717 718 /* name reg shift width busy: reg, shift parent_names num_parents */ 719 hws[IMX6QDL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); 720 hws[IMX6QDL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); 721 722 /* name parent_name reg shift width */ 723 hws[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_hw_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); 724 hws[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_hw_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); 725 hws[IMX6QDL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2); 726 hws[IMX6QDL_CLK_ESAI_PRED] = imx_clk_hw_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); 727 hws[IMX6QDL_CLK_ESAI_PODF] = imx_clk_hw_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); 728 hws[IMX6QDL_CLK_ASRC_PRED] = imx_clk_hw_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); 729 hws[IMX6QDL_CLK_ASRC_PODF] = imx_clk_hw_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); 730 hws[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_hw_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); 731 hws[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_hw_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); 732 733 if (clk_on_imx6qp()) { 734 hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_divider("ipg_per", "ipg_per_sel", base + 0x1c, 0, 6); 735 hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6); 736 hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "can_sel", base + 0x20, 2, 6); 737 hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6); 738 hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7); 739 hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7); 740 } else { 741 hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); 742 hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "pll3_60m", base + 0x20, 2, 6); 743 hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); 744 hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); 745 hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); 746 hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); 747 } 748 749 if (clk_on_imx6dl()) 750 hws[IMX6QDL_CLK_MLB_PODF] = imx_clk_hw_divider("mlb_podf", "mlb_sel", base + 0x18, 23, 3); 751 else 752 hws[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_hw_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); 753 hws[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_hw_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); 754 if (clk_on_imx6dl()) 755 hws[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_hw_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 29, 3); 756 else 757 hws[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_hw_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); 758 hws[IMX6QDL_CLK_IPU1_PODF] = imx_clk_hw_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); 759 hws[IMX6QDL_CLK_IPU2_PODF] = imx_clk_hw_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); 760 hws[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_hw_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); 761 hws[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_hw_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); 762 hws[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_hw_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); 763 hws[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_hw_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); 764 hws[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_hw_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); 765 hws[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_hw_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); 766 hws[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_hw_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); 767 hws[IMX6QDL_CLK_SSI1_PRED] = imx_clk_hw_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); 768 hws[IMX6QDL_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); 769 hws[IMX6QDL_CLK_SSI2_PRED] = imx_clk_hw_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); 770 hws[IMX6QDL_CLK_SSI2_PODF] = imx_clk_hw_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); 771 hws[IMX6QDL_CLK_SSI3_PRED] = imx_clk_hw_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); 772 hws[IMX6QDL_CLK_SSI3_PODF] = imx_clk_hw_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); 773 hws[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); 774 hws[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); 775 hws[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_hw_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); 776 hws[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_hw_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); 777 hws[IMX6QDL_CLK_ENFC_PRED] = imx_clk_hw_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); 778 hws[IMX6QDL_CLK_ENFC_PODF] = imx_clk_hw_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); 779 if (clk_on_imx6qp()) { 780 hws[IMX6QDL_CLK_EIM_PODF] = imx_clk_hw_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3); 781 hws[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_hw_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); 782 } else { 783 hws[IMX6QDL_CLK_EIM_PODF] = imx_clk_hw_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); 784 hws[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_hw_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); 785 } 786 787 hws[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_hw_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); 788 hws[IMX6QDL_CLK_CKO1_PODF] = imx_clk_hw_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); 789 hws[IMX6QDL_CLK_CKO2_PODF] = imx_clk_hw_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); 790 791 /* name parent_name reg shift width busy: reg, shift */ 792 hws[IMX6QDL_CLK_AXI] = imx_clk_hw_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); 793 hws[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); 794 if (clk_on_imx6qp()) { 795 hws[IMX6QDL_CLK_MMDC_CH1_AXI_CG] = imx_clk_hw_gate("mmdc_ch1_axi_cg", "periph2", base + 0x4, 18); 796 hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "mmdc_ch1_axi_cg", base + 0x14, 3, 3, base + 0x48, 2); 797 } else { 798 hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); 799 } 800 hws[IMX6QDL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); 801 hws[IMX6QDL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); 802 803 /* name parent_name reg shift */ 804 hws[IMX6QDL_CLK_APBH_DMA] = imx_clk_hw_gate2("apbh_dma", "usdhc3", base + 0x68, 4); 805 hws[IMX6QDL_CLK_ASRC] = imx_clk_hw_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc); 806 hws[IMX6QDL_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); 807 hws[IMX6QDL_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); 808 hws[IMX6QDL_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem", "ahb", base + 0x68, 8); 809 hws[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk", "ahb", base + 0x68, 10); 810 hws[IMX6QDL_CLK_CAAM_IPG] = imx_clk_hw_gate2("caam_ipg", "ipg", base + 0x68, 12); 811 hws[IMX6QDL_CLK_CAN1_IPG] = imx_clk_hw_gate2("can1_ipg", "ipg", base + 0x68, 14); 812 hws[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_hw_gate2("can1_serial", "can_root", base + 0x68, 16); 813 hws[IMX6QDL_CLK_CAN2_IPG] = imx_clk_hw_gate2("can2_ipg", "ipg", base + 0x68, 18); 814 hws[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_hw_gate2("can2_serial", "can_root", base + 0x68, 20); 815 hws[IMX6QDL_CLK_DCIC1] = imx_clk_hw_gate2("dcic1", "ipu1_podf", base + 0x68, 24); 816 hws[IMX6QDL_CLK_DCIC2] = imx_clk_hw_gate2("dcic2", "ipu2_podf", base + 0x68, 26); 817 hws[IMX6QDL_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); 818 hws[IMX6QDL_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); 819 hws[IMX6QDL_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); 820 hws[IMX6QDL_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); 821 if (clk_on_imx6dl()) 822 hws[IMX6DL_CLK_I2C4] = imx_clk_hw_gate2("i2c4", "ipg_per", base + 0x6c, 8); 823 else 824 hws[IMX6Q_CLK_ECSPI5] = imx_clk_hw_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); 825 hws[IMX6QDL_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x6c, 10); 826 hws[IMX6QDL_CLK_EPIT1] = imx_clk_hw_gate2("epit1", "ipg", base + 0x6c, 12); 827 hws[IMX6QDL_CLK_EPIT2] = imx_clk_hw_gate2("epit2", "ipg", base + 0x6c, 14); 828 hws[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_hw_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); 829 hws[IMX6QDL_CLK_ESAI_IPG] = imx_clk_hw_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); 830 hws[IMX6QDL_CLK_ESAI_MEM] = imx_clk_hw_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); 831 hws[IMX6QDL_CLK_GPT_IPG] = imx_clk_hw_gate2("gpt_ipg", "ipg", base + 0x6c, 20); 832 hws[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_hw_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); 833 hws[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_hw_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); 834 hws[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_hw_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); 835 hws[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_hw_gate2("hdmi_iahb", "ahb", base + 0x70, 0); 836 hws[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_hw_gate2("hdmi_isfr", "mipi_core_cfg", base + 0x70, 4); 837 hws[IMX6QDL_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "ipg_per", base + 0x70, 6); 838 hws[IMX6QDL_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "ipg_per", base + 0x70, 8); 839 hws[IMX6QDL_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "ipg_per", base + 0x70, 10); 840 hws[IMX6QDL_CLK_IIM] = imx_clk_hw_gate2("iim", "ipg", base + 0x70, 12); 841 hws[IMX6QDL_CLK_ENFC] = imx_clk_hw_gate2("enfc", "enfc_podf", base + 0x70, 14); 842 hws[IMX6QDL_CLK_VDOA] = imx_clk_hw_gate2("vdoa", "vdo_axi", base + 0x70, 26); 843 hws[IMX6QDL_CLK_IPU1] = imx_clk_hw_gate2("ipu1", "ipu1_podf", base + 0x74, 0); 844 hws[IMX6QDL_CLK_IPU1_DI0] = imx_clk_hw_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); 845 hws[IMX6QDL_CLK_IPU1_DI1] = imx_clk_hw_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); 846 hws[IMX6QDL_CLK_IPU2] = imx_clk_hw_gate2("ipu2", "ipu2_podf", base + 0x74, 6); 847 hws[IMX6QDL_CLK_IPU2_DI0] = imx_clk_hw_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); 848 if (clk_on_imx6qp()) { 849 hws[IMX6QDL_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0", "ldb_di0_sel", base + 0x74, 12); 850 hws[IMX6QDL_CLK_LDB_DI1] = imx_clk_hw_gate2("ldb_di1", "ldb_di1_sel", base + 0x74, 14); 851 } else { 852 hws[IMX6QDL_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); 853 hws[IMX6QDL_CLK_LDB_DI1] = imx_clk_hw_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); 854 } 855 hws[IMX6QDL_CLK_IPU2_DI1] = imx_clk_hw_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); 856 hws[IMX6QDL_CLK_HSI_TX] = imx_clk_hw_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg); 857 hws[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_hw_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg); 858 hws[IMX6QDL_CLK_MIPI_IPG] = imx_clk_hw_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg); 859 860 if (clk_on_imx6dl()) 861 /* 862 * The multiplexer and divider of the imx6q clock gpu2d get 863 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. 864 */ 865 hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb", "mlb_podf", base + 0x74, 18); 866 else 867 hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb", "axi", base + 0x74, 18); 868 hws[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_hw_gate2_flags("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20, CLK_IS_CRITICAL); 869 hws[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_hw_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); 870 hws[IMX6QDL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); 871 hws[IMX6QDL_CLK_OCRAM] = imx_clk_hw_gate2("ocram", "ahb", base + 0x74, 28); 872 hws[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_hw_gate2("openvg_axi", "axi", base + 0x74, 30); 873 hws[IMX6QDL_CLK_PCIE_AXI] = imx_clk_hw_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); 874 hws[IMX6QDL_CLK_PER1_BCH] = imx_clk_hw_gate2("per1_bch", "usdhc3", base + 0x78, 12); 875 hws[IMX6QDL_CLK_PWM1] = imx_clk_hw_gate2("pwm1", "ipg_per", base + 0x78, 16); 876 hws[IMX6QDL_CLK_PWM2] = imx_clk_hw_gate2("pwm2", "ipg_per", base + 0x78, 18); 877 hws[IMX6QDL_CLK_PWM3] = imx_clk_hw_gate2("pwm3", "ipg_per", base + 0x78, 20); 878 hws[IMX6QDL_CLK_PWM4] = imx_clk_hw_gate2("pwm4", "ipg_per", base + 0x78, 22); 879 hws[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_hw_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); 880 hws[IMX6QDL_CLK_GPMI_BCH] = imx_clk_hw_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); 881 hws[IMX6QDL_CLK_GPMI_IO] = imx_clk_hw_gate2("gpmi_io", "enfc", base + 0x78, 28); 882 hws[IMX6QDL_CLK_GPMI_APB] = imx_clk_hw_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); 883 hws[IMX6QDL_CLK_ROM] = imx_clk_hw_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); 884 hws[IMX6QDL_CLK_SATA] = imx_clk_hw_gate2("sata", "ahb", base + 0x7c, 4); 885 hws[IMX6QDL_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ahb", base + 0x7c, 6); 886 hws[IMX6QDL_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, 12); 887 hws[IMX6QDL_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif); 888 hws[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); 889 hws[IMX6QDL_CLK_SSI1_IPG] = imx_clk_hw_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); 890 hws[IMX6QDL_CLK_SSI2_IPG] = imx_clk_hw_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); 891 hws[IMX6QDL_CLK_SSI3_IPG] = imx_clk_hw_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); 892 hws[IMX6QDL_CLK_SSI1] = imx_clk_hw_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); 893 hws[IMX6QDL_CLK_SSI2] = imx_clk_hw_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); 894 hws[IMX6QDL_CLK_SSI3] = imx_clk_hw_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); 895 hws[IMX6QDL_CLK_UART_IPG] = imx_clk_hw_gate2("uart_ipg", "ipg", base + 0x7c, 24); 896 hws[IMX6QDL_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); 897 hws[IMX6QDL_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg", base + 0x80, 0); 898 hws[IMX6QDL_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); 899 hws[IMX6QDL_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); 900 hws[IMX6QDL_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); 901 hws[IMX6QDL_CLK_USDHC4] = imx_clk_hw_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); 902 hws[IMX6QDL_CLK_EIM_SLOW] = imx_clk_hw_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10); 903 hws[IMX6QDL_CLK_VDO_AXI] = imx_clk_hw_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); 904 hws[IMX6QDL_CLK_VPU_AXI] = imx_clk_hw_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); 905 if (clk_on_imx6qp()) { 906 hws[IMX6QDL_CLK_PRE0] = imx_clk_hw_gate2("pre0", "pre_axi", base + 0x80, 16); 907 hws[IMX6QDL_CLK_PRE1] = imx_clk_hw_gate2("pre1", "pre_axi", base + 0x80, 18); 908 hws[IMX6QDL_CLK_PRE2] = imx_clk_hw_gate2("pre2", "pre_axi", base + 0x80, 20); 909 hws[IMX6QDL_CLK_PRE3] = imx_clk_hw_gate2("pre3", "pre_axi", base + 0x80, 22); 910 hws[IMX6QDL_CLK_PRG0_AXI] = imx_clk_hw_gate2_shared("prg0_axi", "ipu1_podf", base + 0x80, 24, &share_count_prg0); 911 hws[IMX6QDL_CLK_PRG1_AXI] = imx_clk_hw_gate2_shared("prg1_axi", "ipu2_podf", base + 0x80, 26, &share_count_prg1); 912 hws[IMX6QDL_CLK_PRG0_APB] = imx_clk_hw_gate2_shared("prg0_apb", "ipg", base + 0x80, 24, &share_count_prg0); 913 hws[IMX6QDL_CLK_PRG1_APB] = imx_clk_hw_gate2_shared("prg1_apb", "ipg", base + 0x80, 26, &share_count_prg1); 914 } 915 hws[IMX6QDL_CLK_CKO1] = imx_clk_hw_gate("cko1", "cko1_podf", base + 0x60, 7); 916 hws[IMX6QDL_CLK_CKO2] = imx_clk_hw_gate("cko2", "cko2_podf", base + 0x60, 24); 917 918 /* 919 * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it 920 * to clock gpt_ipg_per to ease the gpt driver code. 921 */ 922 if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) 923 hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER]; 924 925 hws[IMX6QDL_CLK_ENET_REF_PAD] = imx6q_obtain_fixed_clk_hw(ccm_node, "enet_ref_pad", 0); 926 927 hws[IMX6QDL_CLK_ENET_REF_SEL] = imx_clk_gpr_mux("enet_ref_sel", "fsl,imx6q-iomuxc-gpr", 928 IOMUXC_GPR1, enet_ref_sels, ARRAY_SIZE(enet_ref_sels), 929 enet_ref_sels_table, enet_ref_sels_table_mask); 930 931 imx_check_clk_hws(hws, IMX6QDL_CLK_END); 932 933 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); 934 935 clk_hw_register_clkdev(hws[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); 936 937 clk_set_rate(hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk, 540000000); 938 if (clk_on_imx6dl()) 939 clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk); 940 941 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); 942 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); 943 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); 944 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); 945 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI0_PRE]->clk); 946 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI1_PRE]->clk); 947 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI0_PRE]->clk); 948 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI1_PRE]->clk); 949 950 /* 951 * The gpmi needs 100MHz frequency in the EDO/Sync mode, 952 * We can not get the 100MHz from the pll2_pfd0_352m. 953 * So choose pll2_pfd2_396m as enfc_sel's parent. 954 */ 955 clk_set_parent(hws[IMX6QDL_CLK_ENFC_SEL]->clk, hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk); 956 957 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { 958 clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY1_GATE]->clk); 959 clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY2_GATE]->clk); 960 } 961 962 /* 963 * Let's initially set up CLKO with OSC24M, since this configuration 964 * is widely used by imx6q board designs to clock audio codec. 965 */ 966 ret = clk_set_parent(hws[IMX6QDL_CLK_CKO2_SEL]->clk, hws[IMX6QDL_CLK_OSC]->clk); 967 if (!ret) 968 ret = clk_set_parent(hws[IMX6QDL_CLK_CKO]->clk, hws[IMX6QDL_CLK_CKO2]->clk); 969 if (ret) 970 pr_warn("failed to set up CLKO: %d\n", ret); 971 972 /* Audio-related clocks configuration */ 973 clk_set_parent(hws[IMX6QDL_CLK_SPDIF_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD3_454M]->clk); 974 975 /* All existing boards with PCIe use LVDS1 */ 976 if (IS_ENABLED(CONFIG_PCI_IMX6)) 977 clk_set_parent(hws[IMX6QDL_CLK_LVDS1_SEL]->clk, hws[IMX6QDL_CLK_SATA_REF_100M]->clk); 978 979 /* 980 * Initialize the GPU clock muxes, so that the maximum specified clock 981 * rates for the respective SoC are not exceeded. 982 */ 983 if (clk_on_imx6dl()) { 984 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, 985 hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); 986 clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk, 987 hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); 988 } else if (clk_on_imx6q()) { 989 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, 990 hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk); 991 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_SHADER_SEL]->clk, 992 hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); 993 clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk, 994 hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); 995 } 996 997 clk_set_parent(hws[IMX6QDL_CLK_ENET_REF_SEL]->clk, hws[IMX6QDL_CLK_ENET_REF]->clk); 998 999 imx_register_uart_clocks(); 1000 } 1001 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); 1002