1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/init.h> 14 #include <linux/types.h> 15 #include <linux/clk.h> 16 #include <linux/clkdev.h> 17 #include <linux/err.h> 18 #include <linux/io.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <soc/imx/revision.h> 23 #include <dt-bindings/clock/imx6qdl-clock.h> 24 25 #include "clk.h" 26 27 static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; 28 static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; 29 static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; 30 static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; 31 static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; 32 static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; 33 static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; 34 static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; 35 static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; 36 static const char *gpu_axi_sels[] = { "axi", "ahb", }; 37 static const char *pre_axi_sels[] = { "axi", "ahb", }; 38 static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; 39 static const char *gpu2d_core_sels_2[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m",}; 40 static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; 41 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; 42 static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; 43 static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; 44 static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; 45 static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 46 static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 47 static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 48 static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 49 static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; 50 static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; 51 static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; 52 static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; 53 static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; 54 static const char *pcie_axi_sels[] = { "axi", "ahb", }; 55 static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; 56 static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; 57 static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; 58 static const char *enfc_sels_2[] = {"pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", }; 59 static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; 60 static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 61 static const char *vdo_axi_sels[] = { "axi", "ahb", }; 62 static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 63 static const char *uart_sels[] = { "pll3_80m", "osc", }; 64 static const char *ipg_per_sels[] = { "ipg", "osc", }; 65 static const char *ecspi_sels[] = { "pll3_60m", "osc", }; 66 static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", }; 67 static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", 68 "video_27m", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", 69 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", }; 70 static const char *cko2_sels[] = { 71 "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", 72 "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", 73 "usdhc3", "dummy", "arm", "ipu1", 74 "ipu2", "vdo_axi", "osc", "gpu2d_core", 75 "gpu3d_core", "usdhc2", "ssi1", "ssi2", 76 "ssi3", "gpu3d_shader", "vpu_axi", "can_root", 77 "ldb_di0", "ldb_di1", "esai_extal", "eim_slow", 78 "uart_serial", "spdif", "asrc", "hsi_tx", 79 }; 80 static const char *cko_sels[] = { "cko1", "cko2", }; 81 static const char *lvds_sels[] = { 82 "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", 83 "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", 84 "pcie_ref_125m", "sata_ref_100m", "usbphy1", "usbphy2", 85 "dummy", "dummy", "dummy", "dummy", "osc", 86 }; 87 static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", }; 88 static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; 89 static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", }; 90 static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; 91 static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", }; 92 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", }; 93 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", }; 94 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; 95 96 static struct clk *clk[IMX6QDL_CLK_END]; 97 static struct clk_onecell_data clk_data; 98 99 static struct clk_div_table clk_enet_ref_table[] = { 100 { .val = 0, .div = 20, }, 101 { .val = 1, .div = 10, }, 102 { .val = 2, .div = 5, }, 103 { .val = 3, .div = 4, }, 104 { /* sentinel */ } 105 }; 106 107 static struct clk_div_table post_div_table[] = { 108 { .val = 2, .div = 1, }, 109 { .val = 1, .div = 2, }, 110 { .val = 0, .div = 4, }, 111 { /* sentinel */ } 112 }; 113 114 static struct clk_div_table video_div_table[] = { 115 { .val = 0, .div = 1, }, 116 { .val = 1, .div = 2, }, 117 { .val = 2, .div = 1, }, 118 { .val = 3, .div = 4, }, 119 { /* sentinel */ } 120 }; 121 122 static unsigned int share_count_esai; 123 static unsigned int share_count_asrc; 124 static unsigned int share_count_ssi1; 125 static unsigned int share_count_ssi2; 126 static unsigned int share_count_ssi3; 127 static unsigned int share_count_mipi_core_cfg; 128 static unsigned int share_count_spdif; 129 static unsigned int share_count_prg0; 130 static unsigned int share_count_prg1; 131 132 static inline int clk_on_imx6q(void) 133 { 134 return of_machine_is_compatible("fsl,imx6q"); 135 } 136 137 static inline int clk_on_imx6qp(void) 138 { 139 return of_machine_is_compatible("fsl,imx6qp"); 140 } 141 142 static inline int clk_on_imx6dl(void) 143 { 144 return of_machine_is_compatible("fsl,imx6dl"); 145 } 146 147 static struct clk ** const uart_clks[] __initconst = { 148 &clk[IMX6QDL_CLK_UART_IPG], 149 &clk[IMX6QDL_CLK_UART_SERIAL], 150 NULL 151 }; 152 153 static int ldb_di_sel_by_clock_id(int clock_id) 154 { 155 switch (clock_id) { 156 case IMX6QDL_CLK_PLL5_VIDEO_DIV: 157 if (clk_on_imx6q() && 158 imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) 159 return -ENOENT; 160 return 0; 161 case IMX6QDL_CLK_PLL2_PFD0_352M: 162 return 1; 163 case IMX6QDL_CLK_PLL2_PFD2_396M: 164 return 2; 165 case IMX6QDL_CLK_MMDC_CH1_AXI: 166 return 3; 167 case IMX6QDL_CLK_PLL3_USB_OTG: 168 return 4; 169 default: 170 return -ENOENT; 171 } 172 } 173 174 static void of_assigned_ldb_sels(struct device_node *node, 175 unsigned int *ldb_di0_sel, 176 unsigned int *ldb_di1_sel) 177 { 178 struct of_phandle_args clkspec; 179 int index, rc, num_parents; 180 int parent, child, sel; 181 182 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", 183 "#clock-cells"); 184 for (index = 0; index < num_parents; index++) { 185 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", 186 "#clock-cells", index, &clkspec); 187 if (rc < 0) { 188 /* skip empty (null) phandles */ 189 if (rc == -ENOENT) 190 continue; 191 else 192 return; 193 } 194 if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { 195 pr_err("ccm: parent clock %d not in ccm\n", index); 196 return; 197 } 198 parent = clkspec.args[0]; 199 200 rc = of_parse_phandle_with_args(node, "assigned-clocks", 201 "#clock-cells", index, &clkspec); 202 if (rc < 0) 203 return; 204 if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { 205 pr_err("ccm: child clock %d not in ccm\n", index); 206 return; 207 } 208 child = clkspec.args[0]; 209 210 if (child != IMX6QDL_CLK_LDB_DI0_SEL && 211 child != IMX6QDL_CLK_LDB_DI1_SEL) 212 continue; 213 214 sel = ldb_di_sel_by_clock_id(parent); 215 if (sel < 0) { 216 pr_err("ccm: invalid ldb_di%d parent clock: %d\n", 217 child == IMX6QDL_CLK_LDB_DI1_SEL, parent); 218 continue; 219 } 220 221 if (child == IMX6QDL_CLK_LDB_DI0_SEL) 222 *ldb_di0_sel = sel; 223 if (child == IMX6QDL_CLK_LDB_DI1_SEL) 224 *ldb_di1_sel = sel; 225 } 226 } 227 228 static bool pll6_bypassed(struct device_node *node) 229 { 230 int index, ret, num_clocks; 231 struct of_phandle_args clkspec; 232 233 num_clocks = of_count_phandle_with_args(node, "assigned-clocks", 234 "#clock-cells"); 235 if (num_clocks < 0) 236 return false; 237 238 for (index = 0; index < num_clocks; index++) { 239 ret = of_parse_phandle_with_args(node, "assigned-clocks", 240 "#clock-cells", index, 241 &clkspec); 242 if (ret < 0) 243 return false; 244 245 if (clkspec.np == node && 246 clkspec.args[0] == IMX6QDL_PLL6_BYPASS) 247 break; 248 } 249 250 /* PLL6 bypass is not part of the assigned clock list */ 251 if (index == num_clocks) 252 return false; 253 254 ret = of_parse_phandle_with_args(node, "assigned-clock-parents", 255 "#clock-cells", index, &clkspec); 256 257 if (clkspec.args[0] != IMX6QDL_CLK_PLL6) 258 return true; 259 260 return false; 261 } 262 263 #define CCM_CCDR 0x04 264 #define CCM_CCSR 0x0c 265 #define CCM_CS2CDR 0x2c 266 267 #define CCDR_MMDC_CH1_MASK BIT(16) 268 #define CCSR_PLL3_SW_CLK_SEL BIT(0) 269 270 #define CS2CDR_LDB_DI0_CLK_SEL_SHIFT 9 271 #define CS2CDR_LDB_DI1_CLK_SEL_SHIFT 12 272 273 static void __init imx6q_mmdc_ch1_mask_handshake(void __iomem *ccm_base) 274 { 275 unsigned int reg; 276 277 reg = readl_relaxed(ccm_base + CCM_CCDR); 278 reg |= CCDR_MMDC_CH1_MASK; 279 writel_relaxed(reg, ccm_base + CCM_CCDR); 280 } 281 282 /* 283 * The only way to disable the MMDC_CH1 clock is to move it to pll3_sw_clk 284 * via periph2_clk2_sel and then to disable pll3_sw_clk by selecting the 285 * bypass clock source, since there is no CG bit for mmdc_ch1. 286 */ 287 static void mmdc_ch1_disable(void __iomem *ccm_base) 288 { 289 unsigned int reg; 290 291 clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL], 292 clk[IMX6QDL_CLK_PLL3_USB_OTG]); 293 294 /* 295 * Handshake with mmdc_ch1 module must be masked when changing 296 * periph2_clk_sel. 297 */ 298 clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_CLK2]); 299 300 /* Disable pll3_sw_clk by selecting the bypass clock source */ 301 reg = readl_relaxed(ccm_base + CCM_CCSR); 302 reg |= CCSR_PLL3_SW_CLK_SEL; 303 writel_relaxed(reg, ccm_base + CCM_CCSR); 304 } 305 306 static void mmdc_ch1_reenable(void __iomem *ccm_base) 307 { 308 unsigned int reg; 309 310 /* Enable pll3_sw_clk by disabling the bypass */ 311 reg = readl_relaxed(ccm_base + CCM_CCSR); 312 reg &= ~CCSR_PLL3_SW_CLK_SEL; 313 writel_relaxed(reg, ccm_base + CCM_CCSR); 314 315 clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_PRE]); 316 } 317 318 /* 319 * We have to follow a strict procedure when changing the LDB clock source, 320 * otherwise we risk introducing a glitch that can lock up the LDB divider. 321 * Things to keep in mind: 322 * 323 * 1. The current and new parent clock inputs to the mux must be disabled. 324 * 2. The default clock input for ldb_di0/1_clk_sel is mmdc_ch1_axi, which 325 * has no CG bit. 326 * 3. pll2_pfd2_396m can not be gated if it is used as memory clock. 327 * 4. In the RTL implementation of the LDB_DI_CLK_SEL muxes the top four 328 * options are in one mux and the PLL3 option along with three unused 329 * inputs is in a second mux. There is a third mux with two inputs used 330 * to decide between the first and second 4-port mux: 331 * 332 * pll5_video_div 0 --|\ 333 * pll2_pfd0_352m 1 --| |_ 334 * pll2_pfd2_396m 2 --| | `-|\ 335 * mmdc_ch1_axi 3 --|/ | | 336 * | |-- 337 * pll3_usb_otg 4 --|\ | | 338 * 5 --| |_,-|/ 339 * 6 --| | 340 * 7 --|/ 341 * 342 * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time. 343 * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below 344 * switches the parent to the bottom mux first and then manipulates the top 345 * mux to ensure that no glitch will enter the divider. 346 */ 347 static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base) 348 { 349 unsigned int reg; 350 unsigned int sel[2][4]; 351 int i; 352 353 reg = readl_relaxed(ccm_base + CCM_CS2CDR); 354 sel[0][0] = (reg >> CS2CDR_LDB_DI0_CLK_SEL_SHIFT) & 7; 355 sel[1][0] = (reg >> CS2CDR_LDB_DI1_CLK_SEL_SHIFT) & 7; 356 357 sel[0][3] = sel[0][2] = sel[0][1] = sel[0][0]; 358 sel[1][3] = sel[1][2] = sel[1][1] = sel[1][0]; 359 360 of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]); 361 362 for (i = 0; i < 2; i++) { 363 /* Warn if a glitch might have been introduced already */ 364 if (sel[i][0] != 3) { 365 pr_warn("ccm: ldb_di%d_sel already changed from reset value: %d\n", 366 i, sel[i][0]); 367 } 368 369 if (sel[i][0] == sel[i][3]) 370 continue; 371 372 /* Only switch to or from pll2_pfd2_396m if it is disabled */ 373 if ((sel[i][0] == 2 || sel[i][3] == 2) && 374 (clk_get_parent(clk[IMX6QDL_CLK_PERIPH_PRE]) == 375 clk[IMX6QDL_CLK_PLL2_PFD2_396M])) { 376 pr_err("ccm: ldb_di%d_sel: couldn't disable pll2_pfd2_396m\n", 377 i); 378 sel[i][3] = sel[i][2] = sel[i][1] = sel[i][0]; 379 continue; 380 } 381 382 /* First switch to the bottom mux */ 383 sel[i][1] = sel[i][0] | 4; 384 385 /* Then configure the top mux before switching back to it */ 386 sel[i][2] = sel[i][3] | 4; 387 388 pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i, 389 sel[i][0], sel[i][1], sel[i][2], sel[i][3]); 390 } 391 392 if (sel[0][0] == sel[0][3] && sel[1][0] == sel[1][3]) 393 return; 394 395 mmdc_ch1_disable(ccm_base); 396 397 for (i = 1; i < 4; i++) { 398 reg = readl_relaxed(ccm_base + CCM_CS2CDR); 399 reg &= ~((7 << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | 400 (7 << CS2CDR_LDB_DI1_CLK_SEL_SHIFT)); 401 reg |= ((sel[0][i] << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | 402 (sel[1][i] << CS2CDR_LDB_DI1_CLK_SEL_SHIFT)); 403 writel_relaxed(reg, ccm_base + CCM_CS2CDR); 404 } 405 406 mmdc_ch1_reenable(ccm_base); 407 } 408 409 #define CCM_ANALOG_PLL_VIDEO 0xa0 410 #define CCM_ANALOG_PFD_480 0xf0 411 #define CCM_ANALOG_PFD_528 0x100 412 413 #define PLL_ENABLE BIT(13) 414 415 #define PFD0_CLKGATE BIT(7) 416 #define PFD1_CLKGATE BIT(15) 417 #define PFD2_CLKGATE BIT(23) 418 #define PFD3_CLKGATE BIT(31) 419 420 static void disable_anatop_clocks(void __iomem *anatop_base) 421 { 422 unsigned int reg; 423 424 /* Make sure PLL2 PFDs 0-2 are gated */ 425 reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528); 426 /* Cannot gate PFD2 if pll2_pfd2_396m is the parent of MMDC clock */ 427 if (clk_get_parent(clk[IMX6QDL_CLK_PERIPH_PRE]) == 428 clk[IMX6QDL_CLK_PLL2_PFD2_396M]) 429 reg |= PFD0_CLKGATE | PFD1_CLKGATE; 430 else 431 reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE; 432 writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528); 433 434 /* Make sure PLL3 PFDs 0-3 are gated */ 435 reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480); 436 reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE; 437 writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480); 438 439 /* Make sure PLL5 is disabled */ 440 reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO); 441 reg &= ~PLL_ENABLE; 442 writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO); 443 } 444 445 static void __init imx6q_clocks_init(struct device_node *ccm_node) 446 { 447 struct device_node *np; 448 void __iomem *anatop_base, *base; 449 int ret; 450 451 clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 452 clk[IMX6QDL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); 453 if (IS_ERR(clk[IMX6QDL_CLK_CKIL])) 454 clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); 455 clk[IMX6QDL_CLK_CKIH] = of_clk_get_by_name(ccm_node, "ckih1"); 456 if (IS_ERR(clk[IMX6QDL_CLK_CKIH])) 457 clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0); 458 clk[IMX6QDL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); 459 if (IS_ERR(clk[IMX6QDL_CLK_OSC])) 460 clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); 461 462 /* Clock source from external clock via CLK1/2 PADs */ 463 clk[IMX6QDL_CLK_ANACLK1] = of_clk_get_by_name(ccm_node, "anaclk1"); 464 if (IS_ERR(clk[IMX6QDL_CLK_ANACLK1])) 465 clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); 466 467 clk[IMX6QDL_CLK_ANACLK2] = of_clk_get_by_name(ccm_node, "anaclk2"); 468 if (IS_ERR(clk[IMX6QDL_CLK_ANACLK2])) 469 clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0); 470 471 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); 472 anatop_base = base = of_iomap(np, 0); 473 WARN_ON(!base); 474 of_node_put(np); 475 476 /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ 477 if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { 478 post_div_table[1].div = 1; 479 post_div_table[2].div = 1; 480 video_div_table[1].div = 1; 481 video_div_table[3].div = 1; 482 } 483 484 clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 485 clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 486 clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 487 clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 488 clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 489 clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 490 clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 491 492 /* type name parent_name base div_mask */ 493 clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f); 494 clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1); 495 clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3); 496 clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f); 497 clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); 498 clk[IMX6QDL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); 499 clk[IMX6QDL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); 500 501 clk[IMX6QDL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); 502 clk[IMX6QDL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); 503 clk[IMX6QDL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); 504 clk[IMX6QDL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); 505 clk[IMX6QDL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); 506 clk[IMX6QDL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); 507 clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); 508 509 /* Do not bypass PLLs initially */ 510 clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]); 511 clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]); 512 clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]); 513 clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]); 514 clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]); 515 clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]); 516 clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]); 517 518 clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); 519 clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); 520 clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); 521 clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); 522 clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); 523 clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); 524 clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); 525 526 /* 527 * Bit 20 is the reserved and read-only bit, we do this only for: 528 * - Do nothing for usbphy clk_enable/disable 529 * - Keep refcount when do usbphy clk_enable/disable, in that case, 530 * the clk framework may need to enable/disable usbphy's parent 531 */ 532 clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); 533 clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); 534 535 /* 536 * usbphy*_gate needs to be on after system boots up, and software 537 * never needs to control it anymore. 538 */ 539 clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); 540 clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); 541 542 /* 543 * The ENET PLL is special in that is has multiple outputs with 544 * different post-dividers that are all affected by the single bypass 545 * bit, so a single mux bit affects 3 independent branches of the clock 546 * tree. There is no good way to model this in the clock framework and 547 * dynamically changing the bypass bit, will yield unexpected results. 548 * So we treat any configuration that bypasses the ENET PLL as 549 * essentially static with the divider ratios reflecting the bypass 550 * status. 551 * 552 */ 553 if (!pll6_bypassed(ccm_node)) { 554 clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); 555 clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); 556 clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, 557 base + 0xe0, 0, 2, 0, clk_enet_ref_table, 558 &imx_ccm_lock); 559 } else { 560 clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 1); 561 clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 1); 562 clk[IMX6QDL_CLK_ENET_REF] = imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1); 563 } 564 565 clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); 566 clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); 567 568 clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); 569 clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); 570 571 /* 572 * lvds1_gate and lvds2_gate are pseudo-gates. Both can be 573 * independently configured as clock inputs or outputs. We treat 574 * the "output_enable" bit as a gate, even though it's really just 575 * enabling clock output. Initially the gate bits are cleared, as 576 * otherwise the exclusive configuration gets locked in the setup done 577 * by software running before the clock driver, with no way to change 578 * it. 579 */ 580 writel(readl(base + 0x160) & ~0x3c00, base + 0x160); 581 clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12)); 582 clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13)); 583 584 clk[IMX6QDL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); 585 clk[IMX6QDL_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11)); 586 587 /* name parent_name reg idx */ 588 clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); 589 clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); 590 clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); 591 clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); 592 clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); 593 clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); 594 clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); 595 596 /* name parent_name mult div */ 597 clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); 598 clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); 599 clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); 600 clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); 601 clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); 602 clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); 603 clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20); 604 if (clk_on_imx6dl() || clk_on_imx6qp()) { 605 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); 606 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); 607 } 608 609 clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); 610 clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); 611 clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); 612 clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); 613 614 np = ccm_node; 615 base = of_iomap(np, 0); 616 WARN_ON(!base); 617 618 /* name reg shift width parent_names num_parents */ 619 clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); 620 clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); 621 clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); 622 clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); 623 clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); 624 clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); 625 clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); 626 clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); 627 clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); 628 clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); 629 if (clk_on_imx6q()) { 630 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 631 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 632 } 633 if (clk_on_imx6qp()) { 634 clk[IMX6QDL_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); 635 clk[IMX6QDL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); 636 clk[IMX6QDL_CLK_IPG_PER_SEL] = imx_clk_mux("ipg_per_sel", base + 0x1c, 6, 1, ipg_per_sels, ARRAY_SIZE(ipg_per_sels)); 637 clk[IMX6QDL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); 638 clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels_2, ARRAY_SIZE(gpu2d_core_sels_2)); 639 } else if (clk_on_imx6dl()) { 640 clk[IMX6QDL_CLK_MLB_SEL] = imx_clk_mux("mlb_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); 641 } else { 642 clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); 643 } 644 clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); 645 if (clk_on_imx6dl()) 646 clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); 647 else 648 clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); 649 clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); 650 clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); 651 652 disable_anatop_clocks(anatop_base); 653 654 imx6q_mmdc_ch1_mask_handshake(base); 655 656 if (clk_on_imx6qp()) { 657 clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); 658 clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); 659 } else { 660 /* 661 * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware 662 * bug. Set the muxes to the requested values before registering the 663 * ldb_di_sel clocks. 664 */ 665 init_ldb_clks(np, base); 666 667 clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); 668 clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); 669 } 670 clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 671 clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 672 clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 673 clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 674 clk[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); 675 clk[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); 676 if (clk_on_imx6qp()) { 677 clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels_2, ARRAY_SIZE(ipu1_di0_sels_2), CLK_SET_RATE_PARENT); 678 clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels_2, ARRAY_SIZE(ipu1_di1_sels_2), CLK_SET_RATE_PARENT); 679 clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels_2, ARRAY_SIZE(ipu2_di0_sels_2), CLK_SET_RATE_PARENT); 680 clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels_2, ARRAY_SIZE(ipu2_di1_sels_2), CLK_SET_RATE_PARENT); 681 clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 682 clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 683 clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 684 clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 685 clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 686 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 687 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 688 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels_2, ARRAY_SIZE(enfc_sels_2)); 689 clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels)); 690 clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); 691 clk[IMX6QDL_CLK_PRE_AXI] = imx_clk_mux("pre_axi", base + 0x18, 1, 1, pre_axi_sels, ARRAY_SIZE(pre_axi_sels)); 692 } else { 693 clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); 694 clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); 695 clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); 696 clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); 697 clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 698 clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 699 clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 700 clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 701 clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 702 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 703 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 704 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); 705 clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup); 706 clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup); 707 } 708 clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); 709 clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); 710 clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); 711 clk[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); 712 clk[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); 713 714 /* name reg shift width busy: reg, shift parent_names num_parents */ 715 clk[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); 716 clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); 717 718 /* name parent_name reg shift width */ 719 clk[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); 720 clk[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); 721 clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); 722 clk[IMX6QDL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); 723 clk[IMX6QDL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); 724 clk[IMX6QDL_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); 725 clk[IMX6QDL_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); 726 clk[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); 727 clk[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); 728 if (clk_on_imx6qp()) { 729 clk[IMX6QDL_CLK_IPG_PER] = imx_clk_divider("ipg_per", "ipg_per_sel", base + 0x1c, 0, 6); 730 clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6); 731 clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "can_sel", base + 0x20, 2, 6); 732 clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6); 733 clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7); 734 clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7); 735 } else { 736 clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); 737 clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); 738 clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); 739 clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); 740 clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); 741 clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); 742 } 743 if (clk_on_imx6dl()) 744 clk[IMX6QDL_CLK_MLB_PODF] = imx_clk_divider("mlb_podf", "mlb_sel", base + 0x18, 23, 3); 745 else 746 clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); 747 clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); 748 if (clk_on_imx6dl()) 749 clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 29, 3); 750 else 751 clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); 752 clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); 753 clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); 754 clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); 755 clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); 756 clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); 757 clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); 758 clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); 759 clk[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); 760 clk[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); 761 clk[IMX6QDL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); 762 clk[IMX6QDL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); 763 clk[IMX6QDL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); 764 clk[IMX6QDL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); 765 clk[IMX6QDL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); 766 clk[IMX6QDL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); 767 clk[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); 768 clk[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); 769 clk[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); 770 clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); 771 clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); 772 clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); 773 if (clk_on_imx6qp()) { 774 clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3); 775 clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); 776 } else { 777 clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); 778 clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); 779 } 780 clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); 781 clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); 782 clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); 783 784 /* name parent_name reg shift width busy: reg, shift */ 785 clk[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); 786 clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); 787 if (clk_on_imx6qp()) { 788 clk[IMX6QDL_CLK_MMDC_CH1_AXI_CG] = imx_clk_gate("mmdc_ch1_axi_cg", "periph2", base + 0x4, 18); 789 clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "mmdc_ch1_axi_cg", base + 0x14, 3, 3, base + 0x48, 2); 790 } else { 791 clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); 792 } 793 clk[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); 794 clk[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); 795 796 /* name parent_name reg shift */ 797 clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); 798 clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc); 799 clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); 800 clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); 801 clk[IMX6QDL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); 802 clk[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); 803 clk[IMX6QDL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); 804 clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); 805 clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); 806 clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); 807 clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); 808 clk[IMX6QDL_CLK_DCIC1] = imx_clk_gate2("dcic1", "ipu1_podf", base + 0x68, 24); 809 clk[IMX6QDL_CLK_DCIC2] = imx_clk_gate2("dcic2", "ipu2_podf", base + 0x68, 26); 810 clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); 811 clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); 812 clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); 813 clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); 814 if (clk_on_imx6dl()) 815 clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8); 816 else 817 clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); 818 clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); 819 clk[IMX6QDL_CLK_EPIT1] = imx_clk_gate2("epit1", "ipg", base + 0x6c, 12); 820 clk[IMX6QDL_CLK_EPIT2] = imx_clk_gate2("epit2", "ipg", base + 0x6c, 14); 821 clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); 822 clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); 823 clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); 824 clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); 825 clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); 826 clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); 827 clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); 828 clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); 829 clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "mipi_core_cfg", base + 0x70, 4); 830 clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); 831 clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); 832 clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); 833 clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); 834 clk[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); 835 clk[IMX6QDL_CLK_VDOA] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); 836 clk[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); 837 clk[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); 838 clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); 839 clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); 840 clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); 841 if (clk_on_imx6qp()) { 842 clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_sel", base + 0x74, 12); 843 clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_sel", base + 0x74, 14); 844 } else { 845 clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); 846 clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); 847 } 848 clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); 849 clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg); 850 clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg); 851 clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg); 852 if (clk_on_imx6dl()) 853 /* 854 * The multiplexer and divider of the imx6q clock gpu2d get 855 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. 856 */ 857 clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "mlb_podf", base + 0x74, 18); 858 else 859 clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); 860 clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2_flags("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20, CLK_IS_CRITICAL); 861 clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); 862 clk[IMX6QDL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); 863 clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); 864 clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); 865 clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); 866 clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); 867 clk[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); 868 clk[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); 869 clk[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); 870 clk[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); 871 clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); 872 clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); 873 clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); 874 clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); 875 clk[IMX6QDL_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); 876 clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4); 877 clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); 878 clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); 879 clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif); 880 clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); 881 clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); 882 clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); 883 clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); 884 clk[IMX6QDL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); 885 clk[IMX6QDL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); 886 clk[IMX6QDL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); 887 clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); 888 clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); 889 clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); 890 clk[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); 891 clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); 892 clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); 893 clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); 894 clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10); 895 clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); 896 clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); 897 if (clk_on_imx6qp()) { 898 clk[IMX6QDL_CLK_PRE0] = imx_clk_gate2("pre0", "pre_axi", base + 0x80, 16); 899 clk[IMX6QDL_CLK_PRE1] = imx_clk_gate2("pre1", "pre_axi", base + 0x80, 18); 900 clk[IMX6QDL_CLK_PRE2] = imx_clk_gate2("pre2", "pre_axi", base + 0x80, 20); 901 clk[IMX6QDL_CLK_PRE3] = imx_clk_gate2("pre3", "pre_axi", base + 0x80, 22); 902 clk[IMX6QDL_CLK_PRG0_AXI] = imx_clk_gate2_shared("prg0_axi", "ipu1_podf", base + 0x80, 24, &share_count_prg0); 903 clk[IMX6QDL_CLK_PRG1_AXI] = imx_clk_gate2_shared("prg1_axi", "ipu2_podf", base + 0x80, 26, &share_count_prg1); 904 clk[IMX6QDL_CLK_PRG0_APB] = imx_clk_gate2_shared("prg0_apb", "ipg", base + 0x80, 24, &share_count_prg0); 905 clk[IMX6QDL_CLK_PRG1_APB] = imx_clk_gate2_shared("prg1_apb", "ipg", base + 0x80, 26, &share_count_prg1); 906 } 907 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); 908 clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); 909 910 /* 911 * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it 912 * to clock gpt_ipg_per to ease the gpt driver code. 913 */ 914 if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) 915 clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER]; 916 917 imx_check_clocks(clk, ARRAY_SIZE(clk)); 918 919 clk_data.clks = clk; 920 clk_data.clk_num = ARRAY_SIZE(clk); 921 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 922 923 clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); 924 925 clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000); 926 if (clk_on_imx6dl()) 927 clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]); 928 929 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); 930 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); 931 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); 932 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); 933 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]); 934 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]); 935 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]); 936 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]); 937 938 /* 939 * The gpmi needs 100MHz frequency in the EDO/Sync mode, 940 * We can not get the 100MHz from the pll2_pfd0_352m. 941 * So choose pll2_pfd2_396m as enfc_sel's parent. 942 */ 943 clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); 944 945 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { 946 clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); 947 clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); 948 } 949 950 /* 951 * Let's initially set up CLKO with OSC24M, since this configuration 952 * is widely used by imx6q board designs to clock audio codec. 953 */ 954 ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]); 955 if (!ret) 956 ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]); 957 if (ret) 958 pr_warn("failed to set up CLKO: %d\n", ret); 959 960 /* Audio-related clocks configuration */ 961 clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]); 962 963 /* All existing boards with PCIe use LVDS1 */ 964 if (IS_ENABLED(CONFIG_PCI_IMX6)) 965 clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); 966 967 /* 968 * Initialize the GPU clock muxes, so that the maximum specified clock 969 * rates for the respective SoC are not exceeded. 970 */ 971 if (clk_on_imx6dl()) { 972 clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], 973 clk[IMX6QDL_CLK_PLL2_PFD1_594M]); 974 clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], 975 clk[IMX6QDL_CLK_PLL2_PFD1_594M]); 976 } else if (clk_on_imx6q()) { 977 clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], 978 clk[IMX6QDL_CLK_MMDC_CH0_AXI]); 979 clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], 980 clk[IMX6QDL_CLK_PLL2_PFD1_594M]); 981 clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], 982 clk[IMX6QDL_CLK_PLL3_USB_OTG]); 983 } 984 985 imx_register_uart_clocks(uart_clks); 986 } 987 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); 988