1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2018 NXP 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/errno.h> 8 #include <linux/export.h> 9 #include <linux/io.h> 10 #include <linux/slab.h> 11 12 #include "clk.h" 13 14 #define PCG_PREDIV_SHIFT 16 15 #define PCG_PREDIV_WIDTH 3 16 #define PCG_PREDIV_MAX 8 17 18 #define PCG_DIV_SHIFT 0 19 #define PCG_CORE_DIV_WIDTH 3 20 #define PCG_DIV_WIDTH 6 21 #define PCG_DIV_MAX 64 22 23 #define PCG_PCS_SHIFT 24 24 #define PCG_PCS_MASK 0x7 25 26 #define PCG_CGC_SHIFT 28 27 28 static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw, 29 unsigned long parent_rate) 30 { 31 struct clk_divider *divider = to_clk_divider(hw); 32 unsigned long prediv_rate; 33 unsigned int prediv_value; 34 unsigned int div_value; 35 36 prediv_value = readl(divider->reg) >> divider->shift; 37 prediv_value &= clk_div_mask(divider->width); 38 39 prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value, 40 NULL, divider->flags, 41 divider->width); 42 43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; 44 div_value &= clk_div_mask(PCG_DIV_WIDTH); 45 46 return divider_recalc_rate(hw, prediv_rate, div_value, NULL, 47 divider->flags, PCG_DIV_WIDTH); 48 } 49 50 static int imx8m_clk_composite_compute_dividers(unsigned long rate, 51 unsigned long parent_rate, 52 int *prediv, int *postdiv) 53 { 54 int div1, div2; 55 int error = INT_MAX; 56 int ret = -EINVAL; 57 58 *prediv = 1; 59 *postdiv = 1; 60 61 for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) { 62 for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) { 63 int new_error = ((parent_rate / div1) / div2) - rate; 64 65 if (abs(new_error) < abs(error)) { 66 *prediv = div1; 67 *postdiv = div2; 68 error = new_error; 69 ret = 0; 70 } 71 } 72 } 73 return ret; 74 } 75 76 static long imx8m_clk_composite_divider_round_rate(struct clk_hw *hw, 77 unsigned long rate, 78 unsigned long *prate) 79 { 80 int prediv_value; 81 int div_value; 82 83 imx8m_clk_composite_compute_dividers(rate, *prate, 84 &prediv_value, &div_value); 85 rate = DIV_ROUND_UP(*prate, prediv_value); 86 87 return DIV_ROUND_UP(rate, div_value); 88 89 } 90 91 static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, 92 unsigned long rate, 93 unsigned long parent_rate) 94 { 95 struct clk_divider *divider = to_clk_divider(hw); 96 unsigned long flags; 97 int prediv_value; 98 int div_value; 99 int ret; 100 u32 val; 101 102 ret = imx8m_clk_composite_compute_dividers(rate, parent_rate, 103 &prediv_value, &div_value); 104 if (ret) 105 return -EINVAL; 106 107 spin_lock_irqsave(divider->lock, flags); 108 109 val = readl(divider->reg); 110 val &= ~((clk_div_mask(divider->width) << divider->shift) | 111 (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); 112 113 val |= (u32)(prediv_value - 1) << divider->shift; 114 val |= (u32)(div_value - 1) << PCG_DIV_SHIFT; 115 writel(val, divider->reg); 116 117 spin_unlock_irqrestore(divider->lock, flags); 118 119 return ret; 120 } 121 122 static int imx8m_divider_determine_rate(struct clk_hw *hw, 123 struct clk_rate_request *req) 124 { 125 struct clk_divider *divider = to_clk_divider(hw); 126 int prediv_value; 127 int div_value; 128 129 /* if read only, just return current value */ 130 if (divider->flags & CLK_DIVIDER_READ_ONLY) { 131 u32 val; 132 133 val = readl(divider->reg); 134 prediv_value = val >> divider->shift; 135 prediv_value &= clk_div_mask(divider->width); 136 prediv_value++; 137 138 div_value = val >> PCG_DIV_SHIFT; 139 div_value &= clk_div_mask(PCG_DIV_WIDTH); 140 div_value++; 141 142 return divider_ro_determine_rate(hw, req, divider->table, 143 PCG_PREDIV_WIDTH + PCG_DIV_WIDTH, 144 divider->flags, prediv_value * div_value); 145 } 146 147 return divider_determine_rate(hw, req, divider->table, 148 PCG_PREDIV_WIDTH + PCG_DIV_WIDTH, 149 divider->flags); 150 } 151 152 static const struct clk_ops imx8m_clk_composite_divider_ops = { 153 .recalc_rate = imx8m_clk_composite_divider_recalc_rate, 154 .round_rate = imx8m_clk_composite_divider_round_rate, 155 .set_rate = imx8m_clk_composite_divider_set_rate, 156 .determine_rate = imx8m_divider_determine_rate, 157 }; 158 159 static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) 160 { 161 return clk_mux_ops.get_parent(hw); 162 } 163 164 static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index) 165 { 166 struct clk_mux *mux = to_clk_mux(hw); 167 u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); 168 unsigned long flags = 0; 169 u32 reg; 170 171 if (mux->lock) 172 spin_lock_irqsave(mux->lock, flags); 173 174 reg = readl(mux->reg); 175 reg &= ~(mux->mask << mux->shift); 176 val = val << mux->shift; 177 reg |= val; 178 /* 179 * write twice to make sure non-target interface 180 * SEL_A/B point the same clk input. 181 */ 182 writel(reg, mux->reg); 183 writel(reg, mux->reg); 184 185 if (mux->lock) 186 spin_unlock_irqrestore(mux->lock, flags); 187 188 return 0; 189 } 190 191 static int 192 imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw, 193 struct clk_rate_request *req) 194 { 195 return clk_mux_ops.determine_rate(hw, req); 196 } 197 198 199 static const struct clk_ops imx8m_clk_composite_mux_ops = { 200 .get_parent = imx8m_clk_composite_mux_get_parent, 201 .set_parent = imx8m_clk_composite_mux_set_parent, 202 .determine_rate = imx8m_clk_composite_mux_determine_rate, 203 }; 204 205 struct clk_hw *__imx8m_clk_hw_composite(const char *name, 206 const char * const *parent_names, 207 int num_parents, void __iomem *reg, 208 u32 composite_flags, 209 unsigned long flags) 210 { 211 struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw; 212 struct clk_hw *div_hw, *gate_hw = NULL; 213 struct clk_divider *div = NULL; 214 struct clk_gate *gate = NULL; 215 struct clk_mux *mux = NULL; 216 const struct clk_ops *divider_ops; 217 const struct clk_ops *mux_ops; 218 219 mux = kzalloc(sizeof(*mux), GFP_KERNEL); 220 if (!mux) 221 goto fail; 222 223 mux_hw = &mux->hw; 224 mux->reg = reg; 225 mux->shift = PCG_PCS_SHIFT; 226 mux->mask = PCG_PCS_MASK; 227 mux->lock = &imx_ccm_lock; 228 229 div = kzalloc(sizeof(*div), GFP_KERNEL); 230 if (!div) 231 goto fail; 232 233 div_hw = &div->hw; 234 div->reg = reg; 235 if (composite_flags & IMX_COMPOSITE_CORE) { 236 div->shift = PCG_DIV_SHIFT; 237 div->width = PCG_CORE_DIV_WIDTH; 238 divider_ops = &clk_divider_ops; 239 mux_ops = &imx8m_clk_composite_mux_ops; 240 } else if (composite_flags & IMX_COMPOSITE_BUS) { 241 div->shift = PCG_PREDIV_SHIFT; 242 div->width = PCG_PREDIV_WIDTH; 243 divider_ops = &imx8m_clk_composite_divider_ops; 244 mux_ops = &imx8m_clk_composite_mux_ops; 245 } else { 246 div->shift = PCG_PREDIV_SHIFT; 247 div->width = PCG_PREDIV_WIDTH; 248 divider_ops = &imx8m_clk_composite_divider_ops; 249 mux_ops = &clk_mux_ops; 250 if (!(composite_flags & IMX_COMPOSITE_FW_MANAGED)) 251 flags |= CLK_SET_PARENT_GATE; 252 } 253 254 div->lock = &imx_ccm_lock; 255 div->flags = CLK_DIVIDER_ROUND_CLOSEST; 256 257 /* skip registering the gate ops if M4 is enabled */ 258 if (!mcore_booted) { 259 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 260 if (!gate) 261 goto fail; 262 263 gate_hw = &gate->hw; 264 gate->reg = reg; 265 gate->bit_idx = PCG_CGC_SHIFT; 266 gate->lock = &imx_ccm_lock; 267 } 268 269 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, 270 mux_hw, mux_ops, div_hw, 271 divider_ops, gate_hw, &clk_gate_ops, flags); 272 if (IS_ERR(hw)) 273 goto fail; 274 275 return hw; 276 277 fail: 278 kfree(gate); 279 kfree(div); 280 kfree(mux); 281 return ERR_CAST(hw); 282 } 283 EXPORT_SYMBOL_GPL(__imx8m_clk_hw_composite); 284