1 /* 2 * Hi3798CV200 Clock and Reset Generator Driver 3 * 4 * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <dt-bindings/clock/histb-clock.h> 21 #include <linux/clk-provider.h> 22 #include <linux/module.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include "clk.h" 26 #include "crg.h" 27 #include "reset.h" 28 29 /* hi3798CV200 core CRG */ 30 #define HI3798CV200_INNER_CLK_OFFSET 64 31 #define HI3798CV200_FIXED_24M 65 32 #define HI3798CV200_FIXED_25M 66 33 #define HI3798CV200_FIXED_50M 67 34 #define HI3798CV200_FIXED_75M 68 35 #define HI3798CV200_FIXED_100M 69 36 #define HI3798CV200_FIXED_150M 70 37 #define HI3798CV200_FIXED_200M 71 38 #define HI3798CV200_FIXED_250M 72 39 #define HI3798CV200_FIXED_300M 73 40 #define HI3798CV200_FIXED_400M 74 41 #define HI3798CV200_MMC_MUX 75 42 #define HI3798CV200_ETH_PUB_CLK 76 43 #define HI3798CV200_ETH_BUS_CLK 77 44 #define HI3798CV200_ETH_BUS0_CLK 78 45 #define HI3798CV200_ETH_BUS1_CLK 79 46 #define HI3798CV200_COMBPHY1_MUX 80 47 48 #define HI3798CV200_CRG_NR_CLKS 128 49 50 static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = { 51 { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, 52 { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, 53 { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, 54 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, }, 55 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, }, 56 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, }, 57 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, }, 58 { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, }, 59 { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, }, 60 { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, }, 61 { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, }, 62 }; 63 64 static const char *const mmc_mux_p[] = { 65 "100m", "50m", "25m", "200m", "150m" }; 66 static u32 mmc_mux_table[] = {0, 1, 2, 3, 6}; 67 68 static const char *const comphy1_mux_p[] = { 69 "100m", "25m"}; 70 static u32 comphy1_mux_table[] = {2, 3}; 71 72 static struct hisi_mux_clock hi3798cv200_mux_clks[] = { 73 { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), 74 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, }, 75 { HI3798CV200_COMBPHY1_MUX, "combphy1_mux", 76 comphy1_mux_p, ARRAY_SIZE(comphy1_mux_p), 77 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, }, 78 }; 79 80 static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { 81 /* UART */ 82 { HISTB_UART2_CLK, "clk_uart2", "75m", 83 CLK_SET_RATE_PARENT, 0x68, 4, 0, }, 84 /* I2C */ 85 { HISTB_I2C0_CLK, "clk_i2c0", "clk_apb", 86 CLK_SET_RATE_PARENT, 0x6C, 4, 0, }, 87 { HISTB_I2C1_CLK, "clk_i2c1", "clk_apb", 88 CLK_SET_RATE_PARENT, 0x6C, 8, 0, }, 89 { HISTB_I2C2_CLK, "clk_i2c2", "clk_apb", 90 CLK_SET_RATE_PARENT, 0x6C, 12, 0, }, 91 { HISTB_I2C3_CLK, "clk_i2c3", "clk_apb", 92 CLK_SET_RATE_PARENT, 0x6C, 16, 0, }, 93 { HISTB_I2C4_CLK, "clk_i2c4", "clk_apb", 94 CLK_SET_RATE_PARENT, 0x6C, 20, 0, }, 95 /* SPI */ 96 { HISTB_SPI0_CLK, "clk_spi0", "clk_apb", 97 CLK_SET_RATE_PARENT, 0x70, 0, 0, }, 98 /* SDIO */ 99 { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m", 100 CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, 101 { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "mmc_mux", 102 CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, 103 /* EMMC */ 104 { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m", 105 CLK_SET_RATE_PARENT, 0xa0, 0, 0, }, 106 { HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux", 107 CLK_SET_RATE_PARENT, 0xa0, 1, 0, }, 108 /* PCIE*/ 109 { HISTB_PCIE_BUS_CLK, "clk_pcie_bus", "200m", 110 CLK_SET_RATE_PARENT, 0x18c, 0, 0, }, 111 { HISTB_PCIE_SYS_CLK, "clk_pcie_sys", "100m", 112 CLK_SET_RATE_PARENT, 0x18c, 1, 0, }, 113 { HISTB_PCIE_PIPE_CLK, "clk_pcie_pipe", "250m", 114 CLK_SET_RATE_PARENT, 0x18c, 2, 0, }, 115 { HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m", 116 CLK_SET_RATE_PARENT, 0x18c, 3, 0, }, 117 /* Ethernet */ 118 { HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL, 119 CLK_SET_RATE_PARENT, 0xcc, 5, 0, }, 120 { HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub", 121 CLK_SET_RATE_PARENT, 0xcc, 0, 0, }, 122 { HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus", 123 CLK_SET_RATE_PARENT, 0xcc, 1, 0, }, 124 { HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus", 125 CLK_SET_RATE_PARENT, 0xcc, 2, 0, }, 126 { HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0", 127 CLK_SET_RATE_PARENT, 0xcc, 3, 0, }, 128 { HISTB_ETH0_MACIF_CLK, "clk_macif0", "clk_bus_m0", 129 CLK_SET_RATE_PARENT, 0xcc, 24, 0, }, 130 { HISTB_ETH1_MAC_CLK, "clk_mac1", "clk_bus_m1", 131 CLK_SET_RATE_PARENT, 0xcc, 4, 0, }, 132 { HISTB_ETH1_MACIF_CLK, "clk_macif1", "clk_bus_m1", 133 CLK_SET_RATE_PARENT, 0xcc, 25, 0, }, 134 /* COMBPHY1 */ 135 { HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux", 136 CLK_SET_RATE_PARENT, 0x188, 8, 0, }, 137 }; 138 139 static struct hisi_clock_data *hi3798cv200_clk_register( 140 struct platform_device *pdev) 141 { 142 struct hisi_clock_data *clk_data; 143 int ret; 144 145 clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS); 146 if (!clk_data) 147 return ERR_PTR(-ENOMEM); 148 149 ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks, 150 ARRAY_SIZE(hi3798cv200_fixed_rate_clks), 151 clk_data); 152 if (ret) 153 return ERR_PTR(ret); 154 155 ret = hisi_clk_register_mux(hi3798cv200_mux_clks, 156 ARRAY_SIZE(hi3798cv200_mux_clks), 157 clk_data); 158 if (ret) 159 goto unregister_fixed_rate; 160 161 ret = hisi_clk_register_gate(hi3798cv200_gate_clks, 162 ARRAY_SIZE(hi3798cv200_gate_clks), 163 clk_data); 164 if (ret) 165 goto unregister_mux; 166 167 ret = of_clk_add_provider(pdev->dev.of_node, 168 of_clk_src_onecell_get, &clk_data->clk_data); 169 if (ret) 170 goto unregister_gate; 171 172 return clk_data; 173 174 unregister_fixed_rate: 175 hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, 176 ARRAY_SIZE(hi3798cv200_fixed_rate_clks), 177 clk_data); 178 179 unregister_mux: 180 hisi_clk_unregister_mux(hi3798cv200_mux_clks, 181 ARRAY_SIZE(hi3798cv200_mux_clks), 182 clk_data); 183 unregister_gate: 184 hisi_clk_unregister_gate(hi3798cv200_gate_clks, 185 ARRAY_SIZE(hi3798cv200_gate_clks), 186 clk_data); 187 return ERR_PTR(ret); 188 } 189 190 static void hi3798cv200_clk_unregister(struct platform_device *pdev) 191 { 192 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); 193 194 of_clk_del_provider(pdev->dev.of_node); 195 196 hisi_clk_unregister_gate(hi3798cv200_gate_clks, 197 ARRAY_SIZE(hi3798cv200_gate_clks), 198 crg->clk_data); 199 hisi_clk_unregister_mux(hi3798cv200_mux_clks, 200 ARRAY_SIZE(hi3798cv200_mux_clks), 201 crg->clk_data); 202 hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, 203 ARRAY_SIZE(hi3798cv200_fixed_rate_clks), 204 crg->clk_data); 205 } 206 207 static const struct hisi_crg_funcs hi3798cv200_crg_funcs = { 208 .register_clks = hi3798cv200_clk_register, 209 .unregister_clks = hi3798cv200_clk_unregister, 210 }; 211 212 /* hi3798CV200 sysctrl CRG */ 213 214 #define HI3798CV200_SYSCTRL_NR_CLKS 16 215 216 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = { 217 { HISTB_IR_CLK, "clk_ir", "100m", 218 CLK_SET_RATE_PARENT, 0x48, 4, 0, }, 219 { HISTB_TIMER01_CLK, "clk_timer01", "24m", 220 CLK_SET_RATE_PARENT, 0x48, 6, 0, }, 221 { HISTB_UART0_CLK, "clk_uart0", "75m", 222 CLK_SET_RATE_PARENT, 0x48, 10, 0, }, 223 }; 224 225 static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register( 226 struct platform_device *pdev) 227 { 228 struct hisi_clock_data *clk_data; 229 int ret; 230 231 clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS); 232 if (!clk_data) 233 return ERR_PTR(-ENOMEM); 234 235 ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks, 236 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), 237 clk_data); 238 if (ret) 239 return ERR_PTR(ret); 240 241 ret = of_clk_add_provider(pdev->dev.of_node, 242 of_clk_src_onecell_get, &clk_data->clk_data); 243 if (ret) 244 goto unregister_gate; 245 246 return clk_data; 247 248 unregister_gate: 249 hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, 250 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), 251 clk_data); 252 return ERR_PTR(ret); 253 } 254 255 static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev) 256 { 257 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); 258 259 of_clk_del_provider(pdev->dev.of_node); 260 261 hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, 262 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), 263 crg->clk_data); 264 } 265 266 static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = { 267 .register_clks = hi3798cv200_sysctrl_clk_register, 268 .unregister_clks = hi3798cv200_sysctrl_clk_unregister, 269 }; 270 271 static const struct of_device_id hi3798cv200_crg_match_table[] = { 272 { .compatible = "hisilicon,hi3798cv200-crg", 273 .data = &hi3798cv200_crg_funcs }, 274 { .compatible = "hisilicon,hi3798cv200-sysctrl", 275 .data = &hi3798cv200_sysctrl_funcs }, 276 { } 277 }; 278 MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table); 279 280 static int hi3798cv200_crg_probe(struct platform_device *pdev) 281 { 282 struct hisi_crg_dev *crg; 283 284 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); 285 if (!crg) 286 return -ENOMEM; 287 288 crg->funcs = of_device_get_match_data(&pdev->dev); 289 if (!crg->funcs) 290 return -ENOENT; 291 292 crg->rstc = hisi_reset_init(pdev); 293 if (!crg->rstc) 294 return -ENOMEM; 295 296 crg->clk_data = crg->funcs->register_clks(pdev); 297 if (IS_ERR(crg->clk_data)) { 298 hisi_reset_exit(crg->rstc); 299 return PTR_ERR(crg->clk_data); 300 } 301 302 platform_set_drvdata(pdev, crg); 303 return 0; 304 } 305 306 static int hi3798cv200_crg_remove(struct platform_device *pdev) 307 { 308 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); 309 310 hisi_reset_exit(crg->rstc); 311 crg->funcs->unregister_clks(pdev); 312 return 0; 313 } 314 315 static struct platform_driver hi3798cv200_crg_driver = { 316 .probe = hi3798cv200_crg_probe, 317 .remove = hi3798cv200_crg_remove, 318 .driver = { 319 .name = "hi3798cv200-crg", 320 .of_match_table = hi3798cv200_crg_match_table, 321 }, 322 }; 323 324 static int __init hi3798cv200_crg_init(void) 325 { 326 return platform_driver_register(&hi3798cv200_crg_driver); 327 } 328 core_initcall(hi3798cv200_crg_init); 329 330 static void __exit hi3798cv200_crg_exit(void) 331 { 332 platform_driver_unregister(&hi3798cv200_crg_driver); 333 } 334 module_exit(hi3798cv200_crg_exit); 335 336 MODULE_LICENSE("GPL v2"); 337 MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver"); 338