1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * clk-xgene.c - AppliedMicro X-Gene Clock Interface 4 * 5 * Copyright (c) 2013, Applied Micro Circuits Corporation 6 * Author: Loc Ho <lho@apm.com> 7 */ 8 #include <linux/module.h> 9 #include <linux/spinlock.h> 10 #include <linux/string_choices.h> 11 #include <linux/io.h> 12 #include <linux/of.h> 13 #include <linux/clkdev.h> 14 #include <linux/clk-provider.h> 15 #include <linux/of_address.h> 16 17 /* Register SCU_PCPPLL bit fields */ 18 #define N_DIV_RD(src) ((src) & 0x000001ff) 19 #define SC_N_DIV_RD(src) ((src) & 0x0000007f) 20 #define SC_OUTDIV2(src) (((src) & 0x00000100) >> 8) 21 22 /* Register SCU_SOCPLL bit fields */ 23 #define CLKR_RD(src) (((src) & 0x07000000)>>24) 24 #define CLKOD_RD(src) (((src) & 0x00300000)>>20) 25 #define REGSPEC_RESET_F1_MASK 0x00010000 26 #define CLKF_RD(src) (((src) & 0x000001ff)) 27 28 #define XGENE_CLK_DRIVER_VER "0.1" 29 30 static DEFINE_SPINLOCK(clk_lock); 31 32 static inline u32 xgene_clk_read(void __iomem *csr) 33 { 34 return readl_relaxed(csr); 35 } 36 37 static inline void xgene_clk_write(u32 data, void __iomem *csr) 38 { 39 writel_relaxed(data, csr); 40 } 41 42 /* PLL Clock */ 43 enum xgene_pll_type { 44 PLL_TYPE_PCP = 0, 45 PLL_TYPE_SOC = 1, 46 }; 47 48 struct xgene_clk_pll { 49 struct clk_hw hw; 50 void __iomem *reg; 51 spinlock_t *lock; 52 u32 pll_offset; 53 enum xgene_pll_type type; 54 int version; 55 }; 56 57 #define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw) 58 59 static int xgene_clk_pll_is_enabled(struct clk_hw *hw) 60 { 61 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); 62 u32 data; 63 64 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); 65 pr_debug("%s pll %s\n", clk_hw_get_name(hw), 66 data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled"); 67 68 return data & REGSPEC_RESET_F1_MASK ? 0 : 1; 69 } 70 71 static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw, 72 unsigned long parent_rate) 73 { 74 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); 75 unsigned long fref; 76 unsigned long fvco; 77 u32 pll; 78 u32 nref; 79 u32 nout; 80 u32 nfb; 81 82 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); 83 84 if (pllclk->version <= 1) { 85 if (pllclk->type == PLL_TYPE_PCP) { 86 /* 87 * PLL VCO = Reference clock * NF 88 * PCP PLL = PLL_VCO / 2 89 */ 90 nout = 2; 91 fvco = parent_rate * (N_DIV_RD(pll) + 4); 92 } else { 93 /* 94 * Fref = Reference Clock / NREF; 95 * Fvco = Fref * NFB; 96 * Fout = Fvco / NOUT; 97 */ 98 nref = CLKR_RD(pll) + 1; 99 nout = CLKOD_RD(pll) + 1; 100 nfb = CLKF_RD(pll); 101 fref = parent_rate / nref; 102 fvco = fref * nfb; 103 } 104 } else { 105 /* 106 * fvco = Reference clock * FBDIVC 107 * PLL freq = fvco / NOUT 108 */ 109 nout = SC_OUTDIV2(pll) ? 2 : 3; 110 fvco = parent_rate * SC_N_DIV_RD(pll); 111 } 112 pr_debug("%s pll recalc rate %ld parent %ld version %d\n", 113 clk_hw_get_name(hw), fvco / nout, parent_rate, 114 pllclk->version); 115 116 return fvco / nout; 117 } 118 119 static const struct clk_ops xgene_clk_pll_ops = { 120 .is_enabled = xgene_clk_pll_is_enabled, 121 .recalc_rate = xgene_clk_pll_recalc_rate, 122 }; 123 124 static struct clk *xgene_register_clk_pll(struct device *dev, 125 const char *name, const char *parent_name, 126 unsigned long flags, void __iomem *reg, u32 pll_offset, 127 u32 type, spinlock_t *lock, int version) 128 { 129 struct xgene_clk_pll *apmclk; 130 struct clk *clk; 131 struct clk_init_data init; 132 133 /* allocate the APM clock structure */ 134 apmclk = kzalloc_obj(*apmclk); 135 if (!apmclk) 136 return ERR_PTR(-ENOMEM); 137 138 init.name = name; 139 init.ops = &xgene_clk_pll_ops; 140 init.flags = flags; 141 init.parent_names = parent_name ? &parent_name : NULL; 142 init.num_parents = parent_name ? 1 : 0; 143 144 apmclk->version = version; 145 apmclk->reg = reg; 146 apmclk->lock = lock; 147 apmclk->pll_offset = pll_offset; 148 apmclk->type = type; 149 apmclk->hw.init = &init; 150 151 /* Register the clock */ 152 clk = clk_register(dev, &apmclk->hw); 153 if (IS_ERR(clk)) { 154 pr_err("%s: could not register clk %s\n", __func__, name); 155 kfree(apmclk); 156 return NULL; 157 } 158 return clk; 159 } 160 161 static int xgene_pllclk_version(struct device_node *np) 162 { 163 if (of_device_is_compatible(np, "apm,xgene-socpll-clock")) 164 return 1; 165 if (of_device_is_compatible(np, "apm,xgene-pcppll-clock")) 166 return 1; 167 return 2; 168 } 169 170 static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type) 171 { 172 const char *clk_name = np->full_name; 173 struct clk *clk; 174 void __iomem *reg; 175 int version = xgene_pllclk_version(np); 176 177 reg = of_iomap(np, 0); 178 if (!reg) { 179 pr_err("Unable to map CSR register for %pOF\n", np); 180 return; 181 } 182 of_property_read_string(np, "clock-output-names", &clk_name); 183 clk = xgene_register_clk_pll(NULL, 184 clk_name, of_clk_get_parent_name(np, 0), 185 0, reg, 0, pll_type, &clk_lock, 186 version); 187 if (!IS_ERR(clk)) { 188 of_clk_add_provider(np, of_clk_src_simple_get, clk); 189 clk_register_clkdev(clk, clk_name, NULL); 190 pr_debug("Add %s clock PLL\n", clk_name); 191 } else { 192 iounmap(reg); 193 } 194 } 195 196 static void xgene_socpllclk_init(struct device_node *np) 197 { 198 xgene_pllclk_init(np, PLL_TYPE_SOC); 199 } 200 201 static void xgene_pcppllclk_init(struct device_node *np) 202 { 203 xgene_pllclk_init(np, PLL_TYPE_PCP); 204 } 205 206 /** 207 * struct xgene_clk_pmd - PMD clock 208 * 209 * @hw: handle between common and hardware-specific interfaces 210 * @reg: register containing the fractional scale multiplier (scaler) 211 * @shift: shift to the unit bit field 212 * @mask: mask to the unit bit field 213 * @denom: 1/denominator unit 214 * @lock: register lock 215 * @flags: XGENE_CLK_PMD_SCALE_INVERTED - By default the scaler is the value read 216 * from the register plus one. For example, 217 * 0 for (0 + 1) / denom, 218 * 1 for (1 + 1) / denom and etc. 219 * If this flag is set, it is 220 * 0 for (denom - 0) / denom, 221 * 1 for (denom - 1) / denom and etc. 222 */ 223 struct xgene_clk_pmd { 224 struct clk_hw hw; 225 void __iomem *reg; 226 u8 shift; 227 u32 mask; 228 u64 denom; 229 u32 flags; 230 spinlock_t *lock; 231 }; 232 233 #define to_xgene_clk_pmd(_hw) container_of(_hw, struct xgene_clk_pmd, hw) 234 235 #define XGENE_CLK_PMD_SCALE_INVERTED BIT(0) 236 #define XGENE_CLK_PMD_SHIFT 8 237 #define XGENE_CLK_PMD_WIDTH 3 238 239 static unsigned long xgene_clk_pmd_recalc_rate(struct clk_hw *hw, 240 unsigned long parent_rate) 241 { 242 struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw); 243 unsigned long flags = 0; 244 u64 ret, scale; 245 u32 val; 246 247 if (fd->lock) 248 spin_lock_irqsave(fd->lock, flags); 249 else 250 __acquire(fd->lock); 251 252 val = readl(fd->reg); 253 254 if (fd->lock) 255 spin_unlock_irqrestore(fd->lock, flags); 256 else 257 __release(fd->lock); 258 259 ret = (u64)parent_rate; 260 261 scale = (val & fd->mask) >> fd->shift; 262 if (fd->flags & XGENE_CLK_PMD_SCALE_INVERTED) 263 scale = fd->denom - scale; 264 else 265 scale++; 266 267 /* freq = parent_rate * scaler / denom */ 268 do_div(ret, fd->denom); 269 ret *= scale; 270 if (ret == 0) 271 ret = (u64)parent_rate; 272 273 return ret; 274 } 275 276 static int xgene_clk_pmd_determine_rate(struct clk_hw *hw, 277 struct clk_rate_request *req) 278 { 279 struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw); 280 u64 ret, scale; 281 282 if (!req->rate || req->rate >= req->best_parent_rate) { 283 req->rate = req->best_parent_rate; 284 285 return 0; 286 } 287 288 /* freq = parent_rate * scaler / denom */ 289 ret = req->rate * fd->denom; 290 scale = DIV_ROUND_UP_ULL(ret, req->best_parent_rate); 291 292 ret = (u64)req->best_parent_rate * scale; 293 do_div(ret, fd->denom); 294 295 req->rate = ret; 296 297 return 0; 298 } 299 300 static int xgene_clk_pmd_set_rate(struct clk_hw *hw, unsigned long rate, 301 unsigned long parent_rate) 302 { 303 struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw); 304 unsigned long flags = 0; 305 u64 scale, ret; 306 u32 val; 307 308 /* 309 * Compute the scaler: 310 * 311 * freq = parent_rate * scaler / denom, or 312 * scaler = freq * denom / parent_rate 313 */ 314 ret = rate * fd->denom; 315 scale = DIV_ROUND_UP_ULL(ret, (u64)parent_rate); 316 317 /* Check if inverted */ 318 if (fd->flags & XGENE_CLK_PMD_SCALE_INVERTED) 319 scale = fd->denom - scale; 320 else 321 scale--; 322 323 if (fd->lock) 324 spin_lock_irqsave(fd->lock, flags); 325 else 326 __acquire(fd->lock); 327 328 val = readl(fd->reg); 329 val &= ~fd->mask; 330 val |= (scale << fd->shift); 331 writel(val, fd->reg); 332 333 if (fd->lock) 334 spin_unlock_irqrestore(fd->lock, flags); 335 else 336 __release(fd->lock); 337 338 return 0; 339 } 340 341 static const struct clk_ops xgene_clk_pmd_ops = { 342 .recalc_rate = xgene_clk_pmd_recalc_rate, 343 .determine_rate = xgene_clk_pmd_determine_rate, 344 .set_rate = xgene_clk_pmd_set_rate, 345 }; 346 347 static struct clk * 348 xgene_register_clk_pmd(struct device *dev, 349 const char *name, const char *parent_name, 350 unsigned long flags, void __iomem *reg, u8 shift, 351 u8 width, u64 denom, u32 clk_flags, spinlock_t *lock) 352 { 353 struct xgene_clk_pmd *fd; 354 struct clk_init_data init; 355 struct clk *clk; 356 357 fd = kzalloc_obj(*fd); 358 if (!fd) 359 return ERR_PTR(-ENOMEM); 360 361 init.name = name; 362 init.ops = &xgene_clk_pmd_ops; 363 init.flags = flags; 364 init.parent_names = parent_name ? &parent_name : NULL; 365 init.num_parents = parent_name ? 1 : 0; 366 367 fd->reg = reg; 368 fd->shift = shift; 369 fd->mask = (BIT(width) - 1) << shift; 370 fd->denom = denom; 371 fd->flags = clk_flags; 372 fd->lock = lock; 373 fd->hw.init = &init; 374 375 clk = clk_register(dev, &fd->hw); 376 if (IS_ERR(clk)) { 377 pr_err("%s: could not register clk %s\n", __func__, name); 378 kfree(fd); 379 return NULL; 380 } 381 382 return clk; 383 } 384 385 static void xgene_pmdclk_init(struct device_node *np) 386 { 387 const char *clk_name = np->full_name; 388 void __iomem *csr_reg; 389 struct resource res; 390 struct clk *clk; 391 u64 denom; 392 u32 flags = 0; 393 int rc; 394 395 /* Check if the entry is disabled */ 396 if (!of_device_is_available(np)) 397 return; 398 399 /* Parse the DTS register for resource */ 400 rc = of_address_to_resource(np, 0, &res); 401 if (rc != 0) { 402 pr_err("no DTS register for %pOF\n", np); 403 return; 404 } 405 csr_reg = of_iomap(np, 0); 406 if (!csr_reg) { 407 pr_err("Unable to map resource for %pOF\n", np); 408 return; 409 } 410 of_property_read_string(np, "clock-output-names", &clk_name); 411 412 denom = BIT(XGENE_CLK_PMD_WIDTH); 413 flags |= XGENE_CLK_PMD_SCALE_INVERTED; 414 415 clk = xgene_register_clk_pmd(NULL, clk_name, 416 of_clk_get_parent_name(np, 0), 0, 417 csr_reg, XGENE_CLK_PMD_SHIFT, 418 XGENE_CLK_PMD_WIDTH, denom, 419 flags, &clk_lock); 420 if (!IS_ERR(clk)) { 421 of_clk_add_provider(np, of_clk_src_simple_get, clk); 422 clk_register_clkdev(clk, clk_name, NULL); 423 pr_debug("Add %s clock\n", clk_name); 424 } else { 425 if (csr_reg) 426 iounmap(csr_reg); 427 } 428 } 429 430 /* IP Clock */ 431 struct xgene_dev_parameters { 432 void __iomem *csr_reg; /* CSR for IP clock */ 433 u32 reg_clk_offset; /* Offset to clock enable CSR */ 434 u32 reg_clk_mask; /* Mask bit for clock enable */ 435 u32 reg_csr_offset; /* Offset to CSR reset */ 436 u32 reg_csr_mask; /* Mask bit for disable CSR reset */ 437 void __iomem *divider_reg; /* CSR for divider */ 438 u32 reg_divider_offset; /* Offset to divider register */ 439 u32 reg_divider_shift; /* Bit shift to divider field */ 440 u32 reg_divider_width; /* Width of the bit to divider field */ 441 }; 442 443 struct xgene_clk { 444 struct clk_hw hw; 445 spinlock_t *lock; 446 struct xgene_dev_parameters param; 447 }; 448 449 #define to_xgene_clk(_hw) container_of(_hw, struct xgene_clk, hw) 450 451 static int xgene_clk_enable(struct clk_hw *hw) 452 { 453 struct xgene_clk *pclk = to_xgene_clk(hw); 454 unsigned long flags = 0; 455 u32 data; 456 457 if (pclk->lock) 458 spin_lock_irqsave(pclk->lock, flags); 459 460 if (pclk->param.csr_reg) { 461 pr_debug("%s clock enabled\n", clk_hw_get_name(hw)); 462 /* First enable the clock */ 463 data = xgene_clk_read(pclk->param.csr_reg + 464 pclk->param.reg_clk_offset); 465 data |= pclk->param.reg_clk_mask; 466 xgene_clk_write(data, pclk->param.csr_reg + 467 pclk->param.reg_clk_offset); 468 pr_debug("%s clk offset 0x%08X mask 0x%08X value 0x%08X\n", 469 clk_hw_get_name(hw), 470 pclk->param.reg_clk_offset, pclk->param.reg_clk_mask, 471 data); 472 473 /* Second enable the CSR */ 474 data = xgene_clk_read(pclk->param.csr_reg + 475 pclk->param.reg_csr_offset); 476 data &= ~pclk->param.reg_csr_mask; 477 xgene_clk_write(data, pclk->param.csr_reg + 478 pclk->param.reg_csr_offset); 479 pr_debug("%s csr offset 0x%08X mask 0x%08X value 0x%08X\n", 480 clk_hw_get_name(hw), 481 pclk->param.reg_csr_offset, pclk->param.reg_csr_mask, 482 data); 483 } 484 485 if (pclk->lock) 486 spin_unlock_irqrestore(pclk->lock, flags); 487 488 return 0; 489 } 490 491 static void xgene_clk_disable(struct clk_hw *hw) 492 { 493 struct xgene_clk *pclk = to_xgene_clk(hw); 494 unsigned long flags = 0; 495 u32 data; 496 497 if (pclk->lock) 498 spin_lock_irqsave(pclk->lock, flags); 499 500 if (pclk->param.csr_reg) { 501 pr_debug("%s clock disabled\n", clk_hw_get_name(hw)); 502 /* First put the CSR in reset */ 503 data = xgene_clk_read(pclk->param.csr_reg + 504 pclk->param.reg_csr_offset); 505 data |= pclk->param.reg_csr_mask; 506 xgene_clk_write(data, pclk->param.csr_reg + 507 pclk->param.reg_csr_offset); 508 509 /* Second disable the clock */ 510 data = xgene_clk_read(pclk->param.csr_reg + 511 pclk->param.reg_clk_offset); 512 data &= ~pclk->param.reg_clk_mask; 513 xgene_clk_write(data, pclk->param.csr_reg + 514 pclk->param.reg_clk_offset); 515 } 516 517 if (pclk->lock) 518 spin_unlock_irqrestore(pclk->lock, flags); 519 } 520 521 static int xgene_clk_is_enabled(struct clk_hw *hw) 522 { 523 struct xgene_clk *pclk = to_xgene_clk(hw); 524 u32 data = 0; 525 526 if (pclk->param.csr_reg) { 527 pr_debug("%s clock checking\n", clk_hw_get_name(hw)); 528 data = xgene_clk_read(pclk->param.csr_reg + 529 pclk->param.reg_clk_offset); 530 pr_debug("%s clock is %s\n", clk_hw_get_name(hw), 531 str_enabled_disabled(data & pclk->param.reg_clk_mask)); 532 } else { 533 return 1; 534 } 535 536 return data & pclk->param.reg_clk_mask ? 1 : 0; 537 } 538 539 static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw, 540 unsigned long parent_rate) 541 { 542 struct xgene_clk *pclk = to_xgene_clk(hw); 543 u32 data; 544 545 if (pclk->param.divider_reg) { 546 data = xgene_clk_read(pclk->param.divider_reg + 547 pclk->param.reg_divider_offset); 548 data >>= pclk->param.reg_divider_shift; 549 data &= (1 << pclk->param.reg_divider_width) - 1; 550 551 pr_debug("%s clock recalc rate %ld parent %ld\n", 552 clk_hw_get_name(hw), 553 parent_rate / data, parent_rate); 554 555 return parent_rate / data; 556 } else { 557 pr_debug("%s clock recalc rate %ld parent %ld\n", 558 clk_hw_get_name(hw), parent_rate, parent_rate); 559 return parent_rate; 560 } 561 } 562 563 static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate, 564 unsigned long parent_rate) 565 { 566 struct xgene_clk *pclk = to_xgene_clk(hw); 567 unsigned long flags = 0; 568 u32 data; 569 u32 divider; 570 u32 divider_save; 571 572 if (pclk->lock) 573 spin_lock_irqsave(pclk->lock, flags); 574 575 if (pclk->param.divider_reg) { 576 /* Let's compute the divider */ 577 if (rate > parent_rate) 578 rate = parent_rate; 579 divider_save = divider = parent_rate / rate; /* Rounded down */ 580 divider &= (1 << pclk->param.reg_divider_width) - 1; 581 divider <<= pclk->param.reg_divider_shift; 582 583 /* Set new divider */ 584 data = xgene_clk_read(pclk->param.divider_reg + 585 pclk->param.reg_divider_offset); 586 data &= ~(((1 << pclk->param.reg_divider_width) - 1) 587 << pclk->param.reg_divider_shift); 588 data |= divider; 589 xgene_clk_write(data, pclk->param.divider_reg + 590 pclk->param.reg_divider_offset); 591 pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw), 592 parent_rate / divider_save); 593 } else { 594 divider_save = 1; 595 } 596 597 if (pclk->lock) 598 spin_unlock_irqrestore(pclk->lock, flags); 599 600 return parent_rate / divider_save; 601 } 602 603 static int xgene_clk_determine_rate(struct clk_hw *hw, 604 struct clk_rate_request *req) 605 { 606 struct xgene_clk *pclk = to_xgene_clk(hw); 607 unsigned long parent_rate = req->best_parent_rate; 608 u32 divider; 609 610 if (pclk->param.divider_reg) { 611 /* Let's compute the divider */ 612 if (req->rate > parent_rate) 613 req->rate = parent_rate; 614 divider = parent_rate / req->rate; /* Rounded down */ 615 } else { 616 divider = 1; 617 } 618 619 req->rate = parent_rate / divider; 620 621 return 0; 622 } 623 624 static const struct clk_ops xgene_clk_ops = { 625 .enable = xgene_clk_enable, 626 .disable = xgene_clk_disable, 627 .is_enabled = xgene_clk_is_enabled, 628 .recalc_rate = xgene_clk_recalc_rate, 629 .set_rate = xgene_clk_set_rate, 630 .determine_rate = xgene_clk_determine_rate, 631 }; 632 633 static struct clk *xgene_register_clk(struct device *dev, 634 const char *name, const char *parent_name, 635 struct xgene_dev_parameters *parameters, spinlock_t *lock) 636 { 637 struct xgene_clk *apmclk; 638 struct clk *clk; 639 struct clk_init_data init; 640 int rc; 641 642 /* allocate the APM clock structure */ 643 apmclk = kzalloc_obj(*apmclk); 644 if (!apmclk) 645 return ERR_PTR(-ENOMEM); 646 647 init.name = name; 648 init.ops = &xgene_clk_ops; 649 init.flags = 0; 650 init.parent_names = parent_name ? &parent_name : NULL; 651 init.num_parents = parent_name ? 1 : 0; 652 653 apmclk->lock = lock; 654 apmclk->hw.init = &init; 655 apmclk->param = *parameters; 656 657 /* Register the clock */ 658 clk = clk_register(dev, &apmclk->hw); 659 if (IS_ERR(clk)) { 660 pr_err("%s: could not register clk %s\n", __func__, name); 661 kfree(apmclk); 662 return clk; 663 } 664 665 /* Register the clock for lookup */ 666 rc = clk_register_clkdev(clk, name, NULL); 667 if (rc != 0) { 668 pr_err("%s: could not register lookup clk %s\n", 669 __func__, name); 670 } 671 return clk; 672 } 673 674 static void __init xgene_devclk_init(struct device_node *np) 675 { 676 const char *clk_name = np->full_name; 677 struct clk *clk; 678 struct resource res; 679 int rc; 680 struct xgene_dev_parameters parameters; 681 int i; 682 683 /* Check if the entry is disabled */ 684 if (!of_device_is_available(np)) 685 return; 686 687 /* Parse the DTS register for resource */ 688 parameters.csr_reg = NULL; 689 parameters.divider_reg = NULL; 690 for (i = 0; i < 2; i++) { 691 void __iomem *map_res; 692 rc = of_address_to_resource(np, i, &res); 693 if (rc != 0) { 694 if (i == 0) { 695 pr_err("no DTS register for %pOF\n", np); 696 return; 697 } 698 break; 699 } 700 map_res = of_iomap(np, i); 701 if (!map_res) { 702 pr_err("Unable to map resource %d for %pOF\n", i, np); 703 goto err; 704 } 705 if (strcmp(res.name, "div-reg") == 0) 706 parameters.divider_reg = map_res; 707 else /* if (strcmp(res->name, "csr-reg") == 0) */ 708 parameters.csr_reg = map_res; 709 } 710 if (of_property_read_u32(np, "csr-offset", ¶meters.reg_csr_offset)) 711 parameters.reg_csr_offset = 0; 712 if (of_property_read_u32(np, "csr-mask", ¶meters.reg_csr_mask)) 713 parameters.reg_csr_mask = 0xF; 714 if (of_property_read_u32(np, "enable-offset", 715 ¶meters.reg_clk_offset)) 716 parameters.reg_clk_offset = 0x8; 717 if (of_property_read_u32(np, "enable-mask", ¶meters.reg_clk_mask)) 718 parameters.reg_clk_mask = 0xF; 719 if (of_property_read_u32(np, "divider-offset", 720 ¶meters.reg_divider_offset)) 721 parameters.reg_divider_offset = 0; 722 if (of_property_read_u32(np, "divider-width", 723 ¶meters.reg_divider_width)) 724 parameters.reg_divider_width = 0; 725 if (of_property_read_u32(np, "divider-shift", 726 ¶meters.reg_divider_shift)) 727 parameters.reg_divider_shift = 0; 728 of_property_read_string(np, "clock-output-names", &clk_name); 729 730 clk = xgene_register_clk(NULL, clk_name, 731 of_clk_get_parent_name(np, 0), ¶meters, &clk_lock); 732 if (IS_ERR(clk)) 733 goto err; 734 pr_debug("Add %s clock\n", clk_name); 735 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); 736 if (rc != 0) 737 pr_err("%s: could register provider clk %pOF\n", __func__, np); 738 739 return; 740 741 err: 742 if (parameters.csr_reg) 743 iounmap(parameters.csr_reg); 744 if (parameters.divider_reg) 745 iounmap(parameters.divider_reg); 746 } 747 748 CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init); 749 CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init); 750 CLK_OF_DECLARE(xgene_pmd_clock, "apm,xgene-pmd-clock", xgene_pmdclk_init); 751 CLK_OF_DECLARE(xgene_socpll_v2_clock, "apm,xgene-socpll-v2-clock", 752 xgene_socpllclk_init); 753 CLK_OF_DECLARE(xgene_pcppll_v2_clock, "apm,xgene-pcppll-v2-clock", 754 xgene_pcppllclk_init); 755 CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init); 756