1 /* 2 * WM831x clock control 3 * 4 * Copyright 2011-2 Wolfson Microelectronics PLC. 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 15 #include <linux/clk-provider.h> 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/slab.h> 19 #include <linux/platform_device.h> 20 #include <linux/mfd/wm831x/core.h> 21 22 struct wm831x_clk { 23 struct wm831x *wm831x; 24 struct clk_hw xtal_hw; 25 struct clk_hw fll_hw; 26 struct clk_hw clkout_hw; 27 bool xtal_ena; 28 }; 29 30 static int wm831x_xtal_is_prepared(struct clk_hw *hw) 31 { 32 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 33 xtal_hw); 34 35 return clkdata->xtal_ena; 36 } 37 38 static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw, 39 unsigned long parent_rate) 40 { 41 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 42 xtal_hw); 43 44 if (clkdata->xtal_ena) 45 return 32768; 46 else 47 return 0; 48 } 49 50 static const struct clk_ops wm831x_xtal_ops = { 51 .is_prepared = wm831x_xtal_is_prepared, 52 .recalc_rate = wm831x_xtal_recalc_rate, 53 }; 54 55 static struct clk_init_data wm831x_xtal_init = { 56 .name = "xtal", 57 .ops = &wm831x_xtal_ops, 58 }; 59 60 static const unsigned long wm831x_fll_auto_rates[] = { 61 2048000, 62 11289600, 63 12000000, 64 12288000, 65 19200000, 66 22579600, 67 24000000, 68 24576000, 69 }; 70 71 static int wm831x_fll_is_prepared(struct clk_hw *hw) 72 { 73 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 74 fll_hw); 75 struct wm831x *wm831x = clkdata->wm831x; 76 int ret; 77 78 ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1); 79 if (ret < 0) { 80 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n", 81 ret); 82 return true; 83 } 84 85 return (ret & WM831X_FLL_ENA) != 0; 86 } 87 88 static int wm831x_fll_prepare(struct clk_hw *hw) 89 { 90 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 91 fll_hw); 92 struct wm831x *wm831x = clkdata->wm831x; 93 int ret; 94 95 ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, 96 WM831X_FLL_ENA, WM831X_FLL_ENA); 97 if (ret != 0) 98 dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret); 99 100 /* wait 2-3 ms for new frequency taking effect */ 101 usleep_range(2000, 3000); 102 103 return ret; 104 } 105 106 static void wm831x_fll_unprepare(struct clk_hw *hw) 107 { 108 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 109 fll_hw); 110 struct wm831x *wm831x = clkdata->wm831x; 111 int ret; 112 113 ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0); 114 if (ret != 0) 115 dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret); 116 } 117 118 static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw, 119 unsigned long parent_rate) 120 { 121 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 122 fll_hw); 123 struct wm831x *wm831x = clkdata->wm831x; 124 int ret; 125 126 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2); 127 if (ret < 0) { 128 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n", 129 ret); 130 return 0; 131 } 132 133 if (ret & WM831X_FLL_AUTO) 134 return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK]; 135 136 dev_err(wm831x->dev, "FLL only supported in AUTO mode\n"); 137 138 return 0; 139 } 140 141 static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate, 142 unsigned long *unused) 143 { 144 int best = 0; 145 int i; 146 147 for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++) 148 if (abs(wm831x_fll_auto_rates[i] - rate) < 149 abs(wm831x_fll_auto_rates[best] - rate)) 150 best = i; 151 152 return wm831x_fll_auto_rates[best]; 153 } 154 155 static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate, 156 unsigned long parent_rate) 157 { 158 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 159 fll_hw); 160 struct wm831x *wm831x = clkdata->wm831x; 161 int i; 162 163 for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++) 164 if (wm831x_fll_auto_rates[i] == rate) 165 break; 166 if (i == ARRAY_SIZE(wm831x_fll_auto_rates)) 167 return -EINVAL; 168 169 if (wm831x_fll_is_prepared(hw)) 170 return -EPERM; 171 172 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2, 173 WM831X_FLL_AUTO_FREQ_MASK, i); 174 } 175 176 static const char *wm831x_fll_parents[] = { 177 "xtal", 178 "clkin", 179 }; 180 181 static u8 wm831x_fll_get_parent(struct clk_hw *hw) 182 { 183 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 184 fll_hw); 185 struct wm831x *wm831x = clkdata->wm831x; 186 int ret; 187 188 /* AUTO mode is always clocked from the crystal */ 189 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2); 190 if (ret < 0) { 191 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n", 192 ret); 193 return 0; 194 } 195 196 if (ret & WM831X_FLL_AUTO) 197 return 0; 198 199 ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5); 200 if (ret < 0) { 201 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n", 202 ret); 203 return 0; 204 } 205 206 switch (ret & WM831X_FLL_CLK_SRC_MASK) { 207 case 0: 208 return 0; 209 case 1: 210 return 1; 211 default: 212 dev_err(wm831x->dev, "Unsupported FLL clock source %d\n", 213 ret & WM831X_FLL_CLK_SRC_MASK); 214 return 0; 215 } 216 } 217 218 static const struct clk_ops wm831x_fll_ops = { 219 .is_prepared = wm831x_fll_is_prepared, 220 .prepare = wm831x_fll_prepare, 221 .unprepare = wm831x_fll_unprepare, 222 .round_rate = wm831x_fll_round_rate, 223 .recalc_rate = wm831x_fll_recalc_rate, 224 .set_rate = wm831x_fll_set_rate, 225 .get_parent = wm831x_fll_get_parent, 226 }; 227 228 static struct clk_init_data wm831x_fll_init = { 229 .name = "fll", 230 .ops = &wm831x_fll_ops, 231 .parent_names = wm831x_fll_parents, 232 .num_parents = ARRAY_SIZE(wm831x_fll_parents), 233 .flags = CLK_SET_RATE_GATE, 234 }; 235 236 static int wm831x_clkout_is_prepared(struct clk_hw *hw) 237 { 238 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 239 clkout_hw); 240 struct wm831x *wm831x = clkdata->wm831x; 241 int ret; 242 243 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1); 244 if (ret < 0) { 245 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n", 246 ret); 247 return false; 248 } 249 250 return (ret & WM831X_CLKOUT_ENA) != 0; 251 } 252 253 static int wm831x_clkout_prepare(struct clk_hw *hw) 254 { 255 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 256 clkout_hw); 257 struct wm831x *wm831x = clkdata->wm831x; 258 int ret; 259 260 ret = wm831x_reg_unlock(wm831x); 261 if (ret != 0) { 262 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret); 263 return ret; 264 } 265 266 ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1, 267 WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA); 268 if (ret != 0) 269 dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret); 270 271 wm831x_reg_lock(wm831x); 272 273 return ret; 274 } 275 276 static void wm831x_clkout_unprepare(struct clk_hw *hw) 277 { 278 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 279 clkout_hw); 280 struct wm831x *wm831x = clkdata->wm831x; 281 int ret; 282 283 ret = wm831x_reg_unlock(wm831x); 284 if (ret != 0) { 285 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret); 286 return; 287 } 288 289 ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1, 290 WM831X_CLKOUT_ENA, 0); 291 if (ret != 0) 292 dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret); 293 294 wm831x_reg_lock(wm831x); 295 } 296 297 static const char *wm831x_clkout_parents[] = { 298 "fll", 299 "xtal", 300 }; 301 302 static u8 wm831x_clkout_get_parent(struct clk_hw *hw) 303 { 304 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 305 clkout_hw); 306 struct wm831x *wm831x = clkdata->wm831x; 307 int ret; 308 309 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1); 310 if (ret < 0) { 311 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n", 312 ret); 313 return 0; 314 } 315 316 if (ret & WM831X_CLKOUT_SRC) 317 return 1; 318 else 319 return 0; 320 } 321 322 static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent) 323 { 324 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 325 clkout_hw); 326 struct wm831x *wm831x = clkdata->wm831x; 327 328 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1, 329 WM831X_CLKOUT_SRC, 330 parent << WM831X_CLKOUT_SRC_SHIFT); 331 } 332 333 static const struct clk_ops wm831x_clkout_ops = { 334 .is_prepared = wm831x_clkout_is_prepared, 335 .prepare = wm831x_clkout_prepare, 336 .unprepare = wm831x_clkout_unprepare, 337 .get_parent = wm831x_clkout_get_parent, 338 .set_parent = wm831x_clkout_set_parent, 339 }; 340 341 static struct clk_init_data wm831x_clkout_init = { 342 .name = "clkout", 343 .ops = &wm831x_clkout_ops, 344 .parent_names = wm831x_clkout_parents, 345 .num_parents = ARRAY_SIZE(wm831x_clkout_parents), 346 .flags = CLK_SET_RATE_PARENT, 347 }; 348 349 static int wm831x_clk_probe(struct platform_device *pdev) 350 { 351 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent); 352 struct wm831x_clk *clkdata; 353 int ret; 354 355 clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL); 356 if (!clkdata) 357 return -ENOMEM; 358 359 clkdata->wm831x = wm831x; 360 361 /* XTAL_ENA can only be set via OTP/InstantConfig so just read once */ 362 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2); 363 if (ret < 0) { 364 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n", 365 ret); 366 return ret; 367 } 368 clkdata->xtal_ena = ret & WM831X_XTAL_ENA; 369 370 clkdata->xtal_hw.init = &wm831x_xtal_init; 371 ret = devm_clk_hw_register(&pdev->dev, &clkdata->xtal_hw); 372 if (ret) 373 return ret; 374 375 clkdata->fll_hw.init = &wm831x_fll_init; 376 ret = devm_clk_hw_register(&pdev->dev, &clkdata->fll_hw); 377 if (ret) 378 return ret; 379 380 clkdata->clkout_hw.init = &wm831x_clkout_init; 381 ret = devm_clk_hw_register(&pdev->dev, &clkdata->clkout_hw); 382 if (ret) 383 return ret; 384 385 platform_set_drvdata(pdev, clkdata); 386 387 return 0; 388 } 389 390 static struct platform_driver wm831x_clk_driver = { 391 .probe = wm831x_clk_probe, 392 .driver = { 393 .name = "wm831x-clk", 394 }, 395 }; 396 397 module_platform_driver(wm831x_clk_driver); 398 399 /* Module information */ 400 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 401 MODULE_DESCRIPTION("WM831x clock driver"); 402 MODULE_LICENSE("GPL"); 403 MODULE_ALIAS("platform:wm831x-clk"); 404