1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Renesas Versaclock 3 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/i2c.h> 10 #include <linux/limits.h> 11 #include <linux/module.h> 12 #include <linux/regmap.h> 13 14 #define NUM_CONFIG_REGISTERS 37 15 16 #define VC3_GENERAL_CTR 0x0 17 #define VC3_GENERAL_CTR_DIV1_SRC_SEL BIT(3) 18 #define VC3_GENERAL_CTR_PLL3_REFIN_SEL BIT(2) 19 20 #define VC3_PLL3_M_DIVIDER 0x3 21 #define VC3_PLL3_M_DIV1 BIT(7) 22 #define VC3_PLL3_M_DIV2 BIT(6) 23 #define VC3_PLL3_M_DIV(n) ((n) & GENMASK(5, 0)) 24 25 #define VC3_PLL3_N_DIVIDER 0x4 26 #define VC3_PLL3_LOOP_FILTER_N_DIV_MSB 0x5 27 28 #define VC3_PLL3_CHARGE_PUMP_CTRL 0x6 29 #define VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL BIT(7) 30 31 #define VC3_PLL1_CTRL_OUTDIV5 0x7 32 #define VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER BIT(7) 33 34 #define VC3_PLL1_M_DIVIDER 0x8 35 #define VC3_PLL1_M_DIV1 BIT(7) 36 #define VC3_PLL1_M_DIV2 BIT(6) 37 #define VC3_PLL1_M_DIV(n) ((n) & GENMASK(5, 0)) 38 39 #define VC3_PLL1_VCO_N_DIVIDER 0x9 40 #define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0xa 41 42 #define VC3_OUT_DIV1_DIV2_CTRL 0xf 43 44 #define VC3_PLL2_FB_INT_DIV_MSB 0x10 45 #define VC3_PLL2_FB_INT_DIV_LSB 0x11 46 #define VC3_PLL2_FB_FRC_DIV_MSB 0x12 47 #define VC3_PLL2_FB_FRC_DIV_LSB 0x13 48 49 #define VC3_PLL2_M_DIVIDER 0x1a 50 #define VC3_PLL2_MDIV_DOUBLER BIT(7) 51 #define VC3_PLL2_M_DIV1 BIT(6) 52 #define VC3_PLL2_M_DIV2 BIT(5) 53 #define VC3_PLL2_M_DIV(n) ((n) & GENMASK(4, 0)) 54 55 #define VC3_OUT_DIV3_DIV4_CTRL 0x1b 56 57 #define VC3_PLL_OP_CTRL 0x1c 58 #define VC3_PLL_OP_CTRL_PLL2_REFIN_SEL 6 59 60 #define VC3_OUTPUT_CTR 0x1d 61 #define VC3_OUTPUT_CTR_DIV4_SRC_SEL BIT(3) 62 63 #define VC3_SE2_CTRL_REG0 0x1f 64 #define VC3_SE2_CTRL_REG0_SE2_CLK_SEL BIT(6) 65 66 #define VC3_SE3_DIFF1_CTRL_REG 0x21 67 #define VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL BIT(6) 68 69 #define VC3_DIFF1_CTRL_REG 0x22 70 #define VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL BIT(7) 71 72 #define VC3_DIFF2_CTRL_REG 0x23 73 #define VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL BIT(7) 74 75 #define VC3_SE1_DIV4_CTRL 0x24 76 #define VC3_SE1_DIV4_CTRL_SE1_CLK_SEL BIT(3) 77 78 #define VC3_PLL1_VCO_MIN 300000000UL 79 #define VC3_PLL1_VCO_MAX 600000000UL 80 81 #define VC3_PLL3_VCO_MIN 300000000UL 82 #define VC3_PLL3_VCO_MAX 800000000UL 83 84 #define VC3_2_POW_16 (U16_MAX + 1) 85 #define VC3_DIV_MASK(width) ((1 << (width)) - 1) 86 87 enum vc3_pfd_mux { 88 VC3_PFD2_MUX, 89 VC3_PFD3_MUX, 90 }; 91 92 enum vc3_pfd { 93 VC3_PFD1, 94 VC3_PFD2, 95 VC3_PFD3, 96 }; 97 98 enum vc3_pll { 99 VC3_PLL1, 100 VC3_PLL2, 101 VC3_PLL3, 102 }; 103 104 enum vc3_div_mux { 105 VC3_DIV1_MUX, 106 VC3_DIV3_MUX, 107 VC3_DIV4_MUX, 108 }; 109 110 enum vc3_div { 111 VC3_DIV1, 112 VC3_DIV2, 113 VC3_DIV3, 114 VC3_DIV4, 115 VC3_DIV5, 116 }; 117 118 enum vc3_clk { 119 VC3_REF, 120 VC3_SE1, 121 VC3_SE2, 122 VC3_SE3, 123 VC3_DIFF1, 124 VC3_DIFF2, 125 }; 126 127 enum vc3_clk_mux { 128 VC3_SE1_MUX = VC3_SE1 - 1, 129 VC3_SE2_MUX = VC3_SE2 - 1, 130 VC3_SE3_MUX = VC3_SE3 - 1, 131 VC3_DIFF1_MUX = VC3_DIFF1 - 1, 132 VC3_DIFF2_MUX = VC3_DIFF2 - 1, 133 }; 134 135 struct vc3_clk_data { 136 u8 offs; 137 u8 bitmsk; 138 }; 139 140 struct vc3_pfd_data { 141 u8 num; 142 u8 offs; 143 u8 mdiv1_bitmsk; 144 u8 mdiv2_bitmsk; 145 }; 146 147 struct vc3_vco { 148 unsigned long min; 149 unsigned long max; 150 }; 151 152 struct vc3_pll_data { 153 struct vc3_vco vco; 154 u8 num; 155 u8 int_div_msb_offs; 156 u8 int_div_lsb_offs; 157 }; 158 159 struct vc3_div_data { 160 const struct clk_div_table *table; 161 u8 offs; 162 u8 shift; 163 u8 width; 164 u8 flags; 165 }; 166 167 struct vc3_hw_data { 168 struct clk_hw hw; 169 struct regmap *regmap; 170 void *data; 171 172 u32 div_int; 173 u32 div_frc; 174 }; 175 176 struct vc3_hw_cfg { 177 struct vc3_vco pll2_vco; 178 u32 se2_clk_sel_msk; 179 }; 180 181 static const struct clk_div_table div1_divs[] = { 182 { .val = 0, .div = 1, }, { .val = 1, .div = 4, }, 183 { .val = 2, .div = 5, }, { .val = 3, .div = 6, }, 184 { .val = 4, .div = 2, }, { .val = 5, .div = 8, }, 185 { .val = 6, .div = 10, }, { .val = 7, .div = 12, }, 186 { .val = 8, .div = 4, }, { .val = 9, .div = 16, }, 187 { .val = 10, .div = 20, }, { .val = 11, .div = 24, }, 188 { .val = 12, .div = 8, }, { .val = 13, .div = 32, }, 189 { .val = 14, .div = 40, }, { .val = 15, .div = 48, }, 190 {} 191 }; 192 193 static const struct clk_div_table div245_divs[] = { 194 { .val = 0, .div = 1, }, { .val = 1, .div = 3, }, 195 { .val = 2, .div = 5, }, { .val = 3, .div = 10, }, 196 { .val = 4, .div = 2, }, { .val = 5, .div = 6, }, 197 { .val = 6, .div = 10, }, { .val = 7, .div = 20, }, 198 { .val = 8, .div = 4, }, { .val = 9, .div = 12, }, 199 { .val = 10, .div = 20, }, { .val = 11, .div = 40, }, 200 { .val = 12, .div = 5, }, { .val = 13, .div = 15, }, 201 { .val = 14, .div = 25, }, { .val = 15, .div = 50, }, 202 {} 203 }; 204 205 static const struct clk_div_table div3_divs[] = { 206 { .val = 0, .div = 1, }, { .val = 1, .div = 3, }, 207 { .val = 2, .div = 5, }, { .val = 3, .div = 10, }, 208 { .val = 4, .div = 2, }, { .val = 5, .div = 6, }, 209 { .val = 6, .div = 10, }, { .val = 7, .div = 20, }, 210 { .val = 8, .div = 4, }, { .val = 9, .div = 12, }, 211 { .val = 10, .div = 20, }, { .val = 11, .div = 40, }, 212 { .val = 12, .div = 8, }, { .val = 13, .div = 24, }, 213 { .val = 14, .div = 40, }, { .val = 15, .div = 80, }, 214 {} 215 }; 216 217 static struct clk_hw *clk_out[6]; 218 219 static u8 vc3_pfd_mux_get_parent(struct clk_hw *hw) 220 { 221 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 222 const struct vc3_clk_data *pfd_mux = vc3->data; 223 u32 src; 224 225 regmap_read(vc3->regmap, pfd_mux->offs, &src); 226 227 return !!(src & pfd_mux->bitmsk); 228 } 229 230 static int vc3_pfd_mux_set_parent(struct clk_hw *hw, u8 index) 231 { 232 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 233 const struct vc3_clk_data *pfd_mux = vc3->data; 234 235 return regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk, 236 index ? pfd_mux->bitmsk : 0); 237 } 238 239 static const struct clk_ops vc3_pfd_mux_ops = { 240 .determine_rate = clk_hw_determine_rate_no_reparent, 241 .set_parent = vc3_pfd_mux_set_parent, 242 .get_parent = vc3_pfd_mux_get_parent, 243 }; 244 245 static unsigned long vc3_pfd_recalc_rate(struct clk_hw *hw, 246 unsigned long parent_rate) 247 { 248 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 249 const struct vc3_pfd_data *pfd = vc3->data; 250 unsigned int prediv, premul; 251 unsigned long rate; 252 u8 mdiv; 253 254 regmap_read(vc3->regmap, pfd->offs, &prediv); 255 if (pfd->num == VC3_PFD1) { 256 /* The bypass_prediv is set, PLL fed from Ref_in directly. */ 257 if (prediv & pfd->mdiv1_bitmsk) { 258 /* check doubler is set or not */ 259 regmap_read(vc3->regmap, VC3_PLL1_CTRL_OUTDIV5, &premul); 260 if (premul & VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER) 261 parent_rate *= 2; 262 return parent_rate; 263 } 264 mdiv = VC3_PLL1_M_DIV(prediv); 265 } else if (pfd->num == VC3_PFD2) { 266 /* The bypass_prediv is set, PLL fed from Ref_in directly. */ 267 if (prediv & pfd->mdiv1_bitmsk) { 268 regmap_read(vc3->regmap, VC3_PLL2_M_DIVIDER, &premul); 269 /* check doubler is set or not */ 270 if (premul & VC3_PLL2_MDIV_DOUBLER) 271 parent_rate *= 2; 272 return parent_rate; 273 } 274 275 mdiv = VC3_PLL2_M_DIV(prediv); 276 } else { 277 /* The bypass_prediv is set, PLL fed from Ref_in directly. */ 278 if (prediv & pfd->mdiv1_bitmsk) 279 return parent_rate; 280 281 mdiv = VC3_PLL3_M_DIV(prediv); 282 } 283 284 if (prediv & pfd->mdiv2_bitmsk) 285 rate = parent_rate / 2; 286 else 287 rate = parent_rate / mdiv; 288 289 return rate; 290 } 291 292 static int vc3_pfd_determine_rate(struct clk_hw *hw, 293 struct clk_rate_request *req) 294 { 295 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 296 const struct vc3_pfd_data *pfd = vc3->data; 297 unsigned long idiv; 298 299 /* PLL cannot operate with input clock above 50 MHz. */ 300 if (req->rate > 50000000) 301 return -EINVAL; 302 303 /* CLKIN within range of PLL input, feed directly to PLL. */ 304 if (req->best_parent_rate <= 50000000) { 305 req->rate = req->best_parent_rate; 306 307 return 0; 308 } 309 310 idiv = DIV_ROUND_UP(req->best_parent_rate, req->rate); 311 if (pfd->num == VC3_PFD1 || pfd->num == VC3_PFD3) { 312 if (idiv > 63) 313 return -EINVAL; 314 } else { 315 if (idiv > 31) 316 return -EINVAL; 317 } 318 319 req->rate = req->best_parent_rate / idiv; 320 321 return 0; 322 } 323 324 static int vc3_pfd_set_rate(struct clk_hw *hw, unsigned long rate, 325 unsigned long parent_rate) 326 { 327 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 328 const struct vc3_pfd_data *pfd = vc3->data; 329 unsigned long idiv; 330 u8 div; 331 332 /* CLKIN within range of PLL input, feed directly to PLL. */ 333 if (parent_rate <= 50000000) { 334 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk, 335 pfd->mdiv1_bitmsk); 336 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk, 0); 337 return 0; 338 } 339 340 idiv = DIV_ROUND_UP(parent_rate, rate); 341 /* We have dedicated div-2 predivider. */ 342 if (idiv == 2) { 343 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk, 344 pfd->mdiv2_bitmsk); 345 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk, 0); 346 } else { 347 if (pfd->num == VC3_PFD1) 348 div = VC3_PLL1_M_DIV(idiv); 349 else if (pfd->num == VC3_PFD2) 350 div = VC3_PLL2_M_DIV(idiv); 351 else 352 div = VC3_PLL3_M_DIV(idiv); 353 354 regmap_write(vc3->regmap, pfd->offs, div); 355 } 356 357 return 0; 358 } 359 360 static const struct clk_ops vc3_pfd_ops = { 361 .recalc_rate = vc3_pfd_recalc_rate, 362 .determine_rate = vc3_pfd_determine_rate, 363 .set_rate = vc3_pfd_set_rate, 364 }; 365 366 static unsigned long vc3_pll_recalc_rate(struct clk_hw *hw, 367 unsigned long parent_rate) 368 { 369 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 370 const struct vc3_pll_data *pll = vc3->data; 371 u32 div_int, div_frc, val; 372 unsigned long rate; 373 374 regmap_read(vc3->regmap, pll->int_div_msb_offs, &val); 375 div_int = (val & GENMASK(2, 0)) << 8; 376 regmap_read(vc3->regmap, pll->int_div_lsb_offs, &val); 377 div_int |= val; 378 379 if (pll->num == VC3_PLL2) { 380 regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB, &val); 381 div_frc = val << 8; 382 regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB, &val); 383 div_frc |= val; 384 rate = (parent_rate * 385 (div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16); 386 } else { 387 rate = parent_rate * div_int; 388 } 389 390 return rate; 391 } 392 393 static int vc3_pll_determine_rate(struct clk_hw *hw, 394 struct clk_rate_request *req) 395 { 396 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 397 const struct vc3_pll_data *pll = vc3->data; 398 u64 div_frc; 399 400 if (req->rate < pll->vco.min) 401 req->rate = pll->vco.min; 402 if (req->rate > pll->vco.max) 403 req->rate = pll->vco.max; 404 405 vc3->div_int = req->rate / req->best_parent_rate; 406 407 if (pll->num == VC3_PLL2) { 408 if (vc3->div_int > 0x7ff) 409 req->rate = req->best_parent_rate * 0x7ff; 410 411 /* Determine best fractional part, which is 16 bit wide */ 412 div_frc = req->rate % req->best_parent_rate; 413 div_frc *= BIT(16) - 1; 414 415 vc3->div_frc = min_t(u64, 416 div64_ul(div_frc, req->best_parent_rate), 417 U16_MAX); 418 req->rate = (req->best_parent_rate * 419 (vc3->div_int * VC3_2_POW_16 + vc3->div_frc) / VC3_2_POW_16); 420 } else { 421 req->rate = req->best_parent_rate * vc3->div_int; 422 } 423 424 return 0; 425 } 426 427 static int vc3_pll_set_rate(struct clk_hw *hw, unsigned long rate, 428 unsigned long parent_rate) 429 { 430 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 431 const struct vc3_pll_data *pll = vc3->data; 432 u32 val; 433 434 regmap_read(vc3->regmap, pll->int_div_msb_offs, &val); 435 val = (val & 0xf8) | ((vc3->div_int >> 8) & 0x7); 436 regmap_write(vc3->regmap, pll->int_div_msb_offs, val); 437 regmap_write(vc3->regmap, pll->int_div_lsb_offs, vc3->div_int & 0xff); 438 439 if (pll->num == VC3_PLL2) { 440 regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB, 441 vc3->div_frc >> 8); 442 regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB, 443 vc3->div_frc & 0xff); 444 } 445 446 return 0; 447 } 448 449 static const struct clk_ops vc3_pll_ops = { 450 .recalc_rate = vc3_pll_recalc_rate, 451 .determine_rate = vc3_pll_determine_rate, 452 .set_rate = vc3_pll_set_rate, 453 }; 454 455 static u8 vc3_div_mux_get_parent(struct clk_hw *hw) 456 { 457 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 458 const struct vc3_clk_data *div_mux = vc3->data; 459 u32 src; 460 461 regmap_read(vc3->regmap, div_mux->offs, &src); 462 463 return !!(src & div_mux->bitmsk); 464 } 465 466 static int vc3_div_mux_set_parent(struct clk_hw *hw, u8 index) 467 { 468 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 469 const struct vc3_clk_data *div_mux = vc3->data; 470 471 return regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk, 472 index ? div_mux->bitmsk : 0); 473 } 474 475 static const struct clk_ops vc3_div_mux_ops = { 476 .determine_rate = clk_hw_determine_rate_no_reparent, 477 .set_parent = vc3_div_mux_set_parent, 478 .get_parent = vc3_div_mux_get_parent, 479 }; 480 481 static unsigned int vc3_get_div(const struct clk_div_table *table, 482 unsigned int val, unsigned long flag) 483 { 484 const struct clk_div_table *clkt; 485 486 for (clkt = table; clkt->div; clkt++) 487 if (clkt->val == val) 488 return clkt->div; 489 490 return 1; 491 } 492 493 static unsigned long vc3_div_recalc_rate(struct clk_hw *hw, 494 unsigned long parent_rate) 495 { 496 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 497 const struct vc3_div_data *div_data = vc3->data; 498 unsigned int val; 499 500 regmap_read(vc3->regmap, div_data->offs, &val); 501 val >>= div_data->shift; 502 val &= VC3_DIV_MASK(div_data->width); 503 504 return divider_recalc_rate(hw, parent_rate, val, div_data->table, 505 div_data->flags, div_data->width); 506 } 507 508 static int vc3_div_determine_rate(struct clk_hw *hw, 509 struct clk_rate_request *req) 510 { 511 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 512 const struct vc3_div_data *div_data = vc3->data; 513 unsigned int bestdiv; 514 515 /* if read only, just return current value */ 516 if (div_data->flags & CLK_DIVIDER_READ_ONLY) { 517 regmap_read(vc3->regmap, div_data->offs, &bestdiv); 518 bestdiv >>= div_data->shift; 519 bestdiv &= VC3_DIV_MASK(div_data->width); 520 bestdiv = vc3_get_div(div_data->table, bestdiv, div_data->flags); 521 req->rate = DIV_ROUND_UP(req->best_parent_rate, bestdiv); 522 523 return 0; 524 } 525 526 req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, 527 div_data->table, 528 div_data->width, div_data->flags); 529 530 return 0; 531 } 532 533 static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate, 534 unsigned long parent_rate) 535 { 536 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 537 const struct vc3_div_data *div_data = vc3->data; 538 unsigned int value; 539 540 value = divider_get_val(rate, parent_rate, div_data->table, 541 div_data->width, div_data->flags); 542 return regmap_update_bits(vc3->regmap, div_data->offs, 543 VC3_DIV_MASK(div_data->width) << div_data->shift, 544 value << div_data->shift); 545 } 546 547 static const struct clk_ops vc3_div_ops = { 548 .recalc_rate = vc3_div_recalc_rate, 549 .determine_rate = vc3_div_determine_rate, 550 .set_rate = vc3_div_set_rate, 551 }; 552 553 static int vc3_clk_mux_determine_rate(struct clk_hw *hw, 554 struct clk_rate_request *req) 555 { 556 int frc; 557 558 if (clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT)) { 559 /* The below check is equivalent to (best_parent_rate/rate) */ 560 if (req->best_parent_rate >= req->rate) { 561 frc = DIV_ROUND_CLOSEST_ULL(req->best_parent_rate, 562 req->rate); 563 req->rate *= frc; 564 return clk_mux_determine_rate_flags(hw, req, 565 CLK_SET_RATE_PARENT); 566 } 567 } 568 569 return 0; 570 } 571 572 static u8 vc3_clk_mux_get_parent(struct clk_hw *hw) 573 { 574 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 575 const struct vc3_clk_data *clk_mux = vc3->data; 576 u32 val; 577 578 regmap_read(vc3->regmap, clk_mux->offs, &val); 579 580 return !!(val & clk_mux->bitmsk); 581 } 582 583 static int vc3_clk_mux_set_parent(struct clk_hw *hw, u8 index) 584 { 585 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); 586 const struct vc3_clk_data *clk_mux = vc3->data; 587 588 return regmap_update_bits(vc3->regmap, clk_mux->offs, clk_mux->bitmsk, 589 index ? clk_mux->bitmsk : 0); 590 } 591 592 static const struct clk_ops vc3_clk_mux_ops = { 593 .determine_rate = vc3_clk_mux_determine_rate, 594 .set_parent = vc3_clk_mux_set_parent, 595 .get_parent = vc3_clk_mux_get_parent, 596 }; 597 598 static const struct regmap_config vc3_regmap_config = { 599 .reg_bits = 8, 600 .val_bits = 8, 601 .cache_type = REGCACHE_MAPLE, 602 .max_register = 0x24, 603 }; 604 605 static struct vc3_hw_data clk_div[5]; 606 607 static const struct clk_parent_data pfd_mux_parent_data[] = { 608 { .index = 0, }, 609 { .hw = &clk_div[VC3_DIV2].hw } 610 }; 611 612 static struct vc3_hw_data clk_pfd_mux[] = { 613 [VC3_PFD2_MUX] = { 614 .data = &(struct vc3_clk_data) { 615 .offs = VC3_PLL_OP_CTRL, 616 .bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL) 617 }, 618 .hw.init = &(struct clk_init_data) { 619 .name = "pfd2_mux", 620 .ops = &vc3_pfd_mux_ops, 621 .parent_data = pfd_mux_parent_data, 622 .num_parents = 2, 623 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT 624 } 625 }, 626 [VC3_PFD3_MUX] = { 627 .data = &(struct vc3_clk_data) { 628 .offs = VC3_GENERAL_CTR, 629 .bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL) 630 }, 631 .hw.init = &(struct clk_init_data) { 632 .name = "pfd3_mux", 633 .ops = &vc3_pfd_mux_ops, 634 .parent_data = pfd_mux_parent_data, 635 .num_parents = 2, 636 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT 637 } 638 } 639 }; 640 641 static struct vc3_hw_data clk_pfd[] = { 642 [VC3_PFD1] = { 643 .data = &(struct vc3_pfd_data) { 644 .num = VC3_PFD1, 645 .offs = VC3_PLL1_M_DIVIDER, 646 .mdiv1_bitmsk = VC3_PLL1_M_DIV1, 647 .mdiv2_bitmsk = VC3_PLL1_M_DIV2 648 }, 649 .hw.init = &(struct clk_init_data) { 650 .name = "pfd1", 651 .ops = &vc3_pfd_ops, 652 .parent_data = &(const struct clk_parent_data) { 653 .index = 0 654 }, 655 .num_parents = 1, 656 .flags = CLK_SET_RATE_PARENT 657 } 658 }, 659 [VC3_PFD2] = { 660 .data = &(struct vc3_pfd_data) { 661 .num = VC3_PFD2, 662 .offs = VC3_PLL2_M_DIVIDER, 663 .mdiv1_bitmsk = VC3_PLL2_M_DIV1, 664 .mdiv2_bitmsk = VC3_PLL2_M_DIV2 665 }, 666 .hw.init = &(struct clk_init_data) { 667 .name = "pfd2", 668 .ops = &vc3_pfd_ops, 669 .parent_hws = (const struct clk_hw *[]) { 670 &clk_pfd_mux[VC3_PFD2_MUX].hw 671 }, 672 .num_parents = 1, 673 .flags = CLK_SET_RATE_PARENT 674 } 675 }, 676 [VC3_PFD3] = { 677 .data = &(struct vc3_pfd_data) { 678 .num = VC3_PFD3, 679 .offs = VC3_PLL3_M_DIVIDER, 680 .mdiv1_bitmsk = VC3_PLL3_M_DIV1, 681 .mdiv2_bitmsk = VC3_PLL3_M_DIV2 682 }, 683 .hw.init = &(struct clk_init_data) { 684 .name = "pfd3", 685 .ops = &vc3_pfd_ops, 686 .parent_hws = (const struct clk_hw *[]) { 687 &clk_pfd_mux[VC3_PFD3_MUX].hw 688 }, 689 .num_parents = 1, 690 .flags = CLK_SET_RATE_PARENT 691 } 692 } 693 }; 694 695 static struct vc3_hw_data clk_pll[] = { 696 [VC3_PLL1] = { 697 .data = &(struct vc3_pll_data) { 698 .num = VC3_PLL1, 699 .int_div_msb_offs = VC3_PLL1_LOOP_FILTER_N_DIV_MSB, 700 .int_div_lsb_offs = VC3_PLL1_VCO_N_DIVIDER, 701 .vco = { 702 .min = VC3_PLL1_VCO_MIN, 703 .max = VC3_PLL1_VCO_MAX 704 } 705 }, 706 .hw.init = &(struct clk_init_data) { 707 .name = "pll1", 708 .ops = &vc3_pll_ops, 709 .parent_hws = (const struct clk_hw *[]) { 710 &clk_pfd[VC3_PFD1].hw 711 }, 712 .num_parents = 1, 713 .flags = CLK_SET_RATE_PARENT 714 } 715 }, 716 [VC3_PLL2] = { 717 .data = &(struct vc3_pll_data) { 718 .num = VC3_PLL2, 719 .int_div_msb_offs = VC3_PLL2_FB_INT_DIV_MSB, 720 .int_div_lsb_offs = VC3_PLL2_FB_INT_DIV_LSB, 721 }, 722 .hw.init = &(struct clk_init_data) { 723 .name = "pll2", 724 .ops = &vc3_pll_ops, 725 .parent_hws = (const struct clk_hw *[]) { 726 &clk_pfd[VC3_PFD2].hw 727 }, 728 .num_parents = 1, 729 .flags = CLK_SET_RATE_PARENT 730 } 731 }, 732 [VC3_PLL3] = { 733 .data = &(struct vc3_pll_data) { 734 .num = VC3_PLL3, 735 .int_div_msb_offs = VC3_PLL3_LOOP_FILTER_N_DIV_MSB, 736 .int_div_lsb_offs = VC3_PLL3_N_DIVIDER, 737 .vco = { 738 .min = VC3_PLL3_VCO_MIN, 739 .max = VC3_PLL3_VCO_MAX 740 } 741 }, 742 .hw.init = &(struct clk_init_data) { 743 .name = "pll3", 744 .ops = &vc3_pll_ops, 745 .parent_hws = (const struct clk_hw *[]) { 746 &clk_pfd[VC3_PFD3].hw 747 }, 748 .num_parents = 1, 749 .flags = CLK_SET_RATE_PARENT 750 } 751 } 752 }; 753 754 static const struct clk_parent_data div_mux_parent_data[][2] = { 755 [VC3_DIV1_MUX] = { 756 { .hw = &clk_pll[VC3_PLL1].hw }, 757 { .index = 0 } 758 }, 759 [VC3_DIV3_MUX] = { 760 { .hw = &clk_pll[VC3_PLL2].hw }, 761 { .hw = &clk_pll[VC3_PLL3].hw } 762 }, 763 [VC3_DIV4_MUX] = { 764 { .hw = &clk_pll[VC3_PLL2].hw }, 765 { .index = 0 } 766 } 767 }; 768 769 static struct vc3_hw_data clk_div_mux[] = { 770 [VC3_DIV1_MUX] = { 771 .data = &(struct vc3_clk_data) { 772 .offs = VC3_GENERAL_CTR, 773 .bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL 774 }, 775 .hw.init = &(struct clk_init_data) { 776 .name = "div1_mux", 777 .ops = &vc3_div_mux_ops, 778 .parent_data = div_mux_parent_data[VC3_DIV1_MUX], 779 .num_parents = 2, 780 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT 781 } 782 }, 783 [VC3_DIV3_MUX] = { 784 .data = &(struct vc3_clk_data) { 785 .offs = VC3_PLL3_CHARGE_PUMP_CTRL, 786 .bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL 787 }, 788 .hw.init = &(struct clk_init_data) { 789 .name = "div3_mux", 790 .ops = &vc3_div_mux_ops, 791 .parent_data = div_mux_parent_data[VC3_DIV3_MUX], 792 .num_parents = 2, 793 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT 794 } 795 }, 796 [VC3_DIV4_MUX] = { 797 .data = &(struct vc3_clk_data) { 798 .offs = VC3_OUTPUT_CTR, 799 .bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL 800 }, 801 .hw.init = &(struct clk_init_data) { 802 .name = "div4_mux", 803 .ops = &vc3_div_mux_ops, 804 .parent_data = div_mux_parent_data[VC3_DIV4_MUX], 805 .num_parents = 2, 806 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT 807 } 808 } 809 }; 810 811 static struct vc3_hw_data clk_div[] = { 812 [VC3_DIV1] = { 813 .data = &(struct vc3_div_data) { 814 .offs = VC3_OUT_DIV1_DIV2_CTRL, 815 .table = div1_divs, 816 .shift = 4, 817 .width = 4, 818 .flags = CLK_DIVIDER_READ_ONLY 819 }, 820 .hw.init = &(struct clk_init_data) { 821 .name = "div1", 822 .ops = &vc3_div_ops, 823 .parent_hws = (const struct clk_hw *[]) { 824 &clk_div_mux[VC3_DIV1_MUX].hw 825 }, 826 .num_parents = 1, 827 .flags = CLK_SET_RATE_PARENT 828 } 829 }, 830 [VC3_DIV2] = { 831 .data = &(struct vc3_div_data) { 832 .offs = VC3_OUT_DIV1_DIV2_CTRL, 833 .table = div245_divs, 834 .shift = 0, 835 .width = 4, 836 .flags = CLK_DIVIDER_READ_ONLY 837 }, 838 .hw.init = &(struct clk_init_data) { 839 .name = "div2", 840 .ops = &vc3_div_ops, 841 .parent_hws = (const struct clk_hw *[]) { 842 &clk_pll[VC3_PLL1].hw 843 }, 844 .num_parents = 1, 845 .flags = CLK_SET_RATE_PARENT 846 } 847 }, 848 [VC3_DIV3] = { 849 .data = &(struct vc3_div_data) { 850 .offs = VC3_OUT_DIV3_DIV4_CTRL, 851 .table = div3_divs, 852 .shift = 4, 853 .width = 4, 854 .flags = CLK_DIVIDER_READ_ONLY 855 }, 856 .hw.init = &(struct clk_init_data) { 857 .name = "div3", 858 .ops = &vc3_div_ops, 859 .parent_hws = (const struct clk_hw *[]) { 860 &clk_div_mux[VC3_DIV3_MUX].hw 861 }, 862 .num_parents = 1, 863 .flags = CLK_SET_RATE_PARENT 864 } 865 }, 866 [VC3_DIV4] = { 867 .data = &(struct vc3_div_data) { 868 .offs = VC3_OUT_DIV3_DIV4_CTRL, 869 .table = div245_divs, 870 .shift = 0, 871 .width = 4, 872 .flags = CLK_DIVIDER_READ_ONLY 873 }, 874 .hw.init = &(struct clk_init_data) { 875 .name = "div4", 876 .ops = &vc3_div_ops, 877 .parent_hws = (const struct clk_hw *[]) { 878 &clk_div_mux[VC3_DIV4_MUX].hw 879 }, 880 .num_parents = 1, 881 .flags = CLK_SET_RATE_PARENT 882 } 883 }, 884 [VC3_DIV5] = { 885 .data = &(struct vc3_div_data) { 886 .offs = VC3_PLL1_CTRL_OUTDIV5, 887 .table = div245_divs, 888 .shift = 0, 889 .width = 4, 890 .flags = CLK_DIVIDER_READ_ONLY 891 }, 892 .hw.init = &(struct clk_init_data) { 893 .name = "div5", 894 .ops = &vc3_div_ops, 895 .parent_hws = (const struct clk_hw *[]) { 896 &clk_pll[VC3_PLL3].hw 897 }, 898 .num_parents = 1, 899 .flags = CLK_SET_RATE_PARENT 900 } 901 } 902 }; 903 904 static struct vc3_hw_data clk_mux[] = { 905 [VC3_SE1_MUX] = { 906 .data = &(struct vc3_clk_data) { 907 .offs = VC3_SE1_DIV4_CTRL, 908 .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL 909 }, 910 .hw.init = &(struct clk_init_data) { 911 .name = "se1_mux", 912 .ops = &vc3_clk_mux_ops, 913 .parent_hws = (const struct clk_hw *[]) { 914 &clk_div[VC3_DIV5].hw, 915 &clk_div[VC3_DIV4].hw 916 }, 917 .num_parents = 2, 918 .flags = CLK_SET_RATE_PARENT 919 } 920 }, 921 [VC3_SE2_MUX] = { 922 .data = &(struct vc3_clk_data) { 923 .offs = VC3_SE2_CTRL_REG0, 924 }, 925 .hw.init = &(struct clk_init_data) { 926 .name = "se2_mux", 927 .ops = &vc3_clk_mux_ops, 928 .parent_hws = (const struct clk_hw *[]) { 929 &clk_div[VC3_DIV5].hw, 930 &clk_div[VC3_DIV4].hw 931 }, 932 .num_parents = 2, 933 .flags = CLK_SET_RATE_PARENT 934 } 935 }, 936 [VC3_SE3_MUX] = { 937 .data = &(struct vc3_clk_data) { 938 .offs = VC3_SE3_DIFF1_CTRL_REG, 939 .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL 940 }, 941 .hw.init = &(struct clk_init_data) { 942 .name = "se3_mux", 943 .ops = &vc3_clk_mux_ops, 944 .parent_hws = (const struct clk_hw *[]) { 945 &clk_div[VC3_DIV2].hw, 946 &clk_div[VC3_DIV4].hw 947 }, 948 .num_parents = 2, 949 .flags = CLK_SET_RATE_PARENT 950 } 951 }, 952 [VC3_DIFF1_MUX] = { 953 .data = &(struct vc3_clk_data) { 954 .offs = VC3_DIFF1_CTRL_REG, 955 .bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL 956 }, 957 .hw.init = &(struct clk_init_data) { 958 .name = "diff1_mux", 959 .ops = &vc3_clk_mux_ops, 960 .parent_hws = (const struct clk_hw *[]) { 961 &clk_div[VC3_DIV1].hw, 962 &clk_div[VC3_DIV3].hw 963 }, 964 .num_parents = 2, 965 .flags = CLK_SET_RATE_PARENT 966 } 967 }, 968 [VC3_DIFF2_MUX] = { 969 .data = &(struct vc3_clk_data) { 970 .offs = VC3_DIFF2_CTRL_REG, 971 .bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL 972 }, 973 .hw.init = &(struct clk_init_data) { 974 .name = "diff2_mux", 975 .ops = &vc3_clk_mux_ops, 976 .parent_hws = (const struct clk_hw *[]) { 977 &clk_div[VC3_DIV1].hw, 978 &clk_div[VC3_DIV3].hw 979 }, 980 .num_parents = 2, 981 .flags = CLK_SET_RATE_PARENT 982 } 983 } 984 }; 985 986 static struct clk_hw *vc3_of_clk_get(struct of_phandle_args *clkspec, 987 void *data) 988 { 989 unsigned int idx = clkspec->args[0]; 990 struct clk_hw **clkout_hw = data; 991 992 if (idx >= ARRAY_SIZE(clk_out)) { 993 pr_err("invalid clk index %u for provider %pOF\n", idx, clkspec->np); 994 return ERR_PTR(-EINVAL); 995 } 996 997 return clkout_hw[idx]; 998 } 999 1000 static int vc3_probe(struct i2c_client *client) 1001 { 1002 struct device *dev = &client->dev; 1003 u8 settings[NUM_CONFIG_REGISTERS]; 1004 const struct vc3_hw_cfg *data; 1005 struct regmap *regmap; 1006 const char *name; 1007 int ret, i; 1008 1009 regmap = devm_regmap_init_i2c(client, &vc3_regmap_config); 1010 if (IS_ERR(regmap)) 1011 return dev_err_probe(dev, PTR_ERR(regmap), 1012 "failed to allocate register map\n"); 1013 1014 ret = of_property_read_u8_array(dev->of_node, "renesas,settings", 1015 settings, ARRAY_SIZE(settings)); 1016 if (!ret) { 1017 /* 1018 * A raw settings array was specified in the DT. Write the 1019 * settings to the device immediately. 1020 */ 1021 for (i = 0; i < NUM_CONFIG_REGISTERS; i++) { 1022 ret = regmap_write(regmap, i, settings[i]); 1023 if (ret) { 1024 dev_err(dev, "error writing to chip (%i)\n", ret); 1025 return ret; 1026 } 1027 } 1028 } else if (ret == -EOVERFLOW) { 1029 dev_err(&client->dev, "EOVERFLOW reg settings. ARRAY_SIZE: %zu\n", 1030 ARRAY_SIZE(settings)); 1031 return ret; 1032 } 1033 1034 /* Register pfd muxes */ 1035 for (i = 0; i < ARRAY_SIZE(clk_pfd_mux); i++) { 1036 clk_pfd_mux[i].regmap = regmap; 1037 ret = devm_clk_hw_register(dev, &clk_pfd_mux[i].hw); 1038 if (ret) 1039 return dev_err_probe(dev, ret, "%s failed\n", 1040 clk_pfd_mux[i].hw.init->name); 1041 } 1042 1043 /* Register pfd's */ 1044 for (i = 0; i < ARRAY_SIZE(clk_pfd); i++) { 1045 clk_pfd[i].regmap = regmap; 1046 ret = devm_clk_hw_register(dev, &clk_pfd[i].hw); 1047 if (ret) 1048 return dev_err_probe(dev, ret, "%s failed\n", 1049 clk_pfd[i].hw.init->name); 1050 } 1051 1052 data = i2c_get_match_data(client); 1053 1054 /* Register pll's */ 1055 for (i = 0; i < ARRAY_SIZE(clk_pll); i++) { 1056 clk_pll[i].regmap = regmap; 1057 if (i == VC3_PLL2) { 1058 struct vc3_pll_data *pll_data = clk_pll[i].data; 1059 1060 pll_data->vco = data->pll2_vco; 1061 } 1062 ret = devm_clk_hw_register(dev, &clk_pll[i].hw); 1063 if (ret) 1064 return dev_err_probe(dev, ret, "%s failed\n", 1065 clk_pll[i].hw.init->name); 1066 } 1067 1068 /* Register divider muxes */ 1069 for (i = 0; i < ARRAY_SIZE(clk_div_mux); i++) { 1070 clk_div_mux[i].regmap = regmap; 1071 ret = devm_clk_hw_register(dev, &clk_div_mux[i].hw); 1072 if (ret) 1073 return dev_err_probe(dev, ret, "%s failed\n", 1074 clk_div_mux[i].hw.init->name); 1075 } 1076 1077 /* Register dividers */ 1078 for (i = 0; i < ARRAY_SIZE(clk_div); i++) { 1079 clk_div[i].regmap = regmap; 1080 ret = devm_clk_hw_register(dev, &clk_div[i].hw); 1081 if (ret) 1082 return dev_err_probe(dev, ret, "%s failed\n", 1083 clk_div[i].hw.init->name); 1084 } 1085 1086 /* Register clk muxes */ 1087 for (i = 0; i < ARRAY_SIZE(clk_mux); i++) { 1088 clk_mux[i].regmap = regmap; 1089 if (i == VC3_SE2_MUX) { 1090 struct vc3_clk_data *clk_data = clk_mux[i].data; 1091 1092 clk_data->bitmsk = data->se2_clk_sel_msk; 1093 } 1094 ret = devm_clk_hw_register(dev, &clk_mux[i].hw); 1095 if (ret) 1096 return dev_err_probe(dev, ret, "%s failed\n", 1097 clk_mux[i].hw.init->name); 1098 } 1099 1100 /* Register clk outputs */ 1101 for (i = 0; i < ARRAY_SIZE(clk_out); i++) { 1102 switch (i) { 1103 case VC3_DIFF2: 1104 name = "diff2"; 1105 break; 1106 case VC3_DIFF1: 1107 name = "diff1"; 1108 break; 1109 case VC3_SE3: 1110 name = "se3"; 1111 break; 1112 case VC3_SE2: 1113 name = "se2"; 1114 break; 1115 case VC3_SE1: 1116 name = "se1"; 1117 break; 1118 case VC3_REF: 1119 name = "ref"; 1120 break; 1121 default: 1122 return dev_err_probe(dev, -EINVAL, "invalid clk output %d\n", i); 1123 } 1124 1125 if (i == VC3_REF) 1126 clk_out[i] = devm_clk_hw_register_fixed_factor_index(dev, 1127 name, 0, CLK_SET_RATE_PARENT, 1, 1); 1128 else 1129 clk_out[i] = devm_clk_hw_register_fixed_factor_parent_hw(dev, 1130 name, &clk_mux[i - 1].hw, CLK_SET_RATE_PARENT, 1, 1); 1131 1132 if (IS_ERR(clk_out[i])) 1133 return PTR_ERR(clk_out[i]); 1134 } 1135 1136 ret = devm_of_clk_add_hw_provider(dev, vc3_of_clk_get, clk_out); 1137 if (ret) 1138 return dev_err_probe(dev, ret, "unable to add clk provider\n"); 1139 1140 return ret; 1141 } 1142 1143 static const struct vc3_hw_cfg vc3_5p = { 1144 .pll2_vco = { .min = 400000000UL, .max = 1200000000UL }, 1145 .se2_clk_sel_msk = BIT(6), 1146 }; 1147 1148 static const struct vc3_hw_cfg vc3_5l = { 1149 .pll2_vco = { .min = 30000000UL, .max = 130000000UL }, 1150 .se2_clk_sel_msk = BIT(0), 1151 }; 1152 1153 static const struct of_device_id dev_ids[] = { 1154 { .compatible = "renesas,5p35023", .data = &vc3_5p }, 1155 { .compatible = "renesas,5l35023", .data = &vc3_5l }, 1156 { /* Sentinel */ } 1157 }; 1158 MODULE_DEVICE_TABLE(of, dev_ids); 1159 1160 static struct i2c_driver vc3_driver = { 1161 .driver = { 1162 .name = "vc3", 1163 .of_match_table = of_match_ptr(dev_ids), 1164 }, 1165 .probe = vc3_probe, 1166 }; 1167 module_i2c_driver(vc3_driver); 1168 1169 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 1170 MODULE_DESCRIPTION("Renesas VersaClock 3 driver"); 1171 MODULE_LICENSE("GPL"); 1172