1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Author: Daniel Thompson <daniel.thompson@linaro.org> 4 * 5 * Inspired by clk-asm9260.c . 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/clk-provider.h> 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/ioport.h> 14 #include <linux/slab.h> 15 #include <linux/spinlock.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/regmap.h> 19 #include <linux/mfd/syscon.h> 20 21 /* 22 * Include list of clocks which are not derived from system clock (SYSCLOCK) 23 * The index of these clocks is the secondary index of DT bindings 24 * 25 */ 26 #include <dt-bindings/clock/stm32fx-clock.h> 27 28 #define STM32F4_RCC_CR 0x00 29 #define STM32F4_RCC_PLLCFGR 0x04 30 #define STM32F4_RCC_CFGR 0x08 31 #define STM32F4_RCC_AHB1ENR 0x30 32 #define STM32F4_RCC_AHB2ENR 0x34 33 #define STM32F4_RCC_AHB3ENR 0x38 34 #define STM32F4_RCC_APB1ENR 0x40 35 #define STM32F4_RCC_APB2ENR 0x44 36 #define STM32F4_RCC_BDCR 0x70 37 #define STM32F4_RCC_CSR 0x74 38 #define STM32F4_RCC_SSCGR 0x80 39 #define STM32F4_RCC_PLLI2SCFGR 0x84 40 #define STM32F4_RCC_PLLSAICFGR 0x88 41 #define STM32F4_RCC_DCKCFGR 0x8c 42 #define STM32F7_RCC_DCKCFGR2 0x90 43 44 #define STM32F4_RCC_PLLCFGR_N_MASK GENMASK(14, 6) 45 46 #define STM32F4_RCC_SSCGR_SSCGEN BIT(31) 47 #define STM32F4_RCC_SSCGR_SPREADSEL BIT(30) 48 #define STM32F4_RCC_SSCGR_RESERVED_MASK GENMASK(29, 28) 49 #define STM32F4_RCC_SSCGR_INCSTEP_MASK GENMASK(27, 13) 50 #define STM32F4_RCC_SSCGR_MODPER_MASK GENMASK(12, 0) 51 52 #define NONE -1 53 #define NO_IDX NONE 54 #define NO_MUX NONE 55 #define NO_GATE NONE 56 57 struct stm32f4_gate_data { 58 u8 offset; 59 u8 bit_idx; 60 const char *name; 61 const char *parent_name; 62 unsigned long flags; 63 }; 64 65 static const struct stm32f4_gate_data stm32f429_gates[] __initconst = { 66 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" }, 67 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" }, 68 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" }, 69 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" }, 70 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" }, 71 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" }, 72 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" }, 73 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" }, 74 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" }, 75 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" }, 76 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" }, 77 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" }, 78 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" }, 79 { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" }, 80 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" }, 81 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" }, 82 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" }, 83 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" }, 84 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" }, 85 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" }, 86 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" }, 87 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" }, 88 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" }, 89 90 { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" }, 91 { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" }, 92 { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" }, 93 { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" }, 94 { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" }, 95 96 { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div", 97 CLK_IGNORE_UNUSED }, 98 99 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" }, 100 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" }, 101 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" }, 102 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" }, 103 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" }, 104 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" }, 105 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" }, 106 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" }, 107 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" }, 108 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" }, 109 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" }, 110 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" }, 111 { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" }, 112 { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" }, 113 { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" }, 114 { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" }, 115 { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" }, 116 { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" }, 117 { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" }, 118 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" }, 119 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" }, 120 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" }, 121 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" }, 122 { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" }, 123 { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" }, 124 125 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" }, 126 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" }, 127 { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" }, 128 { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" }, 129 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" }, 130 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" }, 131 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" }, 132 { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" }, 133 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" }, 134 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" }, 135 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" }, 136 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" }, 137 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" }, 138 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" }, 139 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, 140 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, 141 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, 142 }; 143 144 static const struct stm32f4_gate_data stm32f469_gates[] __initconst = { 145 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" }, 146 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" }, 147 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" }, 148 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" }, 149 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" }, 150 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" }, 151 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" }, 152 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" }, 153 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" }, 154 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" }, 155 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" }, 156 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" }, 157 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" }, 158 { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" }, 159 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" }, 160 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" }, 161 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" }, 162 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" }, 163 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" }, 164 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" }, 165 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" }, 166 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" }, 167 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" }, 168 169 { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" }, 170 { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" }, 171 { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" }, 172 { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" }, 173 { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" }, 174 175 { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div", 176 CLK_IGNORE_UNUSED }, 177 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div", 178 CLK_IGNORE_UNUSED }, 179 180 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" }, 181 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" }, 182 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" }, 183 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" }, 184 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" }, 185 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" }, 186 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" }, 187 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" }, 188 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" }, 189 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" }, 190 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" }, 191 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" }, 192 { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" }, 193 { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" }, 194 { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" }, 195 { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" }, 196 { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" }, 197 { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" }, 198 { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" }, 199 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" }, 200 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" }, 201 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" }, 202 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" }, 203 { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" }, 204 { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" }, 205 206 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" }, 207 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" }, 208 { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" }, 209 { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" }, 210 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" }, 211 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" }, 212 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" }, 213 { STM32F4_RCC_APB2ENR, 11, "sdio", "sdmux" }, 214 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" }, 215 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" }, 216 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" }, 217 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" }, 218 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" }, 219 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" }, 220 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, 221 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, 222 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, 223 }; 224 225 static const struct stm32f4_gate_data stm32f746_gates[] __initconst = { 226 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" }, 227 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" }, 228 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" }, 229 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" }, 230 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" }, 231 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" }, 232 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" }, 233 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" }, 234 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" }, 235 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" }, 236 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" }, 237 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" }, 238 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" }, 239 { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" }, 240 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" }, 241 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" }, 242 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" }, 243 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" }, 244 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" }, 245 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" }, 246 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" }, 247 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" }, 248 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" }, 249 250 { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" }, 251 { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" }, 252 { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" }, 253 { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" }, 254 { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" }, 255 256 { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div", 257 CLK_IGNORE_UNUSED }, 258 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div", 259 CLK_IGNORE_UNUSED }, 260 261 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" }, 262 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" }, 263 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" }, 264 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" }, 265 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" }, 266 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" }, 267 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" }, 268 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" }, 269 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" }, 270 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" }, 271 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" }, 272 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" }, 273 { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" }, 274 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" }, 275 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" }, 276 { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" }, 277 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" }, 278 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" }, 279 280 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" }, 281 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" }, 282 { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux" }, 283 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" }, 284 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" }, 285 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" }, 286 { STM32F4_RCC_APB2ENR, 11, "sdmmc", "sdmux" }, 287 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" }, 288 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" }, 289 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" }, 290 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" }, 291 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" }, 292 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" }, 293 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, 294 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, 295 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, 296 { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" }, 297 }; 298 299 static const struct stm32f4_gate_data stm32f769_gates[] __initconst = { 300 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" }, 301 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" }, 302 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" }, 303 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" }, 304 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" }, 305 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" }, 306 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" }, 307 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" }, 308 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" }, 309 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" }, 310 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" }, 311 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" }, 312 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" }, 313 { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" }, 314 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" }, 315 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" }, 316 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" }, 317 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" }, 318 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" }, 319 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" }, 320 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" }, 321 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" }, 322 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" }, 323 324 { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" }, 325 { STM32F4_RCC_AHB2ENR, 1, "jpeg", "ahb_div" }, 326 { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" }, 327 { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" }, 328 { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" }, 329 { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" }, 330 331 { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div", 332 CLK_IGNORE_UNUSED }, 333 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div", 334 CLK_IGNORE_UNUSED }, 335 336 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" }, 337 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" }, 338 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" }, 339 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" }, 340 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" }, 341 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" }, 342 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" }, 343 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" }, 344 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" }, 345 { STM32F4_RCC_APB1ENR, 10, "rtcapb", "apb1_mul" }, 346 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" }, 347 { STM32F4_RCC_APB1ENR, 13, "can3", "apb1_div" }, 348 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" }, 349 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" }, 350 { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" }, 351 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" }, 352 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" }, 353 { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" }, 354 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" }, 355 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" }, 356 357 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" }, 358 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" }, 359 { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux2" }, 360 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" }, 361 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" }, 362 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" }, 363 { STM32F4_RCC_APB2ENR, 11, "sdmmc1", "sdmux1" }, 364 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" }, 365 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" }, 366 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" }, 367 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" }, 368 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" }, 369 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" }, 370 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, 371 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, 372 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, 373 { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" }, 374 { STM32F4_RCC_APB2ENR, 30, "mdio", "apb2_div" }, 375 }; 376 377 enum stm32f4_pll_ssc_mod_type { 378 STM32F4_PLL_SSC_CENTER_SPREAD, 379 STM32F4_PLL_SSC_DOWN_SPREAD, 380 }; 381 382 static const char * const stm32f4_ssc_mod_methods[] __initconst = { 383 [STM32F4_PLL_SSC_DOWN_SPREAD] = "down-spread", 384 [STM32F4_PLL_SSC_CENTER_SPREAD] = "center-spread", 385 }; 386 387 /* 388 * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx 389 * have gate bits associated with them. Its combined hweight is 71. 390 */ 391 #define MAX_GATE_MAP 3 392 393 static const u64 stm32f42xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull, 394 0x0000000000000001ull, 395 0x04777f33f6fec9ffull }; 396 397 static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull, 398 0x0000000000000003ull, 399 0x0c777f33f6fec9ffull }; 400 401 static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull, 402 0x0000000000000003ull, 403 0x04f77f833e01c9ffull }; 404 405 static const u64 stm32f769_gate_map[MAX_GATE_MAP] = { 0x000000f37ef417ffull, 406 0x0000000000000003ull, 407 0x44F77F833E01EDFFull }; 408 409 static const u64 *stm32f4_gate_map; 410 411 static struct clk_hw **clks; 412 413 static DEFINE_SPINLOCK(stm32f4_clk_lock); 414 static void __iomem *base; 415 416 static struct regmap *pdrm; 417 418 static int stm32fx_end_primary_clk; 419 420 /* 421 * "Multiplier" device for APBx clocks. 422 * 423 * The APBx dividers are power-of-two dividers and, if *not* running in 1:1 424 * mode, they also tap out the one of the low order state bits to run the 425 * timers. ST datasheets represent this feature as a (conditional) clock 426 * multiplier. 427 */ 428 struct clk_apb_mul { 429 struct clk_hw hw; 430 u8 bit_idx; 431 }; 432 433 #define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw) 434 435 static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw, 436 unsigned long parent_rate) 437 { 438 struct clk_apb_mul *am = to_clk_apb_mul(hw); 439 440 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) 441 return parent_rate * 2; 442 443 return parent_rate; 444 } 445 446 static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate, 447 unsigned long *prate) 448 { 449 struct clk_apb_mul *am = to_clk_apb_mul(hw); 450 unsigned long mult = 1; 451 452 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) 453 mult = 2; 454 455 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { 456 unsigned long best_parent = rate / mult; 457 458 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); 459 } 460 461 return *prate * mult; 462 } 463 464 static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate, 465 unsigned long parent_rate) 466 { 467 /* 468 * We must report success but we can do so unconditionally because 469 * clk_apb_mul_round_rate returns values that ensure this call is a 470 * nop. 471 */ 472 473 return 0; 474 } 475 476 static const struct clk_ops clk_apb_mul_factor_ops = { 477 .round_rate = clk_apb_mul_round_rate, 478 .set_rate = clk_apb_mul_set_rate, 479 .recalc_rate = clk_apb_mul_recalc_rate, 480 }; 481 482 static struct clk *clk_register_apb_mul(struct device *dev, const char *name, 483 const char *parent_name, 484 unsigned long flags, u8 bit_idx) 485 { 486 struct clk_apb_mul *am; 487 struct clk_init_data init; 488 struct clk *clk; 489 490 am = kzalloc(sizeof(*am), GFP_KERNEL); 491 if (!am) 492 return ERR_PTR(-ENOMEM); 493 494 am->bit_idx = bit_idx; 495 am->hw.init = &init; 496 497 init.name = name; 498 init.ops = &clk_apb_mul_factor_ops; 499 init.flags = flags; 500 init.parent_names = &parent_name; 501 init.num_parents = 1; 502 503 clk = clk_register(dev, &am->hw); 504 505 if (IS_ERR(clk)) 506 kfree(am); 507 508 return clk; 509 } 510 511 enum { 512 PLL, 513 PLL_I2S, 514 PLL_SAI, 515 }; 516 517 static const struct clk_div_table pll_divp_table[] = { 518 { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 } 519 }; 520 521 static const struct clk_div_table pll_divq_table[] = { 522 { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, 523 { 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 }, 524 { 14, 14 }, { 15, 15 }, 525 { 0 } 526 }; 527 528 static const struct clk_div_table pll_divr_table[] = { 529 { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 } 530 }; 531 532 struct stm32f4_pll_ssc { 533 unsigned int mod_freq; 534 unsigned int mod_depth; 535 enum stm32f4_pll_ssc_mod_type mod_type; 536 }; 537 538 struct stm32f4_pll { 539 spinlock_t *lock; 540 struct clk_gate gate; 541 u8 offset; 542 u8 bit_rdy_idx; 543 u8 status; 544 u8 n_start; 545 bool ssc_enable; 546 struct stm32f4_pll_ssc ssc_conf; 547 }; 548 549 #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate) 550 551 struct stm32f4_pll_post_div_data { 552 int idx; 553 int pll_idx; 554 const char *name; 555 const char *parent; 556 u8 flag; 557 u8 offset; 558 u8 shift; 559 u8 width; 560 u8 flag_div; 561 const struct clk_div_table *div_table; 562 }; 563 564 struct stm32f4_vco_data { 565 const char *vco_name; 566 u8 offset; 567 u8 bit_idx; 568 u8 bit_rdy_idx; 569 bool sscg; 570 }; 571 572 static const struct stm32f4_vco_data vco_data[] = { 573 { "vco", STM32F4_RCC_PLLCFGR, 24, 25 }, 574 { "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 }, 575 { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 }, 576 }; 577 578 579 static const struct clk_div_table post_divr_table[] = { 580 { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 }, { 0 } 581 }; 582 583 #define MAX_POST_DIV 3 584 static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = { 585 { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q", 586 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL}, 587 588 { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q", 589 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL }, 590 591 { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, 592 STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table }, 593 }; 594 595 struct stm32f4_div_data { 596 u8 shift; 597 u8 width; 598 u8 flag_div; 599 const struct clk_div_table *div_table; 600 }; 601 602 #define MAX_PLL_DIV 3 603 static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = { 604 { 16, 2, 0, pll_divp_table }, 605 { 24, 4, 0, pll_divq_table }, 606 { 28, 3, 0, pll_divr_table }, 607 }; 608 609 struct stm32f4_pll_data { 610 u8 pll_num; 611 u8 n_start; 612 const char *div_name[MAX_PLL_DIV]; 613 }; 614 615 static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = { 616 { PLL, 192, { "pll", "pll48", NULL } }, 617 { PLL_I2S, 192, { NULL, "plli2s-q", "plli2s-r" } }, 618 { PLL_SAI, 49, { NULL, "pllsai-q", "pllsai-r" } }, 619 }; 620 621 static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = { 622 { PLL, 50, { "pll", "pll-q", "pll-r" } }, 623 { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } }, 624 { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } }, 625 }; 626 627 static int stm32f4_pll_is_enabled(struct clk_hw *hw) 628 { 629 return clk_gate_ops.is_enabled(hw); 630 } 631 632 #define PLL_TIMEOUT 10000 633 634 static int stm32f4_pll_enable(struct clk_hw *hw) 635 { 636 struct clk_gate *gate = to_clk_gate(hw); 637 struct stm32f4_pll *pll = to_stm32f4_pll(gate); 638 int bit_status; 639 unsigned int timeout = PLL_TIMEOUT; 640 641 if (clk_gate_ops.is_enabled(hw)) 642 return 0; 643 644 clk_gate_ops.enable(hw); 645 646 do { 647 bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx)); 648 649 } while (bit_status && --timeout); 650 651 return bit_status; 652 } 653 654 static void stm32f4_pll_disable(struct clk_hw *hw) 655 { 656 clk_gate_ops.disable(hw); 657 } 658 659 static unsigned long stm32f4_pll_recalc(struct clk_hw *hw, 660 unsigned long parent_rate) 661 { 662 struct clk_gate *gate = to_clk_gate(hw); 663 struct stm32f4_pll *pll = to_stm32f4_pll(gate); 664 unsigned long val; 665 unsigned long n; 666 667 val = readl(base + pll->offset); 668 n = FIELD_GET(STM32F4_RCC_PLLCFGR_N_MASK, val); 669 670 return parent_rate * n; 671 } 672 673 static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate, 674 unsigned long *prate) 675 { 676 struct clk_gate *gate = to_clk_gate(hw); 677 struct stm32f4_pll *pll = to_stm32f4_pll(gate); 678 unsigned long n; 679 680 n = rate / *prate; 681 682 if (n < pll->n_start) 683 n = pll->n_start; 684 else if (n > 432) 685 n = 432; 686 687 return *prate * n; 688 } 689 690 static void stm32f4_pll_set_ssc(struct clk_hw *hw, unsigned long parent_rate, 691 unsigned int ndiv) 692 { 693 struct clk_gate *gate = to_clk_gate(hw); 694 struct stm32f4_pll *pll = to_stm32f4_pll(gate); 695 struct stm32f4_pll_ssc *ssc = &pll->ssc_conf; 696 u32 modeper, incstep; 697 u32 sscgr; 698 699 sscgr = readl(base + STM32F4_RCC_SSCGR); 700 /* reserved field must be kept at reset value */ 701 sscgr &= STM32F4_RCC_SSCGR_RESERVED_MASK; 702 703 modeper = DIV_ROUND_CLOSEST(parent_rate, 4 * ssc->mod_freq); 704 incstep = DIV_ROUND_CLOSEST(((1 << 15) - 1) * ssc->mod_depth * ndiv, 705 5 * 10000 * modeper); 706 sscgr |= STM32F4_RCC_SSCGR_SSCGEN | 707 FIELD_PREP(STM32F4_RCC_SSCGR_INCSTEP_MASK, incstep) | 708 FIELD_PREP(STM32F4_RCC_SSCGR_MODPER_MASK, modeper); 709 710 if (ssc->mod_type) 711 sscgr |= STM32F4_RCC_SSCGR_SPREADSEL; 712 713 writel(sscgr, base + STM32F4_RCC_SSCGR); 714 } 715 716 static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate, 717 unsigned long parent_rate) 718 { 719 struct clk_gate *gate = to_clk_gate(hw); 720 struct stm32f4_pll *pll = to_stm32f4_pll(gate); 721 722 unsigned long n; 723 unsigned long val; 724 int pll_state; 725 726 pll_state = stm32f4_pll_is_enabled(hw); 727 728 if (pll_state) 729 stm32f4_pll_disable(hw); 730 731 n = rate / parent_rate; 732 733 val = readl(base + pll->offset) & ~STM32F4_RCC_PLLCFGR_N_MASK; 734 val |= FIELD_PREP(STM32F4_RCC_PLLCFGR_N_MASK, n); 735 736 writel(val, base + pll->offset); 737 738 if (pll->ssc_enable) 739 stm32f4_pll_set_ssc(hw, parent_rate, n); 740 741 if (pll_state) 742 stm32f4_pll_enable(hw); 743 744 return 0; 745 } 746 747 static const struct clk_ops stm32f4_pll_gate_ops = { 748 .enable = stm32f4_pll_enable, 749 .disable = stm32f4_pll_disable, 750 .is_enabled = stm32f4_pll_is_enabled, 751 .recalc_rate = stm32f4_pll_recalc, 752 .round_rate = stm32f4_pll_round_rate, 753 .set_rate = stm32f4_pll_set_rate, 754 }; 755 756 struct stm32f4_pll_div { 757 struct clk_divider div; 758 struct clk_hw *hw_pll; 759 }; 760 761 #define to_pll_div_clk(_div) container_of(_div, struct stm32f4_pll_div, div) 762 763 static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw, 764 unsigned long parent_rate) 765 { 766 return clk_divider_ops.recalc_rate(hw, parent_rate); 767 } 768 769 static int stm32f4_pll_div_determine_rate(struct clk_hw *hw, 770 struct clk_rate_request *req) 771 { 772 return clk_divider_ops.determine_rate(hw, req); 773 } 774 775 static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate, 776 unsigned long parent_rate) 777 { 778 int pll_state, ret; 779 780 struct clk_divider *div = to_clk_divider(hw); 781 struct stm32f4_pll_div *pll_div = to_pll_div_clk(div); 782 783 pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll); 784 785 if (pll_state) 786 stm32f4_pll_disable(pll_div->hw_pll); 787 788 ret = clk_divider_ops.set_rate(hw, rate, parent_rate); 789 790 if (pll_state) 791 stm32f4_pll_enable(pll_div->hw_pll); 792 793 return ret; 794 } 795 796 static const struct clk_ops stm32f4_pll_div_ops = { 797 .recalc_rate = stm32f4_pll_div_recalc_rate, 798 .determine_rate = stm32f4_pll_div_determine_rate, 799 .set_rate = stm32f4_pll_div_set_rate, 800 }; 801 802 static struct clk_hw *clk_register_pll_div(const char *name, 803 const char *parent_name, unsigned long flags, 804 void __iomem *reg, u8 shift, u8 width, 805 u8 clk_divider_flags, const struct clk_div_table *table, 806 struct clk_hw *pll_hw, spinlock_t *lock) 807 { 808 struct stm32f4_pll_div *pll_div; 809 struct clk_hw *hw; 810 struct clk_init_data init; 811 int ret; 812 813 /* allocate the divider */ 814 pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL); 815 if (!pll_div) 816 return ERR_PTR(-ENOMEM); 817 818 init.name = name; 819 init.ops = &stm32f4_pll_div_ops; 820 init.flags = flags; 821 init.parent_names = (parent_name ? &parent_name : NULL); 822 init.num_parents = (parent_name ? 1 : 0); 823 824 /* struct clk_divider assignments */ 825 pll_div->div.reg = reg; 826 pll_div->div.shift = shift; 827 pll_div->div.width = width; 828 pll_div->div.flags = clk_divider_flags; 829 pll_div->div.lock = lock; 830 pll_div->div.table = table; 831 pll_div->div.hw.init = &init; 832 833 pll_div->hw_pll = pll_hw; 834 835 /* register the clock */ 836 hw = &pll_div->div.hw; 837 ret = clk_hw_register(NULL, hw); 838 if (ret) { 839 kfree(pll_div); 840 hw = ERR_PTR(ret); 841 } 842 843 return hw; 844 } 845 846 static int __init stm32f4_pll_init_ssc(struct clk_hw *hw, 847 const struct stm32f4_pll_ssc *conf) 848 { 849 struct clk_gate *gate = to_clk_gate(hw); 850 struct stm32f4_pll *pll = to_stm32f4_pll(gate); 851 struct clk_hw *parent; 852 unsigned long parent_rate; 853 int pll_state; 854 unsigned long n, val; 855 856 parent = clk_hw_get_parent(hw); 857 if (!parent) { 858 pr_err("%s: failed to get clock parent\n", __func__); 859 return -ENODEV; 860 } 861 862 parent_rate = clk_hw_get_rate(parent); 863 864 pll->ssc_enable = true; 865 memcpy(&pll->ssc_conf, conf, sizeof(pll->ssc_conf)); 866 867 pll_state = stm32f4_pll_is_enabled(hw); 868 869 if (pll_state) 870 stm32f4_pll_disable(hw); 871 872 val = readl(base + pll->offset); 873 n = FIELD_GET(STM32F4_RCC_PLLCFGR_N_MASK, val); 874 875 pr_debug("%s: pll: %s, parent: %s, parent-rate: %lu, n: %lu\n", 876 __func__, clk_hw_get_name(hw), clk_hw_get_name(parent), 877 parent_rate, n); 878 879 stm32f4_pll_set_ssc(hw, parent_rate, n); 880 881 if (pll_state) 882 stm32f4_pll_enable(hw); 883 884 return 0; 885 } 886 887 static int __init stm32f4_pll_ssc_parse_dt(struct device_node *np, 888 struct stm32f4_pll_ssc *conf) 889 { 890 int ret; 891 892 if (!conf) 893 return -EINVAL; 894 895 ret = of_property_read_u32(np, "st,ssc-modfreq-hz", &conf->mod_freq); 896 if (ret) 897 return ret; 898 899 ret = of_property_read_u32(np, "st,ssc-moddepth-permyriad", 900 &conf->mod_depth); 901 if (ret) { 902 pr_err("%pOF: missing st,ssc-moddepth-permyriad\n", np); 903 return ret; 904 } 905 906 ret = fwnode_property_match_property_string(of_fwnode_handle(np), 907 "st,ssc-modmethod", 908 stm32f4_ssc_mod_methods, 909 ARRAY_SIZE(stm32f4_ssc_mod_methods)); 910 if (ret < 0) { 911 pr_err("%pOF: failed to get st,ssc-modmethod\n", np); 912 return ret; 913 } 914 915 conf->mod_type = ret; 916 917 pr_debug("%pOF: SSCG settings: mod_freq: %d, mod_depth: %d mod_method: %s [%d]\n", 918 np, conf->mod_freq, conf->mod_depth, 919 stm32f4_ssc_mod_methods[ret], conf->mod_type); 920 921 return 0; 922 } 923 924 static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc, 925 const struct stm32f4_pll_data *data, spinlock_t *lock) 926 { 927 struct stm32f4_pll *pll; 928 struct clk_init_data init = { NULL }; 929 void __iomem *reg; 930 struct clk_hw *pll_hw; 931 int ret; 932 int i; 933 const struct stm32f4_vco_data *vco; 934 935 936 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 937 if (!pll) 938 return ERR_PTR(-ENOMEM); 939 940 vco = &vco_data[data->pll_num]; 941 942 init.name = vco->vco_name; 943 init.ops = &stm32f4_pll_gate_ops; 944 init.flags = CLK_SET_RATE_GATE; 945 init.parent_names = &pllsrc; 946 init.num_parents = 1; 947 948 pll->gate.lock = lock; 949 pll->gate.reg = base + STM32F4_RCC_CR; 950 pll->gate.bit_idx = vco->bit_idx; 951 pll->gate.hw.init = &init; 952 953 pll->offset = vco->offset; 954 pll->n_start = data->n_start; 955 pll->bit_rdy_idx = vco->bit_rdy_idx; 956 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1; 957 958 reg = base + pll->offset; 959 960 pll_hw = &pll->gate.hw; 961 ret = clk_hw_register(NULL, pll_hw); 962 if (ret) { 963 kfree(pll); 964 return ERR_PTR(ret); 965 } 966 967 for (i = 0; i < MAX_PLL_DIV; i++) 968 if (data->div_name[i]) 969 clk_register_pll_div(data->div_name[i], 970 vco->vco_name, 971 0, 972 reg, 973 div_data[i].shift, 974 div_data[i].width, 975 div_data[i].flag_div, 976 div_data[i].div_table, 977 pll_hw, 978 lock); 979 return pll_hw; 980 } 981 982 /* 983 * Converts the primary and secondary indices (as they appear in DT) to an 984 * offset into our struct clock array. 985 */ 986 static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary) 987 { 988 u64 table[MAX_GATE_MAP]; 989 990 if (primary == 1) { 991 if (WARN_ON(secondary >= stm32fx_end_primary_clk)) 992 return -EINVAL; 993 return secondary; 994 } 995 996 memcpy(table, stm32f4_gate_map, sizeof(table)); 997 998 /* only bits set in table can be used as indices */ 999 if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) || 1000 0 == (table[BIT_ULL_WORD(secondary)] & 1001 BIT_ULL_MASK(secondary)))) 1002 return -EINVAL; 1003 1004 /* mask out bits above our current index */ 1005 table[BIT_ULL_WORD(secondary)] &= 1006 GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0); 1007 1008 return stm32fx_end_primary_clk - 1 + hweight64(table[0]) + 1009 (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) + 1010 (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0); 1011 } 1012 1013 static struct clk_hw * 1014 stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data) 1015 { 1016 int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]); 1017 1018 if (i < 0) 1019 return ERR_PTR(-EINVAL); 1020 1021 return clks[i]; 1022 } 1023 1024 #define to_rgclk(_rgate) container_of(_rgate, struct stm32_rgate, gate) 1025 1026 static inline void disable_power_domain_write_protection(void) 1027 { 1028 if (pdrm) 1029 regmap_update_bits(pdrm, 0x00, (1 << 8), (1 << 8)); 1030 } 1031 1032 static inline void enable_power_domain_write_protection(void) 1033 { 1034 if (pdrm) 1035 regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8)); 1036 } 1037 1038 static inline void sofware_reset_backup_domain(void) 1039 { 1040 unsigned long val; 1041 1042 val = readl(base + STM32F4_RCC_BDCR); 1043 writel(val | BIT(16), base + STM32F4_RCC_BDCR); 1044 writel(val & ~BIT(16), base + STM32F4_RCC_BDCR); 1045 } 1046 1047 struct stm32_rgate { 1048 struct clk_gate gate; 1049 u8 bit_rdy_idx; 1050 }; 1051 1052 #define RGATE_TIMEOUT 50000 1053 1054 static int rgclk_enable(struct clk_hw *hw) 1055 { 1056 struct clk_gate *gate = to_clk_gate(hw); 1057 struct stm32_rgate *rgate = to_rgclk(gate); 1058 int bit_status; 1059 unsigned int timeout = RGATE_TIMEOUT; 1060 1061 if (clk_gate_ops.is_enabled(hw)) 1062 return 0; 1063 1064 disable_power_domain_write_protection(); 1065 1066 clk_gate_ops.enable(hw); 1067 1068 do { 1069 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx)); 1070 if (bit_status) 1071 udelay(100); 1072 1073 } while (bit_status && --timeout); 1074 1075 enable_power_domain_write_protection(); 1076 1077 return bit_status; 1078 } 1079 1080 static void rgclk_disable(struct clk_hw *hw) 1081 { 1082 clk_gate_ops.disable(hw); 1083 } 1084 1085 static int rgclk_is_enabled(struct clk_hw *hw) 1086 { 1087 return clk_gate_ops.is_enabled(hw); 1088 } 1089 1090 static const struct clk_ops rgclk_ops = { 1091 .enable = rgclk_enable, 1092 .disable = rgclk_disable, 1093 .is_enabled = rgclk_is_enabled, 1094 }; 1095 1096 static struct clk_hw *clk_register_rgate(struct device *dev, const char *name, 1097 const char *parent_name, unsigned long flags, 1098 void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx, 1099 u8 clk_gate_flags, spinlock_t *lock) 1100 { 1101 struct stm32_rgate *rgate; 1102 struct clk_init_data init = { NULL }; 1103 struct clk_hw *hw; 1104 int ret; 1105 1106 rgate = kzalloc(sizeof(*rgate), GFP_KERNEL); 1107 if (!rgate) 1108 return ERR_PTR(-ENOMEM); 1109 1110 init.name = name; 1111 init.ops = &rgclk_ops; 1112 init.flags = flags; 1113 init.parent_names = &parent_name; 1114 init.num_parents = 1; 1115 1116 rgate->bit_rdy_idx = bit_rdy_idx; 1117 1118 rgate->gate.lock = lock; 1119 rgate->gate.reg = reg; 1120 rgate->gate.bit_idx = bit_idx; 1121 rgate->gate.hw.init = &init; 1122 1123 hw = &rgate->gate.hw; 1124 ret = clk_hw_register(dev, hw); 1125 if (ret) { 1126 kfree(rgate); 1127 hw = ERR_PTR(ret); 1128 } 1129 1130 return hw; 1131 } 1132 1133 static int cclk_gate_enable(struct clk_hw *hw) 1134 { 1135 int ret; 1136 1137 disable_power_domain_write_protection(); 1138 1139 ret = clk_gate_ops.enable(hw); 1140 1141 enable_power_domain_write_protection(); 1142 1143 return ret; 1144 } 1145 1146 static void cclk_gate_disable(struct clk_hw *hw) 1147 { 1148 disable_power_domain_write_protection(); 1149 1150 clk_gate_ops.disable(hw); 1151 1152 enable_power_domain_write_protection(); 1153 } 1154 1155 static int cclk_gate_is_enabled(struct clk_hw *hw) 1156 { 1157 return clk_gate_ops.is_enabled(hw); 1158 } 1159 1160 static const struct clk_ops cclk_gate_ops = { 1161 .enable = cclk_gate_enable, 1162 .disable = cclk_gate_disable, 1163 .is_enabled = cclk_gate_is_enabled, 1164 }; 1165 1166 static u8 cclk_mux_get_parent(struct clk_hw *hw) 1167 { 1168 return clk_mux_ops.get_parent(hw); 1169 } 1170 1171 static int cclk_mux_set_parent(struct clk_hw *hw, u8 index) 1172 { 1173 int ret; 1174 1175 disable_power_domain_write_protection(); 1176 1177 sofware_reset_backup_domain(); 1178 1179 ret = clk_mux_ops.set_parent(hw, index); 1180 1181 enable_power_domain_write_protection(); 1182 1183 return ret; 1184 } 1185 1186 static const struct clk_ops cclk_mux_ops = { 1187 .determine_rate = clk_hw_determine_rate_no_reparent, 1188 .get_parent = cclk_mux_get_parent, 1189 .set_parent = cclk_mux_set_parent, 1190 }; 1191 1192 static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name, 1193 const char * const *parent_names, int num_parents, 1194 void __iomem *reg, u8 bit_idx, u8 shift, unsigned long flags, 1195 spinlock_t *lock) 1196 { 1197 struct clk_hw *hw; 1198 struct clk_gate *gate; 1199 struct clk_mux *mux; 1200 1201 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 1202 if (!gate) { 1203 hw = ERR_PTR(-EINVAL); 1204 goto fail; 1205 } 1206 1207 mux = kzalloc(sizeof(*mux), GFP_KERNEL); 1208 if (!mux) { 1209 kfree(gate); 1210 hw = ERR_PTR(-EINVAL); 1211 goto fail; 1212 } 1213 1214 gate->reg = reg; 1215 gate->bit_idx = bit_idx; 1216 gate->flags = 0; 1217 gate->lock = lock; 1218 1219 mux->reg = reg; 1220 mux->shift = shift; 1221 mux->mask = 3; 1222 mux->flags = 0; 1223 1224 hw = clk_hw_register_composite(dev, name, parent_names, num_parents, 1225 &mux->hw, &cclk_mux_ops, 1226 NULL, NULL, 1227 &gate->hw, &cclk_gate_ops, 1228 flags); 1229 1230 if (IS_ERR(hw)) { 1231 kfree(gate); 1232 kfree(mux); 1233 } 1234 1235 fail: 1236 return hw; 1237 } 1238 1239 static const char *sys_parents[] __initdata = { "hsi", NULL, "pll" }; 1240 1241 static const struct clk_div_table ahb_div_table[] = { 1242 { 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 }, 1243 { 0x4, 1 }, { 0x5, 1 }, { 0x6, 1 }, { 0x7, 1 }, 1244 { 0x8, 2 }, { 0x9, 4 }, { 0xa, 8 }, { 0xb, 16 }, 1245 { 0xc, 64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 }, 1246 { 0 }, 1247 }; 1248 1249 static const struct clk_div_table apb_div_table[] = { 1250 { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, 1251 { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 }, 1252 { 0 }, 1253 }; 1254 1255 static const char *rtc_parents[4] = { 1256 "no-clock", "lse", "lsi", "hse-rtc" 1257 }; 1258 1259 static const char *pll_src = "pll-src"; 1260 1261 static const char *pllsrc_parent[2] = { "hsi", NULL }; 1262 1263 static const char *dsi_parent[2] = { NULL, "pll-r" }; 1264 1265 static const char *lcd_parent[1] = { "pllsai-r-div" }; 1266 1267 static const char *i2s_parents[2] = { "plli2s-r", NULL }; 1268 1269 static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL, 1270 "no-clock" }; 1271 1272 static const char *pll48_parents[2] = { "pll-q", "pllsai-p" }; 1273 1274 static const char *sdmux_parents[2] = { "pll48", "sys" }; 1275 1276 static const char *hdmi_parents[2] = { "lse", "hsi_div488" }; 1277 1278 static const char *spdif_parent[1] = { "plli2s-p" }; 1279 1280 static const char *lptim_parent[4] = { "apb1_mul", "lsi", "hsi", "lse" }; 1281 1282 static const char *uart_parents1[4] = { "apb2_div", "sys", "hsi", "lse" }; 1283 static const char *uart_parents2[4] = { "apb1_div", "sys", "hsi", "lse" }; 1284 1285 static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" }; 1286 1287 static const char * const dfsdm1_src[] = { "apb2_div", "sys" }; 1288 static const char * const adsfdm1_parent[] = { "sai1_clk", "sai2_clk" }; 1289 1290 struct stm32_aux_clk { 1291 int idx; 1292 const char *name; 1293 const char * const *parent_names; 1294 int num_parents; 1295 int offset_mux; 1296 u8 shift; 1297 u8 mask; 1298 int offset_gate; 1299 u8 bit_idx; 1300 unsigned long flags; 1301 }; 1302 1303 struct stm32f4_clk_data { 1304 const struct stm32f4_gate_data *gates_data; 1305 const u64 *gates_map; 1306 int gates_num; 1307 const struct stm32f4_pll_data *pll_data; 1308 const struct stm32_aux_clk *aux_clk; 1309 int aux_clk_num; 1310 int end_primary; 1311 }; 1312 1313 static const struct stm32_aux_clk stm32f429_aux_clk[] = { 1314 { 1315 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent), 1316 NO_MUX, 0, 0, 1317 STM32F4_RCC_APB2ENR, 26, 1318 CLK_SET_RATE_PARENT 1319 }, 1320 { 1321 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents), 1322 STM32F4_RCC_CFGR, 23, 1, 1323 NO_GATE, 0, 1324 CLK_SET_RATE_PARENT 1325 }, 1326 { 1327 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents), 1328 STM32F4_RCC_DCKCFGR, 20, 3, 1329 STM32F4_RCC_APB2ENR, 22, 1330 CLK_SET_RATE_PARENT 1331 }, 1332 { 1333 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents), 1334 STM32F4_RCC_DCKCFGR, 22, 3, 1335 STM32F4_RCC_APB2ENR, 22, 1336 CLK_SET_RATE_PARENT 1337 }, 1338 }; 1339 1340 static const struct stm32_aux_clk stm32f469_aux_clk[] = { 1341 { 1342 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent), 1343 NO_MUX, 0, 0, 1344 STM32F4_RCC_APB2ENR, 26, 1345 CLK_SET_RATE_PARENT 1346 }, 1347 { 1348 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents), 1349 STM32F4_RCC_CFGR, 23, 1, 1350 NO_GATE, 0, 1351 CLK_SET_RATE_PARENT 1352 }, 1353 { 1354 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents), 1355 STM32F4_RCC_DCKCFGR, 20, 3, 1356 STM32F4_RCC_APB2ENR, 22, 1357 CLK_SET_RATE_PARENT 1358 }, 1359 { 1360 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents), 1361 STM32F4_RCC_DCKCFGR, 22, 3, 1362 STM32F4_RCC_APB2ENR, 22, 1363 CLK_SET_RATE_PARENT 1364 }, 1365 { 1366 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents), 1367 STM32F4_RCC_DCKCFGR, 27, 1, 1368 NO_GATE, 0, 1369 0 1370 }, 1371 { 1372 NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents), 1373 STM32F4_RCC_DCKCFGR, 28, 1, 1374 NO_GATE, 0, 1375 0 1376 }, 1377 { 1378 CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent), 1379 STM32F4_RCC_DCKCFGR, 29, 1, 1380 STM32F4_RCC_APB2ENR, 27, 1381 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT 1382 }, 1383 }; 1384 1385 static const struct stm32_aux_clk stm32f746_aux_clk[] = { 1386 { 1387 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent), 1388 NO_MUX, 0, 0, 1389 STM32F4_RCC_APB2ENR, 26, 1390 CLK_SET_RATE_PARENT 1391 }, 1392 { 1393 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents), 1394 STM32F4_RCC_CFGR, 23, 1, 1395 NO_GATE, 0, 1396 CLK_SET_RATE_PARENT 1397 }, 1398 { 1399 CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents), 1400 STM32F4_RCC_DCKCFGR, 20, 3, 1401 STM32F4_RCC_APB2ENR, 22, 1402 CLK_SET_RATE_PARENT 1403 }, 1404 { 1405 CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents), 1406 STM32F4_RCC_DCKCFGR, 22, 3, 1407 STM32F4_RCC_APB2ENR, 23, 1408 CLK_SET_RATE_PARENT 1409 }, 1410 { 1411 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents), 1412 STM32F7_RCC_DCKCFGR2, 27, 1, 1413 NO_GATE, 0, 1414 0 1415 }, 1416 { 1417 NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents), 1418 STM32F7_RCC_DCKCFGR2, 28, 1, 1419 NO_GATE, 0, 1420 0 1421 }, 1422 { 1423 CLK_HDMI_CEC, "hdmi-cec", 1424 hdmi_parents, ARRAY_SIZE(hdmi_parents), 1425 STM32F7_RCC_DCKCFGR2, 26, 1, 1426 NO_GATE, 0, 1427 0 1428 }, 1429 { 1430 CLK_SPDIF, "spdif-rx", 1431 spdif_parent, ARRAY_SIZE(spdif_parent), 1432 STM32F7_RCC_DCKCFGR2, 22, 3, 1433 STM32F4_RCC_APB2ENR, 23, 1434 CLK_SET_RATE_PARENT 1435 }, 1436 { 1437 CLK_USART1, "usart1", 1438 uart_parents1, ARRAY_SIZE(uart_parents1), 1439 STM32F7_RCC_DCKCFGR2, 0, 3, 1440 STM32F4_RCC_APB2ENR, 4, 1441 CLK_SET_RATE_PARENT, 1442 }, 1443 { 1444 CLK_USART2, "usart2", 1445 uart_parents2, ARRAY_SIZE(uart_parents1), 1446 STM32F7_RCC_DCKCFGR2, 2, 3, 1447 STM32F4_RCC_APB1ENR, 17, 1448 CLK_SET_RATE_PARENT, 1449 }, 1450 { 1451 CLK_USART3, "usart3", 1452 uart_parents2, ARRAY_SIZE(uart_parents1), 1453 STM32F7_RCC_DCKCFGR2, 4, 3, 1454 STM32F4_RCC_APB1ENR, 18, 1455 CLK_SET_RATE_PARENT, 1456 }, 1457 { 1458 CLK_UART4, "uart4", 1459 uart_parents2, ARRAY_SIZE(uart_parents1), 1460 STM32F7_RCC_DCKCFGR2, 6, 3, 1461 STM32F4_RCC_APB1ENR, 19, 1462 CLK_SET_RATE_PARENT, 1463 }, 1464 { 1465 CLK_UART5, "uart5", 1466 uart_parents2, ARRAY_SIZE(uart_parents1), 1467 STM32F7_RCC_DCKCFGR2, 8, 3, 1468 STM32F4_RCC_APB1ENR, 20, 1469 CLK_SET_RATE_PARENT, 1470 }, 1471 { 1472 CLK_USART6, "usart6", 1473 uart_parents1, ARRAY_SIZE(uart_parents1), 1474 STM32F7_RCC_DCKCFGR2, 10, 3, 1475 STM32F4_RCC_APB2ENR, 5, 1476 CLK_SET_RATE_PARENT, 1477 }, 1478 1479 { 1480 CLK_UART7, "uart7", 1481 uart_parents2, ARRAY_SIZE(uart_parents1), 1482 STM32F7_RCC_DCKCFGR2, 12, 3, 1483 STM32F4_RCC_APB1ENR, 30, 1484 CLK_SET_RATE_PARENT, 1485 }, 1486 { 1487 CLK_UART8, "uart8", 1488 uart_parents2, ARRAY_SIZE(uart_parents1), 1489 STM32F7_RCC_DCKCFGR2, 14, 3, 1490 STM32F4_RCC_APB1ENR, 31, 1491 CLK_SET_RATE_PARENT, 1492 }, 1493 { 1494 CLK_I2C1, "i2c1", 1495 i2c_parents, ARRAY_SIZE(i2c_parents), 1496 STM32F7_RCC_DCKCFGR2, 16, 3, 1497 STM32F4_RCC_APB1ENR, 21, 1498 CLK_SET_RATE_PARENT, 1499 }, 1500 { 1501 CLK_I2C2, "i2c2", 1502 i2c_parents, ARRAY_SIZE(i2c_parents), 1503 STM32F7_RCC_DCKCFGR2, 18, 3, 1504 STM32F4_RCC_APB1ENR, 22, 1505 CLK_SET_RATE_PARENT, 1506 }, 1507 { 1508 CLK_I2C3, "i2c3", 1509 i2c_parents, ARRAY_SIZE(i2c_parents), 1510 STM32F7_RCC_DCKCFGR2, 20, 3, 1511 STM32F4_RCC_APB1ENR, 23, 1512 CLK_SET_RATE_PARENT, 1513 }, 1514 { 1515 CLK_I2C4, "i2c4", 1516 i2c_parents, ARRAY_SIZE(i2c_parents), 1517 STM32F7_RCC_DCKCFGR2, 22, 3, 1518 STM32F4_RCC_APB1ENR, 24, 1519 CLK_SET_RATE_PARENT, 1520 }, 1521 1522 { 1523 CLK_LPTIMER, "lptim1", 1524 lptim_parent, ARRAY_SIZE(lptim_parent), 1525 STM32F7_RCC_DCKCFGR2, 24, 3, 1526 STM32F4_RCC_APB1ENR, 9, 1527 CLK_SET_RATE_PARENT 1528 }, 1529 }; 1530 1531 static const struct stm32_aux_clk stm32f769_aux_clk[] = { 1532 { 1533 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent), 1534 NO_MUX, 0, 0, 1535 STM32F4_RCC_APB2ENR, 26, 1536 CLK_SET_RATE_PARENT 1537 }, 1538 { 1539 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents), 1540 STM32F4_RCC_CFGR, 23, 1, 1541 NO_GATE, 0, 1542 CLK_SET_RATE_PARENT 1543 }, 1544 { 1545 CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents), 1546 STM32F4_RCC_DCKCFGR, 20, 3, 1547 STM32F4_RCC_APB2ENR, 22, 1548 CLK_SET_RATE_PARENT 1549 }, 1550 { 1551 CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents), 1552 STM32F4_RCC_DCKCFGR, 22, 3, 1553 STM32F4_RCC_APB2ENR, 23, 1554 CLK_SET_RATE_PARENT 1555 }, 1556 { 1557 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents), 1558 STM32F7_RCC_DCKCFGR2, 27, 1, 1559 NO_GATE, 0, 1560 0 1561 }, 1562 { 1563 NO_IDX, "sdmux1", sdmux_parents, ARRAY_SIZE(sdmux_parents), 1564 STM32F7_RCC_DCKCFGR2, 28, 1, 1565 NO_GATE, 0, 1566 0 1567 }, 1568 { 1569 NO_IDX, "sdmux2", sdmux_parents, ARRAY_SIZE(sdmux_parents), 1570 STM32F7_RCC_DCKCFGR2, 29, 1, 1571 NO_GATE, 0, 1572 0 1573 }, 1574 { 1575 CLK_HDMI_CEC, "hdmi-cec", 1576 hdmi_parents, ARRAY_SIZE(hdmi_parents), 1577 STM32F7_RCC_DCKCFGR2, 26, 1, 1578 NO_GATE, 0, 1579 0 1580 }, 1581 { 1582 CLK_SPDIF, "spdif-rx", 1583 spdif_parent, ARRAY_SIZE(spdif_parent), 1584 STM32F7_RCC_DCKCFGR2, 22, 3, 1585 STM32F4_RCC_APB2ENR, 23, 1586 CLK_SET_RATE_PARENT 1587 }, 1588 { 1589 CLK_USART1, "usart1", 1590 uart_parents1, ARRAY_SIZE(uart_parents1), 1591 STM32F7_RCC_DCKCFGR2, 0, 3, 1592 STM32F4_RCC_APB2ENR, 4, 1593 CLK_SET_RATE_PARENT, 1594 }, 1595 { 1596 CLK_USART2, "usart2", 1597 uart_parents2, ARRAY_SIZE(uart_parents1), 1598 STM32F7_RCC_DCKCFGR2, 2, 3, 1599 STM32F4_RCC_APB1ENR, 17, 1600 CLK_SET_RATE_PARENT, 1601 }, 1602 { 1603 CLK_USART3, "usart3", 1604 uart_parents2, ARRAY_SIZE(uart_parents1), 1605 STM32F7_RCC_DCKCFGR2, 4, 3, 1606 STM32F4_RCC_APB1ENR, 18, 1607 CLK_SET_RATE_PARENT, 1608 }, 1609 { 1610 CLK_UART4, "uart4", 1611 uart_parents2, ARRAY_SIZE(uart_parents1), 1612 STM32F7_RCC_DCKCFGR2, 6, 3, 1613 STM32F4_RCC_APB1ENR, 19, 1614 CLK_SET_RATE_PARENT, 1615 }, 1616 { 1617 CLK_UART5, "uart5", 1618 uart_parents2, ARRAY_SIZE(uart_parents1), 1619 STM32F7_RCC_DCKCFGR2, 8, 3, 1620 STM32F4_RCC_APB1ENR, 20, 1621 CLK_SET_RATE_PARENT, 1622 }, 1623 { 1624 CLK_USART6, "usart6", 1625 uart_parents1, ARRAY_SIZE(uart_parents1), 1626 STM32F7_RCC_DCKCFGR2, 10, 3, 1627 STM32F4_RCC_APB2ENR, 5, 1628 CLK_SET_RATE_PARENT, 1629 }, 1630 { 1631 CLK_UART7, "uart7", 1632 uart_parents2, ARRAY_SIZE(uart_parents1), 1633 STM32F7_RCC_DCKCFGR2, 12, 3, 1634 STM32F4_RCC_APB1ENR, 30, 1635 CLK_SET_RATE_PARENT, 1636 }, 1637 { 1638 CLK_UART8, "uart8", 1639 uart_parents2, ARRAY_SIZE(uart_parents1), 1640 STM32F7_RCC_DCKCFGR2, 14, 3, 1641 STM32F4_RCC_APB1ENR, 31, 1642 CLK_SET_RATE_PARENT, 1643 }, 1644 { 1645 CLK_I2C1, "i2c1", 1646 i2c_parents, ARRAY_SIZE(i2c_parents), 1647 STM32F7_RCC_DCKCFGR2, 16, 3, 1648 STM32F4_RCC_APB1ENR, 21, 1649 CLK_SET_RATE_PARENT, 1650 }, 1651 { 1652 CLK_I2C2, "i2c2", 1653 i2c_parents, ARRAY_SIZE(i2c_parents), 1654 STM32F7_RCC_DCKCFGR2, 18, 3, 1655 STM32F4_RCC_APB1ENR, 22, 1656 CLK_SET_RATE_PARENT, 1657 }, 1658 { 1659 CLK_I2C3, "i2c3", 1660 i2c_parents, ARRAY_SIZE(i2c_parents), 1661 STM32F7_RCC_DCKCFGR2, 20, 3, 1662 STM32F4_RCC_APB1ENR, 23, 1663 CLK_SET_RATE_PARENT, 1664 }, 1665 { 1666 CLK_I2C4, "i2c4", 1667 i2c_parents, ARRAY_SIZE(i2c_parents), 1668 STM32F7_RCC_DCKCFGR2, 22, 3, 1669 STM32F4_RCC_APB1ENR, 24, 1670 CLK_SET_RATE_PARENT, 1671 }, 1672 { 1673 CLK_LPTIMER, "lptim1", 1674 lptim_parent, ARRAY_SIZE(lptim_parent), 1675 STM32F7_RCC_DCKCFGR2, 24, 3, 1676 STM32F4_RCC_APB1ENR, 9, 1677 CLK_SET_RATE_PARENT 1678 }, 1679 { 1680 CLK_F769_DSI, "dsi", 1681 dsi_parent, ARRAY_SIZE(dsi_parent), 1682 STM32F7_RCC_DCKCFGR2, 0, 1, 1683 STM32F4_RCC_APB2ENR, 27, 1684 CLK_SET_RATE_PARENT 1685 }, 1686 { 1687 CLK_DFSDM1, "dfsdm1", 1688 dfsdm1_src, ARRAY_SIZE(dfsdm1_src), 1689 STM32F4_RCC_DCKCFGR, 25, 1, 1690 STM32F4_RCC_APB2ENR, 29, 1691 CLK_SET_RATE_PARENT 1692 }, 1693 { 1694 CLK_ADFSDM1, "adfsdm1", 1695 adsfdm1_parent, ARRAY_SIZE(adsfdm1_parent), 1696 STM32F4_RCC_DCKCFGR, 26, 1, 1697 STM32F4_RCC_APB2ENR, 29, 1698 CLK_SET_RATE_PARENT 1699 }, 1700 }; 1701 1702 static const struct stm32f4_clk_data stm32f429_clk_data = { 1703 .end_primary = END_PRIMARY_CLK, 1704 .gates_data = stm32f429_gates, 1705 .gates_map = stm32f42xx_gate_map, 1706 .gates_num = ARRAY_SIZE(stm32f429_gates), 1707 .pll_data = stm32f429_pll, 1708 .aux_clk = stm32f429_aux_clk, 1709 .aux_clk_num = ARRAY_SIZE(stm32f429_aux_clk), 1710 }; 1711 1712 static const struct stm32f4_clk_data stm32f469_clk_data = { 1713 .end_primary = END_PRIMARY_CLK, 1714 .gates_data = stm32f469_gates, 1715 .gates_map = stm32f46xx_gate_map, 1716 .gates_num = ARRAY_SIZE(stm32f469_gates), 1717 .pll_data = stm32f469_pll, 1718 .aux_clk = stm32f469_aux_clk, 1719 .aux_clk_num = ARRAY_SIZE(stm32f469_aux_clk), 1720 }; 1721 1722 static const struct stm32f4_clk_data stm32f746_clk_data = { 1723 .end_primary = END_PRIMARY_CLK_F7, 1724 .gates_data = stm32f746_gates, 1725 .gates_map = stm32f746_gate_map, 1726 .gates_num = ARRAY_SIZE(stm32f746_gates), 1727 .pll_data = stm32f469_pll, 1728 .aux_clk = stm32f746_aux_clk, 1729 .aux_clk_num = ARRAY_SIZE(stm32f746_aux_clk), 1730 }; 1731 1732 static const struct stm32f4_clk_data stm32f769_clk_data = { 1733 .end_primary = END_PRIMARY_CLK_F7, 1734 .gates_data = stm32f769_gates, 1735 .gates_map = stm32f769_gate_map, 1736 .gates_num = ARRAY_SIZE(stm32f769_gates), 1737 .pll_data = stm32f469_pll, 1738 .aux_clk = stm32f769_aux_clk, 1739 .aux_clk_num = ARRAY_SIZE(stm32f769_aux_clk), 1740 }; 1741 1742 static const struct of_device_id stm32f4_of_match[] = { 1743 { 1744 .compatible = "st,stm32f42xx-rcc", 1745 .data = &stm32f429_clk_data 1746 }, 1747 { 1748 .compatible = "st,stm32f469-rcc", 1749 .data = &stm32f469_clk_data 1750 }, 1751 { 1752 .compatible = "st,stm32f746-rcc", 1753 .data = &stm32f746_clk_data 1754 }, 1755 { 1756 .compatible = "st,stm32f769-rcc", 1757 .data = &stm32f769_clk_data 1758 }, 1759 {} 1760 }; 1761 1762 static struct clk_hw *stm32_register_aux_clk(const char *name, 1763 const char * const *parent_names, int num_parents, 1764 int offset_mux, u8 shift, u8 mask, 1765 int offset_gate, u8 bit_idx, 1766 unsigned long flags, spinlock_t *lock) 1767 { 1768 struct clk_hw *hw; 1769 struct clk_gate *gate = NULL; 1770 struct clk_mux *mux = NULL; 1771 struct clk_hw *mux_hw = NULL, *gate_hw = NULL; 1772 const struct clk_ops *mux_ops = NULL, *gate_ops = NULL; 1773 1774 if (offset_gate != NO_GATE) { 1775 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 1776 if (!gate) { 1777 hw = ERR_PTR(-EINVAL); 1778 goto fail; 1779 } 1780 1781 gate->reg = base + offset_gate; 1782 gate->bit_idx = bit_idx; 1783 gate->flags = 0; 1784 gate->lock = lock; 1785 gate_hw = &gate->hw; 1786 gate_ops = &clk_gate_ops; 1787 } 1788 1789 if (offset_mux != NO_MUX) { 1790 mux = kzalloc(sizeof(*mux), GFP_KERNEL); 1791 if (!mux) { 1792 hw = ERR_PTR(-EINVAL); 1793 goto fail; 1794 } 1795 1796 mux->reg = base + offset_mux; 1797 mux->shift = shift; 1798 mux->mask = mask; 1799 mux->flags = 0; 1800 mux_hw = &mux->hw; 1801 mux_ops = &clk_mux_ops; 1802 } 1803 1804 if (mux_hw == NULL && gate_hw == NULL) { 1805 hw = ERR_PTR(-EINVAL); 1806 goto fail; 1807 } 1808 1809 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, 1810 mux_hw, mux_ops, 1811 NULL, NULL, 1812 gate_hw, gate_ops, 1813 flags); 1814 1815 fail: 1816 if (IS_ERR(hw)) { 1817 kfree(gate); 1818 kfree(mux); 1819 } 1820 1821 return hw; 1822 } 1823 1824 static void __init stm32f4_rcc_init(struct device_node *np) 1825 { 1826 const char *hse_clk, *i2s_in_clk; 1827 int n; 1828 const struct of_device_id *match; 1829 const struct stm32f4_clk_data *data; 1830 unsigned long pllm; 1831 struct clk_hw *pll_src_hw, *pll_vco_hw; 1832 struct stm32f4_pll_ssc ssc_conf; 1833 1834 base = of_iomap(np, 0); 1835 if (!base) { 1836 pr_err("%pOFn: unable to map resource\n", np); 1837 return; 1838 } 1839 1840 pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1841 if (IS_ERR(pdrm)) { 1842 pdrm = NULL; 1843 pr_warn("%s: Unable to get syscfg\n", __func__); 1844 } 1845 1846 match = of_match_node(stm32f4_of_match, np); 1847 if (WARN_ON(!match)) 1848 return; 1849 1850 data = match->data; 1851 1852 stm32fx_end_primary_clk = data->end_primary; 1853 1854 clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk, 1855 sizeof(*clks), GFP_KERNEL); 1856 if (!clks) 1857 goto fail; 1858 1859 stm32f4_gate_map = data->gates_map; 1860 1861 hse_clk = of_clk_get_parent_name(np, 0); 1862 dsi_parent[0] = hse_clk; 1863 pllsrc_parent[1] = hse_clk; 1864 1865 i2s_in_clk = of_clk_get_parent_name(np, 1); 1866 1867 i2s_parents[1] = i2s_in_clk; 1868 sai_parents[2] = i2s_in_clk; 1869 1870 if (of_device_is_compatible(np, "st,stm32f769-rcc")) { 1871 clk_hw_register_gate(NULL, "dfsdm1_apb", "apb2_div", 0, 1872 base + STM32F4_RCC_APB2ENR, 29, 1873 CLK_IGNORE_UNUSED, &stm32f4_clk_lock); 1874 dsi_parent[0] = pll_src; 1875 sai_parents[3] = pll_src; 1876 } 1877 1878 clks[CLK_HSI] = clk_hw_register_fixed_rate_with_accuracy(NULL, "hsi", 1879 NULL, 0, 16000000, 160000); 1880 1881 pll_src_hw = clk_hw_register_mux(NULL, pll_src, pllsrc_parent, 1882 ARRAY_SIZE(pllsrc_parent), 0, 1883 base + STM32F4_RCC_PLLCFGR, 22, 1, 0, 1884 &stm32f4_clk_lock); 1885 1886 pllm = readl(base + STM32F4_RCC_PLLCFGR) & 0x3f; 1887 1888 clk_hw_register_fixed_factor(NULL, "vco_in", pll_src, 1889 0, 1, pllm); 1890 1891 pll_vco_hw = stm32f4_rcc_register_pll("vco_in", &data->pll_data[0], 1892 &stm32f4_clk_lock); 1893 1894 clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in", 1895 &data->pll_data[1], &stm32f4_clk_lock); 1896 1897 clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in", 1898 &data->pll_data[2], &stm32f4_clk_lock); 1899 1900 for (n = 0; n < MAX_POST_DIV; n++) { 1901 const struct stm32f4_pll_post_div_data *post_div; 1902 struct clk_hw *hw; 1903 1904 post_div = &post_div_data[n]; 1905 1906 hw = clk_register_pll_div(post_div->name, 1907 post_div->parent, 1908 post_div->flag, 1909 base + post_div->offset, 1910 post_div->shift, 1911 post_div->width, 1912 post_div->flag_div, 1913 post_div->div_table, 1914 clks[post_div->pll_idx], 1915 &stm32f4_clk_lock); 1916 1917 if (post_div->idx != NO_IDX) 1918 clks[post_div->idx] = hw; 1919 } 1920 1921 sys_parents[1] = hse_clk; 1922 1923 clks[CLK_SYSCLK] = clk_hw_register_mux_table( 1924 NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0, 1925 base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock); 1926 1927 clk_register_divider_table(NULL, "ahb_div", "sys", 1928 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, 1929 4, 4, 0, ahb_div_table, &stm32f4_clk_lock); 1930 1931 clk_register_divider_table(NULL, "apb1_div", "ahb_div", 1932 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, 1933 10, 3, 0, apb_div_table, &stm32f4_clk_lock); 1934 clk_register_apb_mul(NULL, "apb1_mul", "apb1_div", 1935 CLK_SET_RATE_PARENT, 12); 1936 1937 clk_register_divider_table(NULL, "apb2_div", "ahb_div", 1938 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, 1939 13, 3, 0, apb_div_table, &stm32f4_clk_lock); 1940 clk_register_apb_mul(NULL, "apb2_mul", "apb2_div", 1941 CLK_SET_RATE_PARENT, 15); 1942 1943 clks[SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick", "ahb_div", 1944 0, 1, 8); 1945 clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div", 1946 0, 1, 1); 1947 1948 for (n = 0; n < data->gates_num; n++) { 1949 const struct stm32f4_gate_data *gd; 1950 unsigned int secondary; 1951 int idx; 1952 1953 gd = &data->gates_data[n]; 1954 secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) + 1955 gd->bit_idx; 1956 idx = stm32f4_rcc_lookup_clk_idx(0, secondary); 1957 1958 if (idx < 0) 1959 goto fail; 1960 1961 clks[idx] = clk_hw_register_gate( 1962 NULL, gd->name, gd->parent_name, gd->flags, 1963 base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock); 1964 1965 if (IS_ERR(clks[idx])) { 1966 pr_err("%pOF: Unable to register leaf clock %s\n", 1967 np, gd->name); 1968 goto fail; 1969 } 1970 } 1971 1972 clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0, 1973 base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock); 1974 1975 if (IS_ERR(clks[CLK_LSI])) { 1976 pr_err("Unable to register lsi clock\n"); 1977 goto fail; 1978 } 1979 1980 clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0, 1981 base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock); 1982 1983 if (IS_ERR(clks[CLK_LSE])) { 1984 pr_err("Unable to register lse clock\n"); 1985 goto fail; 1986 } 1987 1988 clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse", 1989 0, base + STM32F4_RCC_CFGR, 16, 5, 0, 1990 &stm32f4_clk_lock); 1991 1992 if (IS_ERR(clks[CLK_HSE_RTC])) { 1993 pr_err("Unable to register hse-rtc clock\n"); 1994 goto fail; 1995 } 1996 1997 clks[CLK_RTC] = stm32_register_cclk(NULL, "rtc", rtc_parents, 4, 1998 base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock); 1999 2000 if (IS_ERR(clks[CLK_RTC])) { 2001 pr_err("Unable to register rtc clock\n"); 2002 goto fail; 2003 } 2004 2005 for (n = 0; n < data->aux_clk_num; n++) { 2006 const struct stm32_aux_clk *aux_clk; 2007 struct clk_hw *hw; 2008 2009 aux_clk = &data->aux_clk[n]; 2010 2011 hw = stm32_register_aux_clk(aux_clk->name, 2012 aux_clk->parent_names, aux_clk->num_parents, 2013 aux_clk->offset_mux, aux_clk->shift, 2014 aux_clk->mask, aux_clk->offset_gate, 2015 aux_clk->bit_idx, aux_clk->flags, 2016 &stm32f4_clk_lock); 2017 2018 if (IS_ERR(hw)) { 2019 pr_warn("Unable to register %s clk\n", aux_clk->name); 2020 continue; 2021 } 2022 2023 if (aux_clk->idx != NO_IDX) 2024 clks[aux_clk->idx] = hw; 2025 } 2026 2027 if (of_device_is_compatible(np, "st,stm32f746-rcc")) { 2028 2029 clk_hw_register_fixed_factor(NULL, "hsi_div488", "hsi", 0, 2030 1, 488); 2031 2032 clks[CLK_PLL_SRC] = pll_src_hw; 2033 } 2034 2035 of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL); 2036 2037 if (!stm32f4_pll_ssc_parse_dt(np, &ssc_conf)) 2038 stm32f4_pll_init_ssc(pll_vco_hw, &ssc_conf); 2039 2040 return; 2041 fail: 2042 kfree(clks); 2043 iounmap(base); 2044 } 2045 CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init); 2046 CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init); 2047 CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init); 2048 CLK_OF_DECLARE_DRIVER(stm32f769_rcc, "st,stm32f769-rcc", stm32f4_rcc_init); 2049