1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Silicon Labs Si544/Si549 Programmable Oscillator 4 * Copyright (C) 2018 Topic Embedded Products 5 * Author: Mike Looijmans <mike.looijmans@topic.nl> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/math64.h> 11 #include <linux/module.h> 12 #include <linux/i2c.h> 13 #include <linux/regmap.h> 14 #include <linux/slab.h> 15 16 /* I2C registers (decimal as in datasheet) */ 17 #define SI544_REG_CONTROL 7 18 #define SI544_REG_OE_STATE 17 19 #define SI544_REG_HS_DIV 23 20 #define SI544_REG_LS_HS_DIV 24 21 #define SI544_REG_FBDIV0 26 22 #define SI544_REG_FBDIV8 27 23 #define SI544_REG_FBDIV16 28 24 #define SI544_REG_FBDIV24 29 25 #define SI544_REG_FBDIV32 30 26 #define SI544_REG_FBDIV40 31 27 #define SI544_REG_FCAL_OVR 69 28 #define SI544_REG_ADPLL_DELTA_M0 231 29 #define SI544_REG_ADPLL_DELTA_M8 232 30 #define SI544_REG_ADPLL_DELTA_M16 233 31 #define SI544_REG_PAGE_SELECT 255 32 33 /* Register values */ 34 #define SI544_CONTROL_RESET BIT(7) 35 #define SI544_CONTROL_MS_ICAL2 BIT(3) 36 37 #define SI544_OE_STATE_ODC_OE BIT(0) 38 39 /* Max freq depends on speed grade */ 40 #define SI544_MIN_FREQ 200000U 41 42 /* Si544 Internal oscillator runs at 55.05 MHz */ 43 #define SI544_XO_FREQ 55050000U 44 /* Si549 Internal oscilator runs at 152.60 MHz */ 45 #define SI549_XO_FREQ 152600000U 46 47 /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */ 48 #define FVCO_MIN 10800000000ULL 49 50 #define HS_DIV_MAX 2046 51 #define HS_DIV_MAX_ODD 33 52 53 /* Lowest frequency synthesizeable using only the HS divider */ 54 #define MIN_HSDIV_FREQ (FVCO_MIN / HS_DIV_MAX) 55 56 /* Range and interpretation of the adjustment value */ 57 #define DELTA_M_MAX 8161512 58 #define DELTA_M_FRAC_NUM 19 59 #define DELTA_M_FRAC_DEN 20000 60 61 struct si544_clk_desc { 62 unsigned long max_freq; 63 unsigned long xo_freq; 64 }; 65 66 struct clk_si544 { 67 struct clk_hw hw; 68 struct regmap *regmap; 69 struct i2c_client *i2c_client; 70 const struct si544_clk_desc *chip_info; 71 }; 72 #define to_clk_si544(_hw) container_of(_hw, struct clk_si544, hw) 73 74 /** 75 * struct clk_si544_muldiv - Multiplier/divider settings 76 * @fb_div_frac: integer part of feedback divider (32 bits) 77 * @fb_div_int: fractional part of feedback divider (11 bits) 78 * @hs_div: 1st divider, 5..2046, must be even when >33 79 * @ls_div_bits: 2nd divider, as 2^x, range 0..5 80 * If ls_div_bits is non-zero, hs_div must be even 81 * @delta_m: Frequency shift for small -950..+950 ppm changes, 24 bit 82 */ 83 struct clk_si544_muldiv { 84 u32 fb_div_frac; 85 u16 fb_div_int; 86 u16 hs_div; 87 u8 ls_div_bits; 88 s32 delta_m; 89 u32 xo_freq; 90 }; 91 92 /* Enables or disables the output driver */ 93 static int si544_enable_output(struct clk_si544 *data, bool enable) 94 { 95 return regmap_update_bits(data->regmap, SI544_REG_OE_STATE, 96 SI544_OE_STATE_ODC_OE, enable ? SI544_OE_STATE_ODC_OE : 0); 97 } 98 99 static int si544_prepare(struct clk_hw *hw) 100 { 101 struct clk_si544 *data = to_clk_si544(hw); 102 103 return si544_enable_output(data, true); 104 } 105 106 static void si544_unprepare(struct clk_hw *hw) 107 { 108 struct clk_si544 *data = to_clk_si544(hw); 109 110 si544_enable_output(data, false); 111 } 112 113 static int si544_is_prepared(struct clk_hw *hw) 114 { 115 struct clk_si544 *data = to_clk_si544(hw); 116 unsigned int val; 117 int err; 118 119 err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val); 120 if (err < 0) 121 return err; 122 123 return !!(val & SI544_OE_STATE_ODC_OE); 124 } 125 126 /* Retrieve clock multiplier and dividers from hardware */ 127 static int si544_get_muldiv(struct clk_si544 *data, 128 struct clk_si544_muldiv *settings) 129 { 130 int err; 131 u8 reg[6]; 132 133 err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2); 134 if (err) 135 return err; 136 137 settings->ls_div_bits = (reg[1] >> 4) & 0x07; 138 settings->hs_div = (reg[1] & 0x07) << 8 | reg[0]; 139 140 err = regmap_bulk_read(data->regmap, SI544_REG_FBDIV0, reg, 6); 141 if (err) 142 return err; 143 144 settings->fb_div_int = reg[4] | (reg[5] & 0x07) << 8; 145 settings->fb_div_frac = reg[0] | reg[1] << 8 | reg[2] << 16 | 146 reg[3] << 24; 147 148 err = regmap_bulk_read(data->regmap, SI544_REG_ADPLL_DELTA_M0, reg, 3); 149 if (err) 150 return err; 151 152 /* Interpret as 24-bit signed number */ 153 settings->delta_m = reg[0] << 8 | reg[1] << 16 | reg[2] << 24; 154 settings->delta_m >>= 8; 155 156 settings->xo_freq = data->chip_info->xo_freq; 157 158 return 0; 159 } 160 161 static int si544_set_delta_m(struct clk_si544 *data, s32 delta_m) 162 { 163 u8 reg[3]; 164 165 reg[0] = delta_m; 166 reg[1] = delta_m >> 8; 167 reg[2] = delta_m >> 16; 168 169 return regmap_bulk_write(data->regmap, SI544_REG_ADPLL_DELTA_M0, 170 reg, 3); 171 } 172 173 static int si544_set_muldiv(struct clk_si544 *data, 174 struct clk_si544_muldiv *settings) 175 { 176 int err; 177 u8 reg[6]; 178 179 reg[0] = settings->hs_div; 180 reg[1] = settings->hs_div >> 8 | settings->ls_div_bits << 4; 181 182 err = regmap_bulk_write(data->regmap, SI544_REG_HS_DIV, reg, 2); 183 if (err < 0) 184 return err; 185 186 reg[0] = settings->fb_div_frac; 187 reg[1] = settings->fb_div_frac >> 8; 188 reg[2] = settings->fb_div_frac >> 16; 189 reg[3] = settings->fb_div_frac >> 24; 190 reg[4] = settings->fb_div_int; 191 reg[5] = settings->fb_div_int >> 8; 192 193 /* 194 * Writing to SI544_REG_FBDIV40 triggers the clock change, so that 195 * must be written last 196 */ 197 return regmap_bulk_write(data->regmap, SI544_REG_FBDIV0, reg, 6); 198 } 199 200 static bool is_valid_frequency(const struct clk_si544 *data, 201 unsigned long frequency) 202 { 203 if (frequency < SI544_MIN_FREQ) 204 return false; 205 206 return frequency <= data->chip_info->max_freq; 207 } 208 209 /* Calculate divider settings for a given frequency */ 210 static int si544_calc_muldiv(struct clk_si544_muldiv *settings, 211 unsigned long frequency) 212 { 213 u64 vco; 214 u32 fxo = settings->xo_freq; 215 u32 ls_freq; 216 u32 tmp; 217 u8 res; 218 219 /* Determine the minimum value of LS_DIV and resulting target freq. */ 220 ls_freq = frequency; 221 settings->ls_div_bits = 0; 222 223 if (frequency >= MIN_HSDIV_FREQ) { 224 settings->ls_div_bits = 0; 225 } else { 226 res = 1; 227 tmp = 2 * HS_DIV_MAX; 228 while (tmp <= (HS_DIV_MAX * 32)) { 229 if (((u64)frequency * tmp) >= FVCO_MIN) 230 break; 231 ++res; 232 tmp <<= 1; 233 } 234 settings->ls_div_bits = res; 235 ls_freq = frequency << res; 236 } 237 238 /* Determine minimum HS_DIV by rounding up */ 239 vco = FVCO_MIN + ls_freq - 1; 240 do_div(vco, ls_freq); 241 settings->hs_div = vco; 242 243 /* round up to even number when required */ 244 if ((settings->hs_div & 1) && 245 (settings->hs_div > HS_DIV_MAX_ODD || settings->ls_div_bits)) 246 ++settings->hs_div; 247 248 /* Calculate VCO frequency (in 10..12GHz range) */ 249 vco = (u64)ls_freq * settings->hs_div; 250 251 /* Calculate the integer part of the feedback divider */ 252 tmp = do_div(vco, fxo); 253 settings->fb_div_int = vco; 254 255 /* And the fractional bits using the remainder */ 256 vco = (u64)tmp << 32; 257 vco += fxo / 2; /* Round to nearest multiple */ 258 do_div(vco, fxo); 259 settings->fb_div_frac = vco; 260 261 /* Reset the frequency adjustment */ 262 settings->delta_m = 0; 263 264 return 0; 265 } 266 267 /* Calculate resulting frequency given the register settings */ 268 static unsigned long si544_calc_center_rate( 269 const struct clk_si544_muldiv *settings) 270 { 271 u32 d = settings->hs_div * BIT(settings->ls_div_bits); 272 u32 fxo = settings->xo_freq; 273 u64 vco; 274 275 /* Calculate VCO from the fractional part */ 276 vco = (u64)settings->fb_div_frac * fxo; 277 vco += (fxo / 2); 278 vco >>= 32; 279 280 /* Add the integer part of the VCO frequency */ 281 vco += (u64)settings->fb_div_int * fxo; 282 283 /* Apply divider to obtain the generated frequency */ 284 do_div(vco, d); 285 286 return vco; 287 } 288 289 static unsigned long si544_calc_rate(const struct clk_si544_muldiv *settings) 290 { 291 unsigned long rate = si544_calc_center_rate(settings); 292 s64 delta = (s64)rate * (DELTA_M_FRAC_NUM * settings->delta_m); 293 294 /* 295 * The clock adjustment is much smaller than 1 Hz, round to the 296 * nearest multiple. Apparently div64_s64 rounds towards zero, hence 297 * check the sign and adjust into the proper direction. 298 */ 299 if (settings->delta_m < 0) 300 delta -= ((s64)DELTA_M_MAX * DELTA_M_FRAC_DEN) / 2; 301 else 302 delta += ((s64)DELTA_M_MAX * DELTA_M_FRAC_DEN) / 2; 303 delta = div64_s64(delta, ((s64)DELTA_M_MAX * DELTA_M_FRAC_DEN)); 304 305 return rate + delta; 306 } 307 308 static unsigned long si544_recalc_rate(struct clk_hw *hw, 309 unsigned long parent_rate) 310 { 311 struct clk_si544 *data = to_clk_si544(hw); 312 struct clk_si544_muldiv settings; 313 int err; 314 315 err = si544_get_muldiv(data, &settings); 316 if (err) 317 return 0; 318 319 return si544_calc_rate(&settings); 320 } 321 322 static int si544_determine_rate(struct clk_hw *hw, 323 struct clk_rate_request *req) 324 { 325 struct clk_si544 *data = to_clk_si544(hw); 326 327 if (!is_valid_frequency(data, req->rate)) 328 return -EINVAL; 329 330 /* The accuracy is less than 1 Hz, so any rate is possible */ 331 return 0; 332 } 333 334 /* Calculates the maximum "small" change, 950 * rate / 1000000 */ 335 static unsigned long si544_max_delta(unsigned long rate) 336 { 337 u64 num = rate; 338 339 num *= DELTA_M_FRAC_NUM; 340 do_div(num, DELTA_M_FRAC_DEN); 341 342 return num; 343 } 344 345 static s32 si544_calc_delta(s32 delta, s32 max_delta) 346 { 347 s64 n = (s64)delta * DELTA_M_MAX; 348 349 return div_s64(n, max_delta); 350 } 351 352 static int si544_set_rate(struct clk_hw *hw, unsigned long rate, 353 unsigned long parent_rate) 354 { 355 struct clk_si544 *data = to_clk_si544(hw); 356 struct clk_si544_muldiv settings; 357 unsigned long center; 358 long max_delta; 359 long delta; 360 unsigned int old_oe_state; 361 int err; 362 363 if (!is_valid_frequency(data, rate)) 364 return -EINVAL; 365 366 /* Try using the frequency adjustment feature for a <= 950ppm change */ 367 err = si544_get_muldiv(data, &settings); 368 if (err) 369 return err; 370 371 center = si544_calc_center_rate(&settings); 372 max_delta = si544_max_delta(center); 373 delta = rate - center; 374 375 if (abs(delta) <= max_delta) 376 return si544_set_delta_m(data, 377 si544_calc_delta(delta, max_delta)); 378 379 /* Too big for the delta adjustment, need to reprogram */ 380 err = si544_calc_muldiv(&settings, rate); 381 if (err) 382 return err; 383 384 err = regmap_read(data->regmap, SI544_REG_OE_STATE, &old_oe_state); 385 if (err) 386 return err; 387 388 si544_enable_output(data, false); 389 390 /* Allow FCAL for this frequency update */ 391 err = regmap_write(data->regmap, SI544_REG_FCAL_OVR, 0); 392 if (err < 0) 393 return err; 394 395 err = si544_set_delta_m(data, settings.delta_m); 396 if (err < 0) 397 return err; 398 399 err = si544_set_muldiv(data, &settings); 400 if (err < 0) 401 return err; /* Undefined state now, best to leave disabled */ 402 403 /* Trigger calibration */ 404 err = regmap_write(data->regmap, SI544_REG_CONTROL, 405 SI544_CONTROL_MS_ICAL2); 406 if (err < 0) 407 return err; 408 409 /* Applying a new frequency can take up to 10ms */ 410 usleep_range(10000, 12000); 411 412 if (old_oe_state & SI544_OE_STATE_ODC_OE) 413 si544_enable_output(data, true); 414 415 return err; 416 } 417 418 static const struct clk_ops si544_clk_ops = { 419 .prepare = si544_prepare, 420 .unprepare = si544_unprepare, 421 .is_prepared = si544_is_prepared, 422 .recalc_rate = si544_recalc_rate, 423 .determine_rate = si544_determine_rate, 424 .set_rate = si544_set_rate, 425 }; 426 427 static bool si544_regmap_is_volatile(struct device *dev, unsigned int reg) 428 { 429 switch (reg) { 430 case SI544_REG_CONTROL: 431 case SI544_REG_FCAL_OVR: 432 return true; 433 default: 434 return false; 435 } 436 } 437 438 static const struct regmap_config si544_regmap_config = { 439 .reg_bits = 8, 440 .val_bits = 8, 441 .cache_type = REGCACHE_MAPLE, 442 .max_register = SI544_REG_PAGE_SELECT, 443 .volatile_reg = si544_regmap_is_volatile, 444 }; 445 446 static int si544_probe(struct i2c_client *client) 447 { 448 struct clk_si544 *data; 449 struct clk_init_data init; 450 int err; 451 452 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); 453 if (!data) 454 return -ENOMEM; 455 456 init.ops = &si544_clk_ops; 457 init.flags = 0; 458 init.num_parents = 0; 459 data->hw.init = &init; 460 data->i2c_client = client; 461 data->chip_info = i2c_get_match_data(client); 462 463 if (of_property_read_string(client->dev.of_node, "clock-output-names", 464 &init.name)) 465 init.name = client->dev.of_node->name; 466 467 data->regmap = devm_regmap_init_i2c(client, &si544_regmap_config); 468 if (IS_ERR(data->regmap)) 469 return PTR_ERR(data->regmap); 470 471 i2c_set_clientdata(client, data); 472 473 /* Select page 0, just to be sure, there appear to be no more */ 474 err = regmap_write(data->regmap, SI544_REG_PAGE_SELECT, 0); 475 if (err < 0) 476 return err; 477 478 err = devm_clk_hw_register(&client->dev, &data->hw); 479 if (err) { 480 dev_err(&client->dev, "clock registration failed\n"); 481 return err; 482 } 483 err = devm_of_clk_add_hw_provider(&client->dev, of_clk_hw_simple_get, 484 &data->hw); 485 if (err) { 486 dev_err(&client->dev, "unable to add clk provider\n"); 487 return err; 488 } 489 490 return 0; 491 } 492 493 static const struct si544_clk_desc clk_si544a_info = { 494 .xo_freq = SI544_XO_FREQ, 495 .max_freq = 1500000000, 496 }; 497 498 static const struct si544_clk_desc clk_si544b_info = { 499 .xo_freq = SI544_XO_FREQ, 500 .max_freq = 800000000, 501 }; 502 503 static const struct si544_clk_desc clk_si544c_info = { 504 .xo_freq = SI544_XO_FREQ, 505 .max_freq = 325000000, 506 }; 507 508 static const struct si544_clk_desc clk_si549a_info = { 509 .xo_freq = SI549_XO_FREQ, 510 .max_freq = 1500000000, 511 }; 512 513 static const struct si544_clk_desc clk_si549b_info = { 514 .xo_freq = SI549_XO_FREQ, 515 .max_freq = 800000000, 516 }; 517 518 static const struct si544_clk_desc clk_si549c_info = { 519 .xo_freq = SI549_XO_FREQ, 520 .max_freq = 325000000, 521 }; 522 523 static const struct i2c_device_id si544_id[] = { 524 { .name = "si544a", .driver_data = (kernel_ulong_t)&clk_si544a_info }, 525 { .name = "si544b", .driver_data = (kernel_ulong_t)&clk_si544b_info }, 526 { .name = "si544c", .driver_data = (kernel_ulong_t)&clk_si544c_info }, 527 { .name = "si549a", .driver_data = (kernel_ulong_t)&clk_si549a_info }, 528 { .name = "si549b", .driver_data = (kernel_ulong_t)&clk_si549b_info }, 529 { .name = "si549c", .driver_data = (kernel_ulong_t)&clk_si549c_info }, 530 { } 531 }; 532 MODULE_DEVICE_TABLE(i2c, si544_id); 533 534 static const struct of_device_id clk_si544_of_match[] = { 535 { .compatible = "silabs,si544a", .data = &clk_si544a_info }, 536 { .compatible = "silabs,si544b", .data = &clk_si544b_info }, 537 { .compatible = "silabs,si544c", .data = &clk_si544c_info }, 538 { .compatible = "silabs,si549a", .data = &clk_si549a_info }, 539 { .compatible = "silabs,si549b", .data = &clk_si549b_info }, 540 { .compatible = "silabs,si549c", .data = &clk_si549c_info }, 541 { } 542 }; 543 MODULE_DEVICE_TABLE(of, clk_si544_of_match); 544 545 static struct i2c_driver si544_driver = { 546 .driver = { 547 .name = "si544", 548 .of_match_table = clk_si544_of_match, 549 }, 550 .probe = si544_probe, 551 .id_table = si544_id, 552 }; 553 module_i2c_driver(si544_driver); 554 555 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); 556 MODULE_DESCRIPTION("Si544 driver"); 557 MODULE_LICENSE("GPL"); 558