1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Silicon Labs Si5341/Si5340 Clock generator 4 * Copyright (C) 2019 Topic Embedded Products 5 * Author: Mike Looijmans <mike.looijmans@topic.nl> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/gcd.h> 12 #include <linux/math64.h> 13 #include <linux/i2c.h> 14 #include <linux/module.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <asm/unaligned.h> 18 19 #define SI5341_MAX_NUM_OUTPUTS 10 20 #define SI5340_MAX_NUM_OUTPUTS 4 21 22 #define SI5341_NUM_SYNTH 5 23 #define SI5340_NUM_SYNTH 4 24 25 /* Range of the synthesizer fractional divider */ 26 #define SI5341_SYNTH_N_MIN 10 27 #define SI5341_SYNTH_N_MAX 4095 28 29 /* The chip can get its input clock from 3 input pins or an XTAL */ 30 31 /* There is one PLL running at 13500–14256 MHz */ 32 #define SI5341_PLL_VCO_MIN 13500000000ull 33 #define SI5341_PLL_VCO_MAX 14256000000ull 34 35 /* The 5 frequency synthesizers obtain their input from the PLL */ 36 struct clk_si5341_synth { 37 struct clk_hw hw; 38 struct clk_si5341 *data; 39 u8 index; 40 }; 41 #define to_clk_si5341_synth(_hw) \ 42 container_of(_hw, struct clk_si5341_synth, hw) 43 44 /* The output stages can be connected to any synth (full mux) */ 45 struct clk_si5341_output { 46 struct clk_hw hw; 47 struct clk_si5341 *data; 48 u8 index; 49 }; 50 #define to_clk_si5341_output(_hw) \ 51 container_of(_hw, struct clk_si5341_output, hw) 52 53 struct clk_si5341 { 54 struct clk_hw hw; 55 struct regmap *regmap; 56 struct i2c_client *i2c_client; 57 struct clk_si5341_synth synth[SI5341_NUM_SYNTH]; 58 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS]; 59 struct clk *pxtal; 60 const char *pxtal_name; 61 const u16 *reg_output_offset; 62 const u16 *reg_rdiv_offset; 63 u64 freq_vco; /* 13500–14256 MHz */ 64 u8 num_outputs; 65 u8 num_synth; 66 }; 67 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw) 68 69 struct clk_si5341_output_config { 70 u8 out_format_drv_bits; 71 u8 out_cm_ampl_bits; 72 bool synth_master; 73 bool always_on; 74 }; 75 76 #define SI5341_PAGE 0x0001 77 #define SI5341_PN_BASE 0x0002 78 #define SI5341_DEVICE_REV 0x0005 79 #define SI5341_STATUS 0x000C 80 #define SI5341_SOFT_RST 0x001C 81 82 /* Input dividers (48-bit) */ 83 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10)) 84 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10)) 85 86 /* PLL configuration */ 87 #define SI5341_PLL_M_NUM 0x0235 88 #define SI5341_PLL_M_DEN 0x023B 89 90 /* Output configuration */ 91 #define SI5341_OUT_CONFIG(output) \ 92 ((output)->data->reg_output_offset[(output)->index]) 93 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1) 94 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2) 95 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3) 96 #define SI5341_OUT_R_REG(output) \ 97 ((output)->data->reg_rdiv_offset[(output)->index]) 98 99 /* Synthesize N divider */ 100 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11)) 101 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11)) 102 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11)) 103 104 /* Synthesizer output enable, phase bypass, power mode */ 105 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03 106 #define SI5341_SYNTH_N_PIBYP 0x0A04 107 #define SI5341_SYNTH_N_PDNB 0x0A05 108 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A 109 110 #define SI5341_REGISTER_MAX 0xBFF 111 112 /* SI5341_OUT_CONFIG bits */ 113 #define SI5341_OUT_CFG_PDN BIT(0) 114 #define SI5341_OUT_CFG_OE BIT(1) 115 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2) 116 117 /* Static configuration (to be moved to firmware) */ 118 struct si5341_reg_default { 119 u16 address; 120 u8 value; 121 }; 122 123 /* Output configuration registers 0..9 are not quite logically organized */ 124 static const u16 si5341_reg_output_offset[] = { 125 0x0108, 126 0x010D, 127 0x0112, 128 0x0117, 129 0x011C, 130 0x0121, 131 0x0126, 132 0x012B, 133 0x0130, 134 0x013A, 135 }; 136 137 static const u16 si5340_reg_output_offset[] = { 138 0x0112, 139 0x0117, 140 0x0126, 141 0x012B, 142 }; 143 144 /* The location of the R divider registers */ 145 static const u16 si5341_reg_rdiv_offset[] = { 146 0x024A, 147 0x024D, 148 0x0250, 149 0x0253, 150 0x0256, 151 0x0259, 152 0x025C, 153 0x025F, 154 0x0262, 155 0x0268, 156 }; 157 static const u16 si5340_reg_rdiv_offset[] = { 158 0x0250, 159 0x0253, 160 0x025C, 161 0x025F, 162 }; 163 164 /* 165 * Programming sequence from ClockBuilder, settings to initialize the system 166 * using only the XTAL input, without pre-divider. 167 * This also contains settings that aren't mentioned anywhere in the datasheet. 168 * The "known" settings like synth and output configuration are done later. 169 */ 170 static const struct si5341_reg_default si5341_reg_defaults[] = { 171 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */ 172 { 0x0018, 0xFF }, /* INT mask */ 173 { 0x0021, 0x0F }, /* Select XTAL as input */ 174 { 0x0022, 0x00 }, /* Not in datasheet */ 175 { 0x002B, 0x02 }, /* SPI config */ 176 { 0x002C, 0x20 }, /* LOS enable for XTAL */ 177 { 0x002D, 0x00 }, /* LOS timing */ 178 { 0x002E, 0x00 }, 179 { 0x002F, 0x00 }, 180 { 0x0030, 0x00 }, 181 { 0x0031, 0x00 }, 182 { 0x0032, 0x00 }, 183 { 0x0033, 0x00 }, 184 { 0x0034, 0x00 }, 185 { 0x0035, 0x00 }, 186 { 0x0036, 0x00 }, 187 { 0x0037, 0x00 }, 188 { 0x0038, 0x00 }, /* LOS setting (thresholds) */ 189 { 0x0039, 0x00 }, 190 { 0x003A, 0x00 }, 191 { 0x003B, 0x00 }, 192 { 0x003C, 0x00 }, 193 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */ 194 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */ 195 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */ 196 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */ 197 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */ 198 { 0x009E, 0x00 }, /* Not in datasheet */ 199 { 0x0102, 0x01 }, /* Enable outputs */ 200 { 0x013F, 0x00 }, /* Not in datasheet */ 201 { 0x0140, 0x00 }, /* Not in datasheet */ 202 { 0x0141, 0x40 }, /* OUT LOS */ 203 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/ 204 { 0x0203, 0x00 }, 205 { 0x0204, 0x00 }, 206 { 0x0205, 0x00 }, 207 { 0x0206, 0x00 }, /* PXAXB (2^x) */ 208 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */ 209 { 0x0209, 0x00 }, 210 { 0x020A, 0x00 }, 211 { 0x020B, 0x00 }, 212 { 0x020C, 0x00 }, 213 { 0x020D, 0x00 }, 214 { 0x020E, 0x00 }, 215 { 0x020F, 0x00 }, 216 { 0x0210, 0x00 }, 217 { 0x0211, 0x00 }, 218 { 0x0212, 0x00 }, 219 { 0x0213, 0x00 }, 220 { 0x0214, 0x00 }, 221 { 0x0215, 0x00 }, 222 { 0x0216, 0x00 }, 223 { 0x0217, 0x00 }, 224 { 0x0218, 0x00 }, 225 { 0x0219, 0x00 }, 226 { 0x021A, 0x00 }, 227 { 0x021B, 0x00 }, 228 { 0x021C, 0x00 }, 229 { 0x021D, 0x00 }, 230 { 0x021E, 0x00 }, 231 { 0x021F, 0x00 }, 232 { 0x0220, 0x00 }, 233 { 0x0221, 0x00 }, 234 { 0x0222, 0x00 }, 235 { 0x0223, 0x00 }, 236 { 0x0224, 0x00 }, 237 { 0x0225, 0x00 }, 238 { 0x0226, 0x00 }, 239 { 0x0227, 0x00 }, 240 { 0x0228, 0x00 }, 241 { 0x0229, 0x00 }, 242 { 0x022A, 0x00 }, 243 { 0x022B, 0x00 }, 244 { 0x022C, 0x00 }, 245 { 0x022D, 0x00 }, 246 { 0x022E, 0x00 }, 247 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */ 248 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */ 249 { 0x026C, 0x00 }, 250 { 0x026D, 0x00 }, 251 { 0x026E, 0x00 }, 252 { 0x026F, 0x00 }, 253 { 0x0270, 0x00 }, 254 { 0x0271, 0x00 }, 255 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */ 256 { 0x0339, 0x1F }, /* N_FSTEP_MSK */ 257 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */ 258 { 0x033C, 0x00 }, 259 { 0x033D, 0x00 }, 260 { 0x033E, 0x00 }, 261 { 0x033F, 0x00 }, 262 { 0x0340, 0x00 }, 263 { 0x0341, 0x00 }, 264 { 0x0342, 0x00 }, 265 { 0x0343, 0x00 }, 266 { 0x0344, 0x00 }, 267 { 0x0345, 0x00 }, 268 { 0x0346, 0x00 }, 269 { 0x0347, 0x00 }, 270 { 0x0348, 0x00 }, 271 { 0x0349, 0x00 }, 272 { 0x034A, 0x00 }, 273 { 0x034B, 0x00 }, 274 { 0x034C, 0x00 }, 275 { 0x034D, 0x00 }, 276 { 0x034E, 0x00 }, 277 { 0x034F, 0x00 }, 278 { 0x0350, 0x00 }, 279 { 0x0351, 0x00 }, 280 { 0x0352, 0x00 }, 281 { 0x0353, 0x00 }, 282 { 0x0354, 0x00 }, 283 { 0x0355, 0x00 }, 284 { 0x0356, 0x00 }, 285 { 0x0357, 0x00 }, 286 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */ 287 { 0x0359, 0x00 }, /* Nx_DELAY */ 288 { 0x035A, 0x00 }, 289 { 0x035B, 0x00 }, 290 { 0x035C, 0x00 }, 291 { 0x035D, 0x00 }, 292 { 0x035E, 0x00 }, 293 { 0x035F, 0x00 }, 294 { 0x0360, 0x00 }, 295 { 0x0361, 0x00 }, 296 { 0x0362, 0x00 }, /* Nx_DELAY end */ 297 { 0x0802, 0x00 }, /* Not in datasheet */ 298 { 0x0803, 0x00 }, /* Not in datasheet */ 299 { 0x0804, 0x00 }, /* Not in datasheet */ 300 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */ 301 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */ 302 { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */ 303 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */ 304 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */ 305 { 0x0A02, 0x00 }, /* Not in datasheet */ 306 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */ 307 }; 308 309 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */ 310 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg, 311 u64 *val1, u32 *val2) 312 { 313 int err; 314 u8 r[10]; 315 316 err = regmap_bulk_read(regmap, reg, r, 10); 317 if (err < 0) 318 return err; 319 320 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) | 321 (get_unaligned_le32(r)); 322 *val2 = get_unaligned_le32(&r[6]); 323 324 return 0; 325 } 326 327 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg, 328 u64 n_num, u32 n_den) 329 { 330 u8 r[10]; 331 332 /* Shift left as far as possible without overflowing */ 333 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) { 334 n_num <<= 1; 335 n_den <<= 1; 336 } 337 338 /* 44 bits (6 bytes) numerator */ 339 put_unaligned_le32(n_num, r); 340 r[4] = (n_num >> 32) & 0xff; 341 r[5] = (n_num >> 40) & 0x0f; 342 /* 32 bits denominator */ 343 put_unaligned_le32(n_den, &r[6]); 344 345 /* Program the fraction */ 346 return regmap_bulk_write(regmap, reg, r, sizeof(r)); 347 } 348 349 /* VCO, we assume it runs at a constant frequency */ 350 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw, 351 unsigned long parent_rate) 352 { 353 struct clk_si5341 *data = to_clk_si5341(hw); 354 int err; 355 u64 res; 356 u64 m_num; 357 u32 m_den; 358 unsigned int shift; 359 360 /* Assume that PDIV is not being used, just read the PLL setting */ 361 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM, 362 &m_num, &m_den); 363 if (err < 0) 364 return 0; 365 366 if (!m_num || !m_den) 367 return 0; 368 369 /* 370 * Though m_num is 64-bit, only the upper bits are actually used. While 371 * calculating m_num and m_den, they are shifted as far as possible to 372 * the left. To avoid 96-bit division here, we just shift them back so 373 * we can do with just 64 bits. 374 */ 375 shift = 0; 376 res = m_num; 377 while (res & 0xffff00000000ULL) { 378 ++shift; 379 res >>= 1; 380 } 381 res *= parent_rate; 382 do_div(res, (m_den >> shift)); 383 384 /* We cannot return the actual frequency in 32 bit, store it locally */ 385 data->freq_vco = res; 386 387 /* Report kHz since the value is out of range */ 388 do_div(res, 1000); 389 390 return (unsigned long)res; 391 } 392 393 static const struct clk_ops si5341_clk_ops = { 394 .recalc_rate = si5341_clk_recalc_rate, 395 }; 396 397 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */ 398 399 /* The synthesizer is on if all power and enable bits are set */ 400 static int si5341_synth_clk_is_on(struct clk_hw *hw) 401 { 402 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 403 int err; 404 u32 val; 405 u8 index = synth->index; 406 407 err = regmap_read(synth->data->regmap, 408 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val); 409 if (err < 0) 410 return 0; 411 412 if (!(val & BIT(index))) 413 return 0; 414 415 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val); 416 if (err < 0) 417 return 0; 418 419 if (!(val & BIT(index))) 420 return 0; 421 422 /* This bit must be 0 for the synthesizer to receive clock input */ 423 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val); 424 if (err < 0) 425 return 0; 426 427 return !(val & BIT(index)); 428 } 429 430 static void si5341_synth_clk_unprepare(struct clk_hw *hw) 431 { 432 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 433 u8 index = synth->index; /* In range 0..5 */ 434 u8 mask = BIT(index); 435 436 /* Disable output */ 437 regmap_update_bits(synth->data->regmap, 438 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0); 439 /* Power down */ 440 regmap_update_bits(synth->data->regmap, 441 SI5341_SYNTH_N_PDNB, mask, 0); 442 /* Disable clock input to synth (set to 1 to disable) */ 443 regmap_update_bits(synth->data->regmap, 444 SI5341_SYNTH_N_CLK_DIS, mask, mask); 445 } 446 447 static int si5341_synth_clk_prepare(struct clk_hw *hw) 448 { 449 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 450 int err; 451 u8 index = synth->index; 452 u8 mask = BIT(index); 453 454 /* Power up */ 455 err = regmap_update_bits(synth->data->regmap, 456 SI5341_SYNTH_N_PDNB, mask, mask); 457 if (err < 0) 458 return err; 459 460 /* Enable clock input to synth (set bit to 0 to enable) */ 461 err = regmap_update_bits(synth->data->regmap, 462 SI5341_SYNTH_N_CLK_DIS, mask, 0); 463 if (err < 0) 464 return err; 465 466 /* Enable output */ 467 return regmap_update_bits(synth->data->regmap, 468 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask); 469 } 470 471 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */ 472 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw, 473 unsigned long parent_rate) 474 { 475 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 476 u64 f; 477 u64 n_num; 478 u32 n_den; 479 int err; 480 481 err = si5341_decode_44_32(synth->data->regmap, 482 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den); 483 if (err < 0) 484 return err; 485 486 /* 487 * n_num and n_den are shifted left as much as possible, so to prevent 488 * overflow in 64-bit math, we shift n_den 4 bits to the right 489 */ 490 f = synth->data->freq_vco; 491 f *= n_den >> 4; 492 493 /* Now we need to to 64-bit division: f/n_num */ 494 /* And compensate for the 4 bits we dropped */ 495 f = div64_u64(f, (n_num >> 4)); 496 497 return f; 498 } 499 500 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate, 501 unsigned long *parent_rate) 502 { 503 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 504 u64 f; 505 506 /* The synthesizer accuracy is such that anything in range will work */ 507 f = synth->data->freq_vco; 508 do_div(f, SI5341_SYNTH_N_MAX); 509 if (rate < f) 510 return f; 511 512 f = synth->data->freq_vco; 513 do_div(f, SI5341_SYNTH_N_MIN); 514 if (rate > f) 515 return f; 516 517 return rate; 518 } 519 520 static int si5341_synth_program(struct clk_si5341_synth *synth, 521 u64 n_num, u32 n_den, bool is_integer) 522 { 523 int err; 524 u8 index = synth->index; 525 526 err = si5341_encode_44_32(synth->data->regmap, 527 SI5341_SYNTH_N_NUM(index), n_num, n_den); 528 529 err = regmap_update_bits(synth->data->regmap, 530 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0); 531 if (err < 0) 532 return err; 533 534 return regmap_write(synth->data->regmap, 535 SI5341_SYNTH_N_UPD(index), 0x01); 536 } 537 538 539 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate, 540 unsigned long parent_rate) 541 { 542 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 543 u64 n_num; 544 u32 n_den; 545 u32 r; 546 u32 g; 547 bool is_integer; 548 549 n_num = synth->data->freq_vco; 550 n_den = rate; 551 552 /* see if there's an integer solution */ 553 r = do_div(n_num, rate); 554 is_integer = (r == 0); 555 if (is_integer) { 556 /* Integer divider equal to n_num */ 557 n_den = 1; 558 } else { 559 /* Calculate a fractional solution */ 560 g = gcd(r, rate); 561 n_den = rate / g; 562 n_num *= n_den; 563 n_num += r / g; 564 } 565 566 dev_dbg(&synth->data->i2c_client->dev, 567 "%s(%u): n=0x%llx d=0x%x %s\n", __func__, 568 synth->index, n_num, n_den, 569 is_integer ? "int" : "frac"); 570 571 return si5341_synth_program(synth, n_num, n_den, is_integer); 572 } 573 574 static const struct clk_ops si5341_synth_clk_ops = { 575 .is_prepared = si5341_synth_clk_is_on, 576 .prepare = si5341_synth_clk_prepare, 577 .unprepare = si5341_synth_clk_unprepare, 578 .recalc_rate = si5341_synth_clk_recalc_rate, 579 .round_rate = si5341_synth_clk_round_rate, 580 .set_rate = si5341_synth_clk_set_rate, 581 }; 582 583 static int si5341_output_clk_is_on(struct clk_hw *hw) 584 { 585 struct clk_si5341_output *output = to_clk_si5341_output(hw); 586 int err; 587 u32 val; 588 589 err = regmap_read(output->data->regmap, 590 SI5341_OUT_CONFIG(output), &val); 591 if (err < 0) 592 return err; 593 594 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */ 595 return (val & 0x03) == SI5341_OUT_CFG_OE; 596 } 597 598 /* Disables and then powers down the output */ 599 static void si5341_output_clk_unprepare(struct clk_hw *hw) 600 { 601 struct clk_si5341_output *output = to_clk_si5341_output(hw); 602 603 regmap_update_bits(output->data->regmap, 604 SI5341_OUT_CONFIG(output), 605 SI5341_OUT_CFG_OE, 0); 606 regmap_update_bits(output->data->regmap, 607 SI5341_OUT_CONFIG(output), 608 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN); 609 } 610 611 /* Powers up and then enables the output */ 612 static int si5341_output_clk_prepare(struct clk_hw *hw) 613 { 614 struct clk_si5341_output *output = to_clk_si5341_output(hw); 615 int err; 616 617 err = regmap_update_bits(output->data->regmap, 618 SI5341_OUT_CONFIG(output), 619 SI5341_OUT_CFG_PDN, 0); 620 if (err < 0) 621 return err; 622 623 return regmap_update_bits(output->data->regmap, 624 SI5341_OUT_CONFIG(output), 625 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE); 626 } 627 628 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw, 629 unsigned long parent_rate) 630 { 631 struct clk_si5341_output *output = to_clk_si5341_output(hw); 632 int err; 633 u32 val; 634 u32 r_divider; 635 u8 r[3]; 636 637 err = regmap_bulk_read(output->data->regmap, 638 SI5341_OUT_R_REG(output), r, 3); 639 if (err < 0) 640 return err; 641 642 /* Calculate value as 24-bit integer*/ 643 r_divider = r[2] << 16 | r[1] << 8 | r[0]; 644 645 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */ 646 if (!r_divider) 647 return 0; 648 649 /* Divider is 2*(Rx_REG+1) */ 650 r_divider += 1; 651 r_divider <<= 1; 652 653 err = regmap_read(output->data->regmap, 654 SI5341_OUT_CONFIG(output), &val); 655 if (err < 0) 656 return err; 657 658 if (val & SI5341_OUT_CFG_RDIV_FORCE2) 659 r_divider = 2; 660 661 return parent_rate / r_divider; 662 } 663 664 static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate, 665 unsigned long *parent_rate) 666 { 667 unsigned long r; 668 669 r = *parent_rate >> 1; 670 671 /* If rate is an even divisor, no changes to parent required */ 672 if (r && !(r % rate)) 673 return (long)rate; 674 675 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { 676 if (rate > 200000000) { 677 /* minimum r-divider is 2 */ 678 r = 2; 679 } else { 680 /* Take a parent frequency near 400 MHz */ 681 r = (400000000u / rate) & ~1; 682 } 683 *parent_rate = r * rate; 684 } else { 685 /* We cannot change our parent's rate, report what we can do */ 686 r /= rate; 687 rate = *parent_rate / (r << 1); 688 } 689 690 return rate; 691 } 692 693 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate, 694 unsigned long parent_rate) 695 { 696 struct clk_si5341_output *output = to_clk_si5341_output(hw); 697 /* Frequency divider is (r_div + 1) * 2 */ 698 u32 r_div = (parent_rate / rate) >> 1; 699 int err; 700 u8 r[3]; 701 702 if (r_div <= 1) 703 r_div = 0; 704 else if (r_div >= BIT(24)) 705 r_div = BIT(24) - 1; 706 else 707 --r_div; 708 709 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */ 710 err = regmap_update_bits(output->data->regmap, 711 SI5341_OUT_CONFIG(output), 712 SI5341_OUT_CFG_RDIV_FORCE2, 713 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0); 714 if (err < 0) 715 return err; 716 717 /* Always write Rx_REG, because a zero value disables the divider */ 718 r[0] = r_div ? (r_div & 0xff) : 1; 719 r[1] = (r_div >> 8) & 0xff; 720 r[2] = (r_div >> 16) & 0xff; 721 err = regmap_bulk_write(output->data->regmap, 722 SI5341_OUT_R_REG(output), r, 3); 723 724 return 0; 725 } 726 727 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index) 728 { 729 return regmap_update_bits(output->data->regmap, 730 SI5341_OUT_MUX_SEL(output), 0x07, index); 731 } 732 733 static int si5341_output_set_parent(struct clk_hw *hw, u8 index) 734 { 735 struct clk_si5341_output *output = to_clk_si5341_output(hw); 736 737 if (index >= output->data->num_synth) 738 return -EINVAL; 739 740 return si5341_output_reparent(output, index); 741 } 742 743 static u8 si5341_output_get_parent(struct clk_hw *hw) 744 { 745 struct clk_si5341_output *output = to_clk_si5341_output(hw); 746 int err; 747 u32 val; 748 749 err = regmap_read(output->data->regmap, 750 SI5341_OUT_MUX_SEL(output), &val); 751 752 return val & 0x7; 753 } 754 755 static const struct clk_ops si5341_output_clk_ops = { 756 .is_prepared = si5341_output_clk_is_on, 757 .prepare = si5341_output_clk_prepare, 758 .unprepare = si5341_output_clk_unprepare, 759 .recalc_rate = si5341_output_clk_recalc_rate, 760 .round_rate = si5341_output_clk_round_rate, 761 .set_rate = si5341_output_clk_set_rate, 762 .set_parent = si5341_output_set_parent, 763 .get_parent = si5341_output_get_parent, 764 }; 765 766 /* 767 * The chip can be bought in a pre-programmed version, or one can program the 768 * NVM in the chip to boot up in a preset mode. This routine tries to determine 769 * if that's the case, or if we need to reset and program everything from 770 * scratch. Returns negative error, or true/false. 771 */ 772 static int si5341_is_programmed_already(struct clk_si5341 *data) 773 { 774 int err; 775 u8 r[4]; 776 777 /* Read the PLL divider value, it must have a non-zero value */ 778 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN, 779 r, ARRAY_SIZE(r)); 780 if (err < 0) 781 return err; 782 783 return !!get_unaligned_le32(r); 784 } 785 786 static struct clk_hw * 787 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data) 788 { 789 struct clk_si5341 *data = _data; 790 unsigned int idx = clkspec->args[1]; 791 unsigned int group = clkspec->args[0]; 792 793 switch (group) { 794 case 0: 795 if (idx >= data->num_outputs) { 796 dev_err(&data->i2c_client->dev, 797 "invalid output index %u\n", idx); 798 return ERR_PTR(-EINVAL); 799 } 800 return &data->clk[idx].hw; 801 case 1: 802 if (idx >= data->num_synth) { 803 dev_err(&data->i2c_client->dev, 804 "invalid synthesizer index %u\n", idx); 805 return ERR_PTR(-EINVAL); 806 } 807 return &data->synth[idx].hw; 808 case 2: 809 if (idx > 0) { 810 dev_err(&data->i2c_client->dev, 811 "invalid PLL index %u\n", idx); 812 return ERR_PTR(-EINVAL); 813 } 814 return &data->hw; 815 default: 816 dev_err(&data->i2c_client->dev, "invalid group %u\n", group); 817 return ERR_PTR(-EINVAL); 818 } 819 } 820 821 static int si5341_probe_chip_id(struct clk_si5341 *data) 822 { 823 int err; 824 u8 reg[4]; 825 u16 model; 826 827 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg, 828 ARRAY_SIZE(reg)); 829 if (err < 0) { 830 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n"); 831 return err; 832 } 833 834 model = get_unaligned_le16(reg); 835 836 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n", 837 model, reg[2], reg[3]); 838 839 switch (model) { 840 case 0x5340: 841 data->num_outputs = SI5340_MAX_NUM_OUTPUTS; 842 data->num_synth = SI5340_NUM_SYNTH; 843 data->reg_output_offset = si5340_reg_output_offset; 844 data->reg_rdiv_offset = si5340_reg_rdiv_offset; 845 break; 846 case 0x5341: 847 data->num_outputs = SI5341_MAX_NUM_OUTPUTS; 848 data->num_synth = SI5341_NUM_SYNTH; 849 data->reg_output_offset = si5341_reg_output_offset; 850 data->reg_rdiv_offset = si5341_reg_rdiv_offset; 851 break; 852 default: 853 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n", 854 model); 855 return -EINVAL; 856 } 857 858 return 0; 859 } 860 861 /* Read active settings into the regmap cache for later reference */ 862 static int si5341_read_settings(struct clk_si5341 *data) 863 { 864 int err; 865 u8 i; 866 u8 r[10]; 867 868 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10); 869 if (err < 0) 870 return err; 871 872 err = regmap_bulk_read(data->regmap, 873 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3); 874 if (err < 0) 875 return err; 876 877 err = regmap_bulk_read(data->regmap, 878 SI5341_SYNTH_N_CLK_DIS, r, 1); 879 if (err < 0) 880 return err; 881 882 for (i = 0; i < data->num_synth; ++i) { 883 err = regmap_bulk_read(data->regmap, 884 SI5341_SYNTH_N_NUM(i), r, 10); 885 if (err < 0) 886 return err; 887 } 888 889 for (i = 0; i < data->num_outputs; ++i) { 890 err = regmap_bulk_read(data->regmap, 891 data->reg_output_offset[i], r, 4); 892 if (err < 0) 893 return err; 894 895 err = regmap_bulk_read(data->regmap, 896 data->reg_rdiv_offset[i], r, 3); 897 if (err < 0) 898 return err; 899 } 900 901 return 0; 902 } 903 904 static int si5341_write_multiple(struct clk_si5341 *data, 905 const struct si5341_reg_default *values, unsigned int num_values) 906 { 907 unsigned int i; 908 int res; 909 910 for (i = 0; i < num_values; ++i) { 911 res = regmap_write(data->regmap, 912 values[i].address, values[i].value); 913 if (res < 0) { 914 dev_err(&data->i2c_client->dev, 915 "Failed to write %#x:%#x\n", 916 values[i].address, values[i].value); 917 return res; 918 } 919 } 920 921 return 0; 922 } 923 924 static const struct si5341_reg_default si5341_preamble[] = { 925 { 0x0B25, 0x00 }, 926 { 0x0502, 0x01 }, 927 { 0x0505, 0x03 }, 928 { 0x0957, 0x1F }, 929 { 0x0B4E, 0x1A }, 930 }; 931 932 static int si5341_send_preamble(struct clk_si5341 *data) 933 { 934 int res; 935 u32 revision; 936 937 /* For revision 2 and up, the values are slightly different */ 938 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); 939 if (res < 0) 940 return res; 941 942 /* Write "preamble" as specified by datasheet */ 943 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0); 944 if (res < 0) 945 return res; 946 res = si5341_write_multiple(data, 947 si5341_preamble, ARRAY_SIZE(si5341_preamble)); 948 if (res < 0) 949 return res; 950 951 /* Datasheet specifies a 300ms wait after sending the preamble */ 952 msleep(300); 953 954 return 0; 955 } 956 957 /* Perform a soft reset and write post-amble */ 958 static int si5341_finalize_defaults(struct clk_si5341 *data) 959 { 960 int res; 961 u32 revision; 962 963 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); 964 if (res < 0) 965 return res; 966 967 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision); 968 969 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01); 970 if (res < 0) 971 return res; 972 973 /* Datasheet does not explain these nameless registers */ 974 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3); 975 if (res < 0) 976 return res; 977 res = regmap_write(data->regmap, 0x0B25, 0x02); 978 if (res < 0) 979 return res; 980 981 return 0; 982 } 983 984 985 static const struct regmap_range si5341_regmap_volatile_range[] = { 986 regmap_reg_range(0x000C, 0x0012), /* Status */ 987 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */ 988 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */ 989 /* Update bits for synth config */ 990 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)), 991 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)), 992 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)), 993 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)), 994 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)), 995 }; 996 997 static const struct regmap_access_table si5341_regmap_volatile = { 998 .yes_ranges = si5341_regmap_volatile_range, 999 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range), 1000 }; 1001 1002 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */ 1003 static const struct regmap_range_cfg si5341_regmap_ranges[] = { 1004 { 1005 .range_min = 0, 1006 .range_max = SI5341_REGISTER_MAX, 1007 .selector_reg = SI5341_PAGE, 1008 .selector_mask = 0xff, 1009 .selector_shift = 0, 1010 .window_start = 0, 1011 .window_len = 256, 1012 }, 1013 }; 1014 1015 static const struct regmap_config si5341_regmap_config = { 1016 .reg_bits = 8, 1017 .val_bits = 8, 1018 .cache_type = REGCACHE_RBTREE, 1019 .ranges = si5341_regmap_ranges, 1020 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges), 1021 .max_register = SI5341_REGISTER_MAX, 1022 .volatile_table = &si5341_regmap_volatile, 1023 }; 1024 1025 static int si5341_dt_parse_dt(struct i2c_client *client, 1026 struct clk_si5341_output_config *config) 1027 { 1028 struct device_node *child; 1029 struct device_node *np = client->dev.of_node; 1030 u32 num; 1031 u32 val; 1032 1033 memset(config, 0, sizeof(struct clk_si5341_output_config) * 1034 SI5341_MAX_NUM_OUTPUTS); 1035 1036 for_each_child_of_node(np, child) { 1037 if (of_property_read_u32(child, "reg", &num)) { 1038 dev_err(&client->dev, "missing reg property of %s\n", 1039 child->name); 1040 goto put_child; 1041 } 1042 1043 if (num >= SI5341_MAX_NUM_OUTPUTS) { 1044 dev_err(&client->dev, "invalid clkout %d\n", num); 1045 goto put_child; 1046 } 1047 1048 if (!of_property_read_u32(child, "silabs,format", &val)) { 1049 /* Set cm and ampl conservatively to 3v3 settings */ 1050 switch (val) { 1051 case 1: /* normal differential */ 1052 config[num].out_cm_ampl_bits = 0x33; 1053 break; 1054 case 2: /* low-power differential */ 1055 config[num].out_cm_ampl_bits = 0x13; 1056 break; 1057 case 4: /* LVCMOS */ 1058 config[num].out_cm_ampl_bits = 0x33; 1059 /* Set SI recommended impedance for LVCMOS */ 1060 config[num].out_format_drv_bits |= 0xc0; 1061 break; 1062 default: 1063 dev_err(&client->dev, 1064 "invalid silabs,format %u for %u\n", 1065 val, num); 1066 goto put_child; 1067 } 1068 config[num].out_format_drv_bits &= ~0x07; 1069 config[num].out_format_drv_bits |= val & 0x07; 1070 /* Always enable the SYNC feature */ 1071 config[num].out_format_drv_bits |= 0x08; 1072 } 1073 1074 if (!of_property_read_u32(child, "silabs,common-mode", &val)) { 1075 if (val > 0xf) { 1076 dev_err(&client->dev, 1077 "invalid silabs,common-mode %u\n", 1078 val); 1079 goto put_child; 1080 } 1081 config[num].out_cm_ampl_bits &= 0xf0; 1082 config[num].out_cm_ampl_bits |= val & 0x0f; 1083 } 1084 1085 if (!of_property_read_u32(child, "silabs,amplitude", &val)) { 1086 if (val > 0xf) { 1087 dev_err(&client->dev, 1088 "invalid silabs,amplitude %u\n", 1089 val); 1090 goto put_child; 1091 } 1092 config[num].out_cm_ampl_bits &= 0x0f; 1093 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0; 1094 } 1095 1096 if (of_property_read_bool(child, "silabs,disable-high")) 1097 config[num].out_format_drv_bits |= 0x10; 1098 1099 config[num].synth_master = 1100 of_property_read_bool(child, "silabs,synth-master"); 1101 1102 config[num].always_on = 1103 of_property_read_bool(child, "always-on"); 1104 } 1105 1106 return 0; 1107 1108 put_child: 1109 of_node_put(child); 1110 return -EINVAL; 1111 } 1112 1113 /* 1114 * If not pre-configured, calculate and set the PLL configuration manually. 1115 * For low-jitter performance, the PLL should be set such that the synthesizers 1116 * only need integer division. 1117 * Without any user guidance, we'll set the PLL to 14GHz, which still allows 1118 * the chip to generate any frequency on its outputs, but jitter performance 1119 * may be sub-optimal. 1120 */ 1121 static int si5341_initialize_pll(struct clk_si5341 *data) 1122 { 1123 struct device_node *np = data->i2c_client->dev.of_node; 1124 u32 m_num = 0; 1125 u32 m_den = 0; 1126 1127 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) { 1128 dev_err(&data->i2c_client->dev, 1129 "PLL configuration requires silabs,pll-m-num\n"); 1130 } 1131 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) { 1132 dev_err(&data->i2c_client->dev, 1133 "PLL configuration requires silabs,pll-m-den\n"); 1134 } 1135 1136 if (!m_num || !m_den) { 1137 dev_err(&data->i2c_client->dev, 1138 "PLL configuration invalid, assume 14GHz\n"); 1139 m_den = clk_get_rate(data->pxtal) / 10; 1140 m_num = 1400000000; 1141 } 1142 1143 return si5341_encode_44_32(data->regmap, 1144 SI5341_PLL_M_NUM, m_num, m_den); 1145 } 1146 1147 static int si5341_probe(struct i2c_client *client, 1148 const struct i2c_device_id *id) 1149 { 1150 struct clk_si5341 *data; 1151 struct clk_init_data init; 1152 const char *root_clock_name; 1153 const char *synth_clock_names[SI5341_NUM_SYNTH]; 1154 int err; 1155 unsigned int i; 1156 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS]; 1157 bool initialization_required; 1158 1159 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); 1160 if (!data) 1161 return -ENOMEM; 1162 1163 data->i2c_client = client; 1164 1165 data->pxtal = devm_clk_get(&client->dev, "xtal"); 1166 if (IS_ERR(data->pxtal)) { 1167 if (PTR_ERR(data->pxtal) == -EPROBE_DEFER) 1168 return -EPROBE_DEFER; 1169 1170 dev_err(&client->dev, "Missing xtal clock input\n"); 1171 } 1172 1173 err = si5341_dt_parse_dt(client, config); 1174 if (err) 1175 return err; 1176 1177 if (of_property_read_string(client->dev.of_node, "clock-output-names", 1178 &init.name)) 1179 init.name = client->dev.of_node->name; 1180 root_clock_name = init.name; 1181 1182 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config); 1183 if (IS_ERR(data->regmap)) 1184 return PTR_ERR(data->regmap); 1185 1186 i2c_set_clientdata(client, data); 1187 1188 err = si5341_probe_chip_id(data); 1189 if (err < 0) 1190 return err; 1191 1192 /* "Activate" the xtal (usually a fixed clock) */ 1193 clk_prepare_enable(data->pxtal); 1194 1195 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) { 1196 initialization_required = true; 1197 } else { 1198 err = si5341_is_programmed_already(data); 1199 if (err < 0) 1200 return err; 1201 1202 initialization_required = !err; 1203 } 1204 1205 if (initialization_required) { 1206 /* Populate the regmap cache in preparation for "cache only" */ 1207 err = si5341_read_settings(data); 1208 if (err < 0) 1209 return err; 1210 1211 err = si5341_send_preamble(data); 1212 if (err < 0) 1213 return err; 1214 1215 /* 1216 * We intend to send all 'final' register values in a single 1217 * transaction. So cache all register writes until we're done 1218 * configuring. 1219 */ 1220 regcache_cache_only(data->regmap, true); 1221 1222 /* Write the configuration pairs from the firmware blob */ 1223 err = si5341_write_multiple(data, si5341_reg_defaults, 1224 ARRAY_SIZE(si5341_reg_defaults)); 1225 if (err < 0) 1226 return err; 1227 1228 /* PLL configuration is required */ 1229 err = si5341_initialize_pll(data); 1230 if (err < 0) 1231 return err; 1232 } 1233 1234 /* Register the PLL */ 1235 data->pxtal_name = __clk_get_name(data->pxtal); 1236 init.parent_names = &data->pxtal_name; 1237 init.num_parents = 1; /* For now, only XTAL input supported */ 1238 init.ops = &si5341_clk_ops; 1239 init.flags = 0; 1240 data->hw.init = &init; 1241 1242 err = devm_clk_hw_register(&client->dev, &data->hw); 1243 if (err) { 1244 dev_err(&client->dev, "clock registration failed\n"); 1245 return err; 1246 } 1247 1248 init.num_parents = 1; 1249 init.parent_names = &root_clock_name; 1250 init.ops = &si5341_synth_clk_ops; 1251 for (i = 0; i < data->num_synth; ++i) { 1252 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL, 1253 "%s.N%u", client->dev.of_node->name, i); 1254 init.name = synth_clock_names[i]; 1255 data->synth[i].index = i; 1256 data->synth[i].data = data; 1257 data->synth[i].hw.init = &init; 1258 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw); 1259 if (err) { 1260 dev_err(&client->dev, 1261 "synth N%u registration failed\n", i); 1262 } 1263 } 1264 1265 init.num_parents = data->num_synth; 1266 init.parent_names = synth_clock_names; 1267 init.ops = &si5341_output_clk_ops; 1268 for (i = 0; i < data->num_outputs; ++i) { 1269 init.name = kasprintf(GFP_KERNEL, "%s.%d", 1270 client->dev.of_node->name, i); 1271 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0; 1272 data->clk[i].index = i; 1273 data->clk[i].data = data; 1274 data->clk[i].hw.init = &init; 1275 if (config[i].out_format_drv_bits & 0x07) { 1276 regmap_write(data->regmap, 1277 SI5341_OUT_FORMAT(&data->clk[i]), 1278 config[i].out_format_drv_bits); 1279 regmap_write(data->regmap, 1280 SI5341_OUT_CM(&data->clk[i]), 1281 config[i].out_cm_ampl_bits); 1282 } 1283 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); 1284 kfree(init.name); /* clock framework made a copy of the name */ 1285 if (err) { 1286 dev_err(&client->dev, 1287 "output %u registration failed\n", i); 1288 return err; 1289 } 1290 if (config[i].always_on) 1291 clk_prepare(data->clk[i].hw.clk); 1292 } 1293 1294 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_si5341_get, 1295 data); 1296 if (err) { 1297 dev_err(&client->dev, "unable to add clk provider\n"); 1298 return err; 1299 } 1300 1301 if (initialization_required) { 1302 /* Synchronize */ 1303 regcache_cache_only(data->regmap, false); 1304 err = regcache_sync(data->regmap); 1305 if (err < 0) 1306 return err; 1307 1308 err = si5341_finalize_defaults(data); 1309 if (err < 0) 1310 return err; 1311 } 1312 1313 /* Free the names, clk framework makes copies */ 1314 for (i = 0; i < data->num_synth; ++i) 1315 devm_kfree(&client->dev, (void *)synth_clock_names[i]); 1316 1317 return 0; 1318 } 1319 1320 static const struct i2c_device_id si5341_id[] = { 1321 { "si5340", 0 }, 1322 { "si5341", 1 }, 1323 { } 1324 }; 1325 MODULE_DEVICE_TABLE(i2c, si5341_id); 1326 1327 static const struct of_device_id clk_si5341_of_match[] = { 1328 { .compatible = "silabs,si5340" }, 1329 { .compatible = "silabs,si5341" }, 1330 { } 1331 }; 1332 MODULE_DEVICE_TABLE(of, clk_si5341_of_match); 1333 1334 static struct i2c_driver si5341_driver = { 1335 .driver = { 1336 .name = "si5341", 1337 .of_match_table = clk_si5341_of_match, 1338 }, 1339 .probe = si5341_probe, 1340 .id_table = si5341_id, 1341 }; 1342 module_i2c_driver(si5341_driver); 1343 1344 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); 1345 MODULE_DESCRIPTION("Si5341 driver"); 1346 MODULE_LICENSE("GPL"); 1347