1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Renesas 9-series PCIe clock generator driver 4 * 5 * The following series can be supported: 6 * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ 7 * Currently supported: 8 * - 9FGV0241 9 * - 9FGV0441 10 * - 9FGV0841 11 * 12 * Copyright (C) 2022 Marek Vasut <marex@denx.de> 13 */ 14 15 #include <linux/clk-provider.h> 16 #include <linux/i2c.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/regmap.h> 21 22 #define RS9_REG_OE 0x0 23 #define RS9_REG_SS 0x1 24 #define RS9_REG_SS_AMP_0V6 0x0 25 #define RS9_REG_SS_AMP_0V7 0x1 26 #define RS9_REG_SS_AMP_0V8 0x2 27 #define RS9_REG_SS_AMP_0V9 0x3 28 #define RS9_REG_SS_AMP_DEFAULT RS9_REG_SS_AMP_0V8 29 #define RS9_REG_SS_AMP_MASK 0x3 30 #define RS9_REG_SS_SSC_100 0 31 #define RS9_REG_SS_SSC_M025 (1 << 3) 32 #define RS9_REG_SS_SSC_M050 (3 << 3) 33 #define RS9_REG_SS_SSC_DEFAULT RS9_REG_SS_SSC_100 34 #define RS9_REG_SS_SSC_MASK (3 << 3) 35 #define RS9_REG_SS_SSC_LOCK BIT(5) 36 #define RS9_REG_SR 0x2 37 #define RS9_REG_REF 0x3 38 #define RS9_REG_REF_OE BIT(4) 39 #define RS9_REG_REF_OD BIT(5) 40 #define RS9_REG_REF_SR_SLOWEST 0 41 #define RS9_REG_REF_SR_SLOW (1 << 6) 42 #define RS9_REG_REF_SR_FAST (2 << 6) 43 #define RS9_REG_REF_SR_FASTER (3 << 6) 44 #define RS9_REG_VID 0x5 45 #define RS9_REG_DID 0x6 46 #define RS9_REG_BCP 0x7 47 48 #define RS9_REG_VID_MASK GENMASK(3, 0) 49 #define RS9_REG_VID_IDT 0x01 50 51 #define RS9_REG_DID_TYPE_FGV (0x0 << RS9_REG_DID_TYPE_SHIFT) 52 #define RS9_REG_DID_TYPE_DBV (0x1 << RS9_REG_DID_TYPE_SHIFT) 53 #define RS9_REG_DID_TYPE_DMV (0x2 << RS9_REG_DID_TYPE_SHIFT) 54 #define RS9_REG_DID_TYPE_SHIFT 0x6 55 56 /* Structure to describe features of a particular 9-series model */ 57 struct rs9_chip_info { 58 unsigned int num_clks; 59 u8 outshift; 60 u8 did; 61 }; 62 63 struct rs9_driver_data { 64 struct i2c_client *client; 65 struct regmap *regmap; 66 const struct rs9_chip_info *chip_info; 67 struct clk_hw *clk_dif[4]; 68 u8 pll_amplitude; 69 u8 pll_ssc; 70 u8 clk_dif_sr; 71 }; 72 73 /* 74 * Renesas 9-series i2c regmap 75 */ 76 static const struct regmap_range rs9_readable_ranges[] = { 77 regmap_reg_range(RS9_REG_OE, RS9_REG_REF), 78 regmap_reg_range(RS9_REG_VID, RS9_REG_BCP), 79 }; 80 81 static const struct regmap_access_table rs9_readable_table = { 82 .yes_ranges = rs9_readable_ranges, 83 .n_yes_ranges = ARRAY_SIZE(rs9_readable_ranges), 84 }; 85 86 static const struct regmap_range rs9_writeable_ranges[] = { 87 regmap_reg_range(RS9_REG_OE, RS9_REG_REF), 88 regmap_reg_range(RS9_REG_BCP, RS9_REG_BCP), 89 }; 90 91 static const struct regmap_access_table rs9_writeable_table = { 92 .yes_ranges = rs9_writeable_ranges, 93 .n_yes_ranges = ARRAY_SIZE(rs9_writeable_ranges), 94 }; 95 96 static int rs9_regmap_i2c_write(void *context, 97 unsigned int reg, unsigned int val) 98 { 99 struct i2c_client *i2c = context; 100 const u8 data[3] = { reg, 1, val }; 101 const int count = ARRAY_SIZE(data); 102 int ret; 103 104 ret = i2c_master_send(i2c, data, count); 105 if (ret == count) 106 return 0; 107 else if (ret < 0) 108 return ret; 109 else 110 return -EIO; 111 } 112 113 static int rs9_regmap_i2c_read(void *context, 114 unsigned int reg, unsigned int *val) 115 { 116 struct i2c_client *i2c = context; 117 struct i2c_msg xfer[2]; 118 u8 txdata = reg; 119 u8 rxdata[2]; 120 int ret; 121 122 xfer[0].addr = i2c->addr; 123 xfer[0].flags = 0; 124 xfer[0].len = 1; 125 xfer[0].buf = (void *)&txdata; 126 127 xfer[1].addr = i2c->addr; 128 xfer[1].flags = I2C_M_RD; 129 xfer[1].len = 2; 130 xfer[1].buf = (void *)rxdata; 131 132 ret = i2c_transfer(i2c->adapter, xfer, 2); 133 if (ret < 0) 134 return ret; 135 if (ret != 2) 136 return -EIO; 137 138 /* 139 * Byte 0 is transfer length, which is always 1 due 140 * to BCP register programming to 1 in rs9_probe(), 141 * ignore it and use data from Byte 1. 142 */ 143 *val = rxdata[1]; 144 return 0; 145 } 146 147 static const struct regmap_config rs9_regmap_config = { 148 .reg_bits = 8, 149 .val_bits = 8, 150 .cache_type = REGCACHE_FLAT, 151 .max_register = RS9_REG_BCP, 152 .num_reg_defaults_raw = 0x8, 153 .rd_table = &rs9_readable_table, 154 .wr_table = &rs9_writeable_table, 155 .reg_write = rs9_regmap_i2c_write, 156 .reg_read = rs9_regmap_i2c_read, 157 }; 158 159 static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx) 160 { 161 /* 162 * On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE(1) is BIT(2), 163 * on 9FGV0441 and 9FGV0841 the DIF OE0 is BIT(0) and so on. 164 * Increment the index in the 9FGV0241 special case here. 165 */ 166 return BIT(idx + rs9->chip_info->outshift); 167 } 168 169 static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx) 170 { 171 struct i2c_client *client = rs9->client; 172 u8 dif = rs9_calc_dif(rs9, idx); 173 unsigned char name[5] = "DIF0"; 174 struct device_node *np; 175 int ret; 176 u32 sr; 177 178 /* Set defaults */ 179 rs9->clk_dif_sr |= dif; 180 181 snprintf(name, 5, "DIF%d", idx); 182 np = of_get_child_by_name(client->dev.of_node, name); 183 if (!np) 184 return 0; 185 186 /* Output clock slew rate */ 187 ret = of_property_read_u32(np, "renesas,slew-rate", &sr); 188 of_node_put(np); 189 if (!ret) { 190 if (sr == 2000000) { /* 2V/ns */ 191 rs9->clk_dif_sr &= ~dif; 192 } else if (sr == 3000000) { /* 3V/ns (default) */ 193 rs9->clk_dif_sr |= dif; 194 } else 195 ret = dev_err_probe(&client->dev, -EINVAL, 196 "Invalid renesas,slew-rate value\n"); 197 } 198 199 return ret; 200 } 201 202 static int rs9_get_common_config(struct rs9_driver_data *rs9) 203 { 204 struct i2c_client *client = rs9->client; 205 struct device_node *np = client->dev.of_node; 206 unsigned int amp, ssc; 207 int ret; 208 209 /* Set defaults */ 210 rs9->pll_amplitude = RS9_REG_SS_AMP_DEFAULT; 211 rs9->pll_ssc = RS9_REG_SS_SSC_DEFAULT; 212 213 /* Output clock amplitude */ 214 ret = of_property_read_u32(np, "renesas,out-amplitude-microvolt", 215 &); 216 if (!ret) { 217 if (amp == 600000) /* 0.6V */ 218 rs9->pll_amplitude = RS9_REG_SS_AMP_0V6; 219 else if (amp == 700000) /* 0.7V (default) */ 220 rs9->pll_amplitude = RS9_REG_SS_AMP_0V7; 221 else if (amp == 800000) /* 0.8V */ 222 rs9->pll_amplitude = RS9_REG_SS_AMP_0V8; 223 else if (amp == 900000) /* 0.9V */ 224 rs9->pll_amplitude = RS9_REG_SS_AMP_0V9; 225 else 226 return dev_err_probe(&client->dev, -EINVAL, 227 "Invalid renesas,out-amplitude-microvolt value\n"); 228 } 229 230 /* Output clock spread spectrum */ 231 ret = of_property_read_u32(np, "renesas,out-spread-spectrum", &ssc); 232 if (!ret) { 233 if (ssc == 100000) /* 100% ... no spread (default) */ 234 rs9->pll_ssc = RS9_REG_SS_SSC_100; 235 else if (ssc == 99750) /* -0.25% ... down spread */ 236 rs9->pll_ssc = RS9_REG_SS_SSC_M025; 237 else if (ssc == 99500) /* -0.50% ... down spread */ 238 rs9->pll_ssc = RS9_REG_SS_SSC_M050; 239 else 240 return dev_err_probe(&client->dev, -EINVAL, 241 "Invalid renesas,out-spread-spectrum value\n"); 242 } 243 244 return 0; 245 } 246 247 static void rs9_update_config(struct rs9_driver_data *rs9) 248 { 249 int i; 250 251 /* If amplitude is non-default, update it. */ 252 if (rs9->pll_amplitude != RS9_REG_SS_AMP_DEFAULT) { 253 regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_AMP_MASK, 254 rs9->pll_amplitude); 255 } 256 257 /* If SSC is non-default, update it. */ 258 if (rs9->pll_ssc != RS9_REG_SS_SSC_DEFAULT) { 259 regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_SSC_MASK, 260 rs9->pll_ssc); 261 } 262 263 for (i = 0; i < rs9->chip_info->num_clks; i++) { 264 u8 dif = rs9_calc_dif(rs9, i); 265 266 if (rs9->clk_dif_sr & dif) 267 continue; 268 269 regmap_update_bits(rs9->regmap, RS9_REG_SR, dif, 270 rs9->clk_dif_sr & dif); 271 } 272 } 273 274 static struct clk_hw * 275 rs9_of_clk_get(struct of_phandle_args *clkspec, void *data) 276 { 277 struct rs9_driver_data *rs9 = data; 278 unsigned int idx = clkspec->args[0]; 279 280 return rs9->clk_dif[idx]; 281 } 282 283 static int rs9_probe(struct i2c_client *client) 284 { 285 unsigned char name[5] = "DIF0"; 286 struct rs9_driver_data *rs9; 287 unsigned int vid, did; 288 struct clk_hw *hw; 289 int i, ret; 290 291 rs9 = devm_kzalloc(&client->dev, sizeof(*rs9), GFP_KERNEL); 292 if (!rs9) 293 return -ENOMEM; 294 295 i2c_set_clientdata(client, rs9); 296 rs9->client = client; 297 rs9->chip_info = i2c_get_match_data(client); 298 if (!rs9->chip_info) 299 return -EINVAL; 300 301 /* Fetch common configuration from DT (if specified) */ 302 ret = rs9_get_common_config(rs9); 303 if (ret) 304 return ret; 305 306 /* Fetch DIFx output configuration from DT (if specified) */ 307 for (i = 0; i < rs9->chip_info->num_clks; i++) { 308 ret = rs9_get_output_config(rs9, i); 309 if (ret) 310 return ret; 311 } 312 313 rs9->regmap = devm_regmap_init(&client->dev, NULL, 314 client, &rs9_regmap_config); 315 if (IS_ERR(rs9->regmap)) 316 return dev_err_probe(&client->dev, PTR_ERR(rs9->regmap), 317 "Failed to allocate register map\n"); 318 319 /* Always read back 1 Byte via I2C */ 320 ret = regmap_write(rs9->regmap, RS9_REG_BCP, 1); 321 if (ret < 0) 322 return ret; 323 324 ret = regmap_read(rs9->regmap, RS9_REG_VID, &vid); 325 if (ret < 0) 326 return ret; 327 328 ret = regmap_read(rs9->regmap, RS9_REG_DID, &did); 329 if (ret < 0) 330 return ret; 331 332 vid &= RS9_REG_VID_MASK; 333 if (vid != RS9_REG_VID_IDT || did != rs9->chip_info->did) 334 return dev_err_probe(&client->dev, -ENODEV, 335 "Incorrect VID/DID: %#02x, %#02x. Expected %#02x, %#02x\n", 336 vid, did, RS9_REG_VID_IDT, 337 rs9->chip_info->did); 338 339 /* Register clock */ 340 for (i = 0; i < rs9->chip_info->num_clks; i++) { 341 snprintf(name, 5, "DIF%d", i); 342 hw = devm_clk_hw_register_fixed_factor_index(&client->dev, name, 343 0, 0, 4, 1); 344 if (IS_ERR(hw)) 345 return PTR_ERR(hw); 346 347 rs9->clk_dif[i] = hw; 348 } 349 350 ret = devm_of_clk_add_hw_provider(&client->dev, rs9_of_clk_get, rs9); 351 if (!ret) 352 rs9_update_config(rs9); 353 354 return ret; 355 } 356 357 static int __maybe_unused rs9_suspend(struct device *dev) 358 { 359 struct rs9_driver_data *rs9 = dev_get_drvdata(dev); 360 361 regcache_cache_only(rs9->regmap, true); 362 regcache_mark_dirty(rs9->regmap); 363 364 return 0; 365 } 366 367 static int __maybe_unused rs9_resume(struct device *dev) 368 { 369 struct rs9_driver_data *rs9 = dev_get_drvdata(dev); 370 int ret; 371 372 regcache_cache_only(rs9->regmap, false); 373 ret = regcache_sync(rs9->regmap); 374 if (ret) 375 dev_err(dev, "Failed to restore register map: %d\n", ret); 376 return ret; 377 } 378 379 static const struct rs9_chip_info renesas_9fgv0241_info = { 380 .num_clks = 2, 381 .outshift = 1, 382 .did = RS9_REG_DID_TYPE_FGV | 0x02, 383 }; 384 385 static const struct rs9_chip_info renesas_9fgv0441_info = { 386 .num_clks = 4, 387 .outshift = 0, 388 .did = RS9_REG_DID_TYPE_FGV | 0x04, 389 }; 390 391 static const struct rs9_chip_info renesas_9fgv0841_info = { 392 .num_clks = 8, 393 .outshift = 0, 394 .did = RS9_REG_DID_TYPE_FGV | 0x08, 395 }; 396 397 static const struct i2c_device_id rs9_id[] = { 398 { "9fgv0241", .driver_data = (kernel_ulong_t)&renesas_9fgv0241_info }, 399 { "9fgv0441", .driver_data = (kernel_ulong_t)&renesas_9fgv0441_info }, 400 { "9fgv0841", .driver_data = (kernel_ulong_t)&renesas_9fgv0841_info }, 401 { } 402 }; 403 MODULE_DEVICE_TABLE(i2c, rs9_id); 404 405 static const struct of_device_id clk_rs9_of_match[] = { 406 { .compatible = "renesas,9fgv0241", .data = &renesas_9fgv0241_info }, 407 { .compatible = "renesas,9fgv0441", .data = &renesas_9fgv0441_info }, 408 { .compatible = "renesas,9fgv0841", .data = &renesas_9fgv0841_info }, 409 { } 410 }; 411 MODULE_DEVICE_TABLE(of, clk_rs9_of_match); 412 413 static SIMPLE_DEV_PM_OPS(rs9_pm_ops, rs9_suspend, rs9_resume); 414 415 static struct i2c_driver rs9_driver = { 416 .driver = { 417 .name = "clk-renesas-pcie-9series", 418 .pm = &rs9_pm_ops, 419 .of_match_table = clk_rs9_of_match, 420 }, 421 .probe = rs9_probe, 422 .id_table = rs9_id, 423 }; 424 module_i2c_driver(rs9_driver); 425 426 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 427 MODULE_DESCRIPTION("Renesas 9-series PCIe clock generator driver"); 428 MODULE_LICENSE("GPL"); 429