1*fcfd1436STali Perry // SPDX-License-Identifier: GPL-2.0 2*fcfd1436STali Perry /* 3*fcfd1436STali Perry * Nuvoton NPCM7xx Clock Generator 4*fcfd1436STali Perry * All the clocks are initialized by the bootloader, so this driver allow only 5*fcfd1436STali Perry * reading of current settings directly from the hardware. 6*fcfd1436STali Perry * 7*fcfd1436STali Perry * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com 8*fcfd1436STali Perry */ 9*fcfd1436STali Perry 10*fcfd1436STali Perry #include <linux/module.h> 11*fcfd1436STali Perry #include <linux/clk-provider.h> 12*fcfd1436STali Perry #include <linux/io.h> 13*fcfd1436STali Perry #include <linux/kernel.h> 14*fcfd1436STali Perry #include <linux/of.h> 15*fcfd1436STali Perry #include <linux/of_address.h> 16*fcfd1436STali Perry #include <linux/slab.h> 17*fcfd1436STali Perry #include <linux/err.h> 18*fcfd1436STali Perry #include <linux/bitfield.h> 19*fcfd1436STali Perry 20*fcfd1436STali Perry #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> 21*fcfd1436STali Perry 22*fcfd1436STali Perry struct npcm7xx_clk_pll { 23*fcfd1436STali Perry struct clk_hw hw; 24*fcfd1436STali Perry void __iomem *pllcon; 25*fcfd1436STali Perry u8 flags; 26*fcfd1436STali Perry }; 27*fcfd1436STali Perry 28*fcfd1436STali Perry #define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw) 29*fcfd1436STali Perry 30*fcfd1436STali Perry #define PLLCON_LOKI BIT(31) 31*fcfd1436STali Perry #define PLLCON_LOKS BIT(30) 32*fcfd1436STali Perry #define PLLCON_FBDV GENMASK(27, 16) 33*fcfd1436STali Perry #define PLLCON_OTDV2 GENMASK(15, 13) 34*fcfd1436STali Perry #define PLLCON_PWDEN BIT(12) 35*fcfd1436STali Perry #define PLLCON_OTDV1 GENMASK(10, 8) 36*fcfd1436STali Perry #define PLLCON_INDV GENMASK(5, 0) 37*fcfd1436STali Perry 38*fcfd1436STali Perry static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw, 39*fcfd1436STali Perry unsigned long parent_rate) 40*fcfd1436STali Perry { 41*fcfd1436STali Perry struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw); 42*fcfd1436STali Perry unsigned long fbdv, indv, otdv1, otdv2; 43*fcfd1436STali Perry unsigned int val; 44*fcfd1436STali Perry u64 ret; 45*fcfd1436STali Perry 46*fcfd1436STali Perry if (parent_rate == 0) { 47*fcfd1436STali Perry pr_err("%s: parent rate is zero", __func__); 48*fcfd1436STali Perry return 0; 49*fcfd1436STali Perry } 50*fcfd1436STali Perry 51*fcfd1436STali Perry val = readl_relaxed(pll->pllcon); 52*fcfd1436STali Perry 53*fcfd1436STali Perry indv = FIELD_GET(PLLCON_INDV, val); 54*fcfd1436STali Perry fbdv = FIELD_GET(PLLCON_FBDV, val); 55*fcfd1436STali Perry otdv1 = FIELD_GET(PLLCON_OTDV1, val); 56*fcfd1436STali Perry otdv2 = FIELD_GET(PLLCON_OTDV2, val); 57*fcfd1436STali Perry 58*fcfd1436STali Perry ret = (u64)parent_rate * fbdv; 59*fcfd1436STali Perry do_div(ret, indv * otdv1 * otdv2); 60*fcfd1436STali Perry 61*fcfd1436STali Perry return ret; 62*fcfd1436STali Perry } 63*fcfd1436STali Perry 64*fcfd1436STali Perry static const struct clk_ops npcm7xx_clk_pll_ops = { 65*fcfd1436STali Perry .recalc_rate = npcm7xx_clk_pll_recalc_rate, 66*fcfd1436STali Perry }; 67*fcfd1436STali Perry 68*fcfd1436STali Perry static struct clk_hw * 69*fcfd1436STali Perry npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name, 70*fcfd1436STali Perry const char *parent_name, unsigned long flags) 71*fcfd1436STali Perry { 72*fcfd1436STali Perry struct npcm7xx_clk_pll *pll; 73*fcfd1436STali Perry struct clk_init_data init; 74*fcfd1436STali Perry struct clk_hw *hw; 75*fcfd1436STali Perry int ret; 76*fcfd1436STali Perry 77*fcfd1436STali Perry pll = kzalloc(sizeof(*pll), GFP_KERNEL); 78*fcfd1436STali Perry if (!pll) 79*fcfd1436STali Perry return ERR_PTR(-ENOMEM); 80*fcfd1436STali Perry 81*fcfd1436STali Perry pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name); 82*fcfd1436STali Perry 83*fcfd1436STali Perry init.name = name; 84*fcfd1436STali Perry init.ops = &npcm7xx_clk_pll_ops; 85*fcfd1436STali Perry init.parent_names = &parent_name; 86*fcfd1436STali Perry init.num_parents = 1; 87*fcfd1436STali Perry init.flags = flags; 88*fcfd1436STali Perry 89*fcfd1436STali Perry pll->pllcon = pllcon; 90*fcfd1436STali Perry pll->hw.init = &init; 91*fcfd1436STali Perry 92*fcfd1436STali Perry hw = &pll->hw; 93*fcfd1436STali Perry 94*fcfd1436STali Perry ret = clk_hw_register(NULL, hw); 95*fcfd1436STali Perry if (ret) { 96*fcfd1436STali Perry kfree(pll); 97*fcfd1436STali Perry hw = ERR_PTR(ret); 98*fcfd1436STali Perry } 99*fcfd1436STali Perry 100*fcfd1436STali Perry return hw; 101*fcfd1436STali Perry } 102*fcfd1436STali Perry 103*fcfd1436STali Perry #define NPCM7XX_CLKEN1 (0x00) 104*fcfd1436STali Perry #define NPCM7XX_CLKEN2 (0x28) 105*fcfd1436STali Perry #define NPCM7XX_CLKEN3 (0x30) 106*fcfd1436STali Perry #define NPCM7XX_CLKSEL (0x04) 107*fcfd1436STali Perry #define NPCM7XX_CLKDIV1 (0x08) 108*fcfd1436STali Perry #define NPCM7XX_CLKDIV2 (0x2C) 109*fcfd1436STali Perry #define NPCM7XX_CLKDIV3 (0x58) 110*fcfd1436STali Perry #define NPCM7XX_PLLCON0 (0x0C) 111*fcfd1436STali Perry #define NPCM7XX_PLLCON1 (0x10) 112*fcfd1436STali Perry #define NPCM7XX_PLLCON2 (0x54) 113*fcfd1436STali Perry #define NPCM7XX_SWRSTR (0x14) 114*fcfd1436STali Perry #define NPCM7XX_IRQWAKECON (0x18) 115*fcfd1436STali Perry #define NPCM7XX_IRQWAKEFLAG (0x1C) 116*fcfd1436STali Perry #define NPCM7XX_IPSRST1 (0x20) 117*fcfd1436STali Perry #define NPCM7XX_IPSRST2 (0x24) 118*fcfd1436STali Perry #define NPCM7XX_IPSRST3 (0x34) 119*fcfd1436STali Perry #define NPCM7XX_WD0RCR (0x38) 120*fcfd1436STali Perry #define NPCM7XX_WD1RCR (0x3C) 121*fcfd1436STali Perry #define NPCM7XX_WD2RCR (0x40) 122*fcfd1436STali Perry #define NPCM7XX_SWRSTC1 (0x44) 123*fcfd1436STali Perry #define NPCM7XX_SWRSTC2 (0x48) 124*fcfd1436STali Perry #define NPCM7XX_SWRSTC3 (0x4C) 125*fcfd1436STali Perry #define NPCM7XX_SWRSTC4 (0x50) 126*fcfd1436STali Perry #define NPCM7XX_CORSTC (0x5C) 127*fcfd1436STali Perry #define NPCM7XX_PLLCONG (0x60) 128*fcfd1436STali Perry #define NPCM7XX_AHBCKFI (0x64) 129*fcfd1436STali Perry #define NPCM7XX_SECCNT (0x68) 130*fcfd1436STali Perry #define NPCM7XX_CNTR25M (0x6C) 131*fcfd1436STali Perry 132*fcfd1436STali Perry struct npcm7xx_clk_gate_data { 133*fcfd1436STali Perry u32 reg; 134*fcfd1436STali Perry u8 bit_idx; 135*fcfd1436STali Perry const char *name; 136*fcfd1436STali Perry const char *parent_name; 137*fcfd1436STali Perry unsigned long flags; 138*fcfd1436STali Perry /* 139*fcfd1436STali Perry * If this clock is exported via DT, set onecell_idx to constant 140*fcfd1436STali Perry * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for 141*fcfd1436STali Perry * this specific clock. Otherwise, set to -1. 142*fcfd1436STali Perry */ 143*fcfd1436STali Perry int onecell_idx; 144*fcfd1436STali Perry }; 145*fcfd1436STali Perry 146*fcfd1436STali Perry struct npcm7xx_clk_mux_data { 147*fcfd1436STali Perry u8 shift; 148*fcfd1436STali Perry u8 mask; 149*fcfd1436STali Perry u32 *table; 150*fcfd1436STali Perry const char *name; 151*fcfd1436STali Perry const char * const *parent_names; 152*fcfd1436STali Perry u8 num_parents; 153*fcfd1436STali Perry unsigned long flags; 154*fcfd1436STali Perry /* 155*fcfd1436STali Perry * If this clock is exported via DT, set onecell_idx to constant 156*fcfd1436STali Perry * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for 157*fcfd1436STali Perry * this specific clock. Otherwise, set to -1. 158*fcfd1436STali Perry */ 159*fcfd1436STali Perry int onecell_idx; 160*fcfd1436STali Perry 161*fcfd1436STali Perry }; 162*fcfd1436STali Perry 163*fcfd1436STali Perry struct npcm7xx_clk_div_fixed_data { 164*fcfd1436STali Perry u8 mult; 165*fcfd1436STali Perry u8 div; 166*fcfd1436STali Perry const char *name; 167*fcfd1436STali Perry const char *parent_name; 168*fcfd1436STali Perry u8 clk_divider_flags; 169*fcfd1436STali Perry /* 170*fcfd1436STali Perry * If this clock is exported via DT, set onecell_idx to constant 171*fcfd1436STali Perry * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for 172*fcfd1436STali Perry * this specific clock. Otherwise, set to -1. 173*fcfd1436STali Perry */ 174*fcfd1436STali Perry int onecell_idx; 175*fcfd1436STali Perry }; 176*fcfd1436STali Perry 177*fcfd1436STali Perry 178*fcfd1436STali Perry struct npcm7xx_clk_div_data { 179*fcfd1436STali Perry u32 reg; 180*fcfd1436STali Perry u8 shift; 181*fcfd1436STali Perry u8 width; 182*fcfd1436STali Perry const char *name; 183*fcfd1436STali Perry const char *parent_name; 184*fcfd1436STali Perry u8 clk_divider_flags; 185*fcfd1436STali Perry unsigned long flags; 186*fcfd1436STali Perry /* 187*fcfd1436STali Perry * If this clock is exported via DT, set onecell_idx to constant 188*fcfd1436STali Perry * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for 189*fcfd1436STali Perry * this specific clock. Otherwise, set to -1. 190*fcfd1436STali Perry */ 191*fcfd1436STali Perry int onecell_idx; 192*fcfd1436STali Perry }; 193*fcfd1436STali Perry 194*fcfd1436STali Perry struct npcm7xx_clk_pll_data { 195*fcfd1436STali Perry u32 reg; 196*fcfd1436STali Perry const char *name; 197*fcfd1436STali Perry const char *parent_name; 198*fcfd1436STali Perry unsigned long flags; 199*fcfd1436STali Perry /* 200*fcfd1436STali Perry * If this clock is exported via DT, set onecell_idx to constant 201*fcfd1436STali Perry * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for 202*fcfd1436STali Perry * this specific clock. Otherwise, set to -1. 203*fcfd1436STali Perry */ 204*fcfd1436STali Perry int onecell_idx; 205*fcfd1436STali Perry }; 206*fcfd1436STali Perry 207*fcfd1436STali Perry /* 208*fcfd1436STali Perry * Single copy of strings used to refer to clocks within this driver indexed by 209*fcfd1436STali Perry * above enum. 210*fcfd1436STali Perry */ 211*fcfd1436STali Perry #define NPCM7XX_CLK_S_REFCLK "refclk" 212*fcfd1436STali Perry #define NPCM7XX_CLK_S_SYSBYPCK "sysbypck" 213*fcfd1436STali Perry #define NPCM7XX_CLK_S_MCBYPCK "mcbypck" 214*fcfd1436STali Perry #define NPCM7XX_CLK_S_GFXBYPCK "gfxbypck" 215*fcfd1436STali Perry #define NPCM7XX_CLK_S_PLL0 "pll0" 216*fcfd1436STali Perry #define NPCM7XX_CLK_S_PLL1 "pll1" 217*fcfd1436STali Perry #define NPCM7XX_CLK_S_PLL1_DIV2 "pll1_div2" 218*fcfd1436STali Perry #define NPCM7XX_CLK_S_PLL2 "pll2" 219*fcfd1436STali Perry #define NPCM7XX_CLK_S_PLL_GFX "pll_gfx" 220*fcfd1436STali Perry #define NPCM7XX_CLK_S_PLL2_DIV2 "pll2_div2" 221*fcfd1436STali Perry #define NPCM7XX_CLK_S_PIX_MUX "gfx_pixel" 222*fcfd1436STali Perry #define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux" 223*fcfd1436STali Perry #define NPCM7XX_CLK_S_MC_MUX "mc_phy" 224*fcfd1436STali Perry #define NPCM7XX_CLK_S_CPU_MUX "cpu" /*AKA system clock.*/ 225*fcfd1436STali Perry #define NPCM7XX_CLK_S_MC "mc" 226*fcfd1436STali Perry #define NPCM7XX_CLK_S_AXI "axi" /*AKA CLK2*/ 227*fcfd1436STali Perry #define NPCM7XX_CLK_S_AHB "ahb" /*AKA CLK4*/ 228*fcfd1436STali Perry #define NPCM7XX_CLK_S_CLKOUT_MUX "clkout_mux" 229*fcfd1436STali Perry #define NPCM7XX_CLK_S_UART_MUX "uart_mux" 230*fcfd1436STali Perry #define NPCM7XX_CLK_S_TIM_MUX "timer_mux" 231*fcfd1436STali Perry #define NPCM7XX_CLK_S_SD_MUX "sd_mux" 232*fcfd1436STali Perry #define NPCM7XX_CLK_S_GFXM_MUX "gfxm_mux" 233*fcfd1436STali Perry #define NPCM7XX_CLK_S_SU_MUX "serial_usb_mux" 234*fcfd1436STali Perry #define NPCM7XX_CLK_S_DVC_MUX "dvc_mux" 235*fcfd1436STali Perry #define NPCM7XX_CLK_S_GFX_MUX "gfx_mux" 236*fcfd1436STali Perry #define NPCM7XX_CLK_S_GFX_PIXEL "gfx_pixel" 237*fcfd1436STali Perry #define NPCM7XX_CLK_S_SPI0 "spi0" 238*fcfd1436STali Perry #define NPCM7XX_CLK_S_SPI3 "spi3" 239*fcfd1436STali Perry #define NPCM7XX_CLK_S_SPIX "spix" 240*fcfd1436STali Perry #define NPCM7XX_CLK_S_APB1 "apb1" 241*fcfd1436STali Perry #define NPCM7XX_CLK_S_APB2 "apb2" 242*fcfd1436STali Perry #define NPCM7XX_CLK_S_APB3 "apb3" 243*fcfd1436STali Perry #define NPCM7XX_CLK_S_APB4 "apb4" 244*fcfd1436STali Perry #define NPCM7XX_CLK_S_APB5 "apb5" 245*fcfd1436STali Perry #define NPCM7XX_CLK_S_TOCK "tock" 246*fcfd1436STali Perry #define NPCM7XX_CLK_S_CLKOUT "clkout" 247*fcfd1436STali Perry #define NPCM7XX_CLK_S_UART "uart" 248*fcfd1436STali Perry #define NPCM7XX_CLK_S_TIMER "timer" 249*fcfd1436STali Perry #define NPCM7XX_CLK_S_MMC "mmc" 250*fcfd1436STali Perry #define NPCM7XX_CLK_S_SDHC "sdhc" 251*fcfd1436STali Perry #define NPCM7XX_CLK_S_ADC "adc" 252*fcfd1436STali Perry #define NPCM7XX_CLK_S_GFX "gfx0_gfx1_mem" 253*fcfd1436STali Perry #define NPCM7XX_CLK_S_USBIF "serial_usbif" 254*fcfd1436STali Perry #define NPCM7XX_CLK_S_USB_HOST "usb_host" 255*fcfd1436STali Perry #define NPCM7XX_CLK_S_USB_BRIDGE "usb_bridge" 256*fcfd1436STali Perry #define NPCM7XX_CLK_S_PCI "pci" 257*fcfd1436STali Perry 258*fcfd1436STali Perry static u32 pll_mux_table[] = {0, 1, 2, 3}; 259*fcfd1436STali Perry static const char * const pll_mux_parents[] __initconst = { 260*fcfd1436STali Perry NPCM7XX_CLK_S_PLL0, 261*fcfd1436STali Perry NPCM7XX_CLK_S_PLL1_DIV2, 262*fcfd1436STali Perry NPCM7XX_CLK_S_REFCLK, 263*fcfd1436STali Perry NPCM7XX_CLK_S_PLL2_DIV2, 264*fcfd1436STali Perry }; 265*fcfd1436STali Perry 266*fcfd1436STali Perry static u32 cpuck_mux_table[] = {0, 1, 2, 3}; 267*fcfd1436STali Perry static const char * const cpuck_mux_parents[] __initconst = { 268*fcfd1436STali Perry NPCM7XX_CLK_S_PLL0, 269*fcfd1436STali Perry NPCM7XX_CLK_S_PLL1_DIV2, 270*fcfd1436STali Perry NPCM7XX_CLK_S_REFCLK, 271*fcfd1436STali Perry NPCM7XX_CLK_S_SYSBYPCK, 272*fcfd1436STali Perry }; 273*fcfd1436STali Perry 274*fcfd1436STali Perry static u32 pixcksel_mux_table[] = {0, 2}; 275*fcfd1436STali Perry static const char * const pixcksel_mux_parents[] __initconst = { 276*fcfd1436STali Perry NPCM7XX_CLK_S_PLL_GFX, 277*fcfd1436STali Perry NPCM7XX_CLK_S_REFCLK, 278*fcfd1436STali Perry }; 279*fcfd1436STali Perry 280*fcfd1436STali Perry static u32 sucksel_mux_table[] = {2, 3}; 281*fcfd1436STali Perry static const char * const sucksel_mux_parents[] __initconst = { 282*fcfd1436STali Perry NPCM7XX_CLK_S_REFCLK, 283*fcfd1436STali Perry NPCM7XX_CLK_S_PLL2_DIV2, 284*fcfd1436STali Perry }; 285*fcfd1436STali Perry 286*fcfd1436STali Perry static u32 mccksel_mux_table[] = {0, 2, 3}; 287*fcfd1436STali Perry static const char * const mccksel_mux_parents[] __initconst = { 288*fcfd1436STali Perry NPCM7XX_CLK_S_PLL1_DIV2, 289*fcfd1436STali Perry NPCM7XX_CLK_S_REFCLK, 290*fcfd1436STali Perry NPCM7XX_CLK_S_MCBYPCK, 291*fcfd1436STali Perry }; 292*fcfd1436STali Perry 293*fcfd1436STali Perry static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4}; 294*fcfd1436STali Perry static const char * const clkoutsel_mux_parents[] __initconst = { 295*fcfd1436STali Perry NPCM7XX_CLK_S_PLL0, 296*fcfd1436STali Perry NPCM7XX_CLK_S_PLL1_DIV2, 297*fcfd1436STali Perry NPCM7XX_CLK_S_REFCLK, 298*fcfd1436STali Perry NPCM7XX_CLK_S_PLL_GFX, // divided by 2 299*fcfd1436STali Perry NPCM7XX_CLK_S_PLL2_DIV2, 300*fcfd1436STali Perry }; 301*fcfd1436STali Perry 302*fcfd1436STali Perry static u32 gfxmsel_mux_table[] = {2, 3}; 303*fcfd1436STali Perry static const char * const gfxmsel_mux_parents[] __initconst = { 304*fcfd1436STali Perry NPCM7XX_CLK_S_REFCLK, 305*fcfd1436STali Perry NPCM7XX_CLK_S_PLL2_DIV2, 306*fcfd1436STali Perry }; 307*fcfd1436STali Perry 308*fcfd1436STali Perry static u32 dvcssel_mux_table[] = {2, 3}; 309*fcfd1436STali Perry static const char * const dvcssel_mux_parents[] __initconst = { 310*fcfd1436STali Perry NPCM7XX_CLK_S_REFCLK, 311*fcfd1436STali Perry NPCM7XX_CLK_S_PLL2, 312*fcfd1436STali Perry }; 313*fcfd1436STali Perry 314*fcfd1436STali Perry static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = { 315*fcfd1436STali Perry {NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1}, 316*fcfd1436STali Perry 317*fcfd1436STali Perry {NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1, 318*fcfd1436STali Perry NPCM7XX_CLK_S_REFCLK, 0, -1}, 319*fcfd1436STali Perry 320*fcfd1436STali Perry {NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2, 321*fcfd1436STali Perry NPCM7XX_CLK_S_REFCLK, 0, -1}, 322*fcfd1436STali Perry 323*fcfd1436STali Perry {NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX, 324*fcfd1436STali Perry NPCM7XX_CLK_S_REFCLK, 0, -1}, 325*fcfd1436STali Perry }; 326*fcfd1436STali Perry 327*fcfd1436STali Perry static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = { 328*fcfd1436STali Perry {0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX, 329*fcfd1436STali Perry cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL, 330*fcfd1436STali Perry NPCM7XX_CLK_CPU}, 331*fcfd1436STali Perry 332*fcfd1436STali Perry {4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX, 333*fcfd1436STali Perry pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0, 334*fcfd1436STali Perry NPCM7XX_CLK_GFX_PIXEL}, 335*fcfd1436STali Perry 336*fcfd1436STali Perry {6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX, 337*fcfd1436STali Perry pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, 338*fcfd1436STali Perry 339*fcfd1436STali Perry {8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX, 340*fcfd1436STali Perry pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, 341*fcfd1436STali Perry 342*fcfd1436STali Perry {10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX, 343*fcfd1436STali Perry sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1}, 344*fcfd1436STali Perry 345*fcfd1436STali Perry {12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX, 346*fcfd1436STali Perry mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1}, 347*fcfd1436STali Perry 348*fcfd1436STali Perry {14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX, 349*fcfd1436STali Perry pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, 350*fcfd1436STali Perry 351*fcfd1436STali Perry {16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX, 352*fcfd1436STali Perry pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, 353*fcfd1436STali Perry 354*fcfd1436STali Perry {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX, 355*fcfd1436STali Perry clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1}, 356*fcfd1436STali Perry 357*fcfd1436STali Perry {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX, 358*fcfd1436STali Perry gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1}, 359*fcfd1436STali Perry 360*fcfd1436STali Perry {23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX, 361*fcfd1436STali Perry dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1}, 362*fcfd1436STali Perry }; 363*fcfd1436STali Perry 364*fcfd1436STali Perry /* fixed ratio dividers (no register): */ 365*fcfd1436STali Perry static const struct npcm7xx_clk_div_fixed_data npcm7xx_divs_fx[] __initconst = { 366*fcfd1436STali Perry { 1, 2, NPCM7XX_CLK_S_MC, NPCM7XX_CLK_S_MC_MUX, 0, NPCM7XX_CLK_MC}, 367*fcfd1436STali Perry { 1, 2, NPCM7XX_CLK_S_PLL1_DIV2, NPCM7XX_CLK_S_PLL1, 0, -1}, 368*fcfd1436STali Perry { 1, 2, NPCM7XX_CLK_S_PLL2_DIV2, NPCM7XX_CLK_S_PLL2, 0, -1}, 369*fcfd1436STali Perry }; 370*fcfd1436STali Perry 371*fcfd1436STali Perry /* configurable dividers: */ 372*fcfd1436STali Perry static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = { 373*fcfd1436STali Perry {NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC, 374*fcfd1436STali Perry NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC}, 375*fcfd1436STali Perry /*30-28 ADCCKDIV*/ 376*fcfd1436STali Perry {NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB, 377*fcfd1436STali Perry NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB}, 378*fcfd1436STali Perry /*27-26 CLK4DIV*/ 379*fcfd1436STali Perry {NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER, 380*fcfd1436STali Perry NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER}, 381*fcfd1436STali Perry /*25-21 TIMCKDIV*/ 382*fcfd1436STali Perry {NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART, 383*fcfd1436STali Perry NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART}, 384*fcfd1436STali Perry /*20-16 UARTDIV*/ 385*fcfd1436STali Perry {NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC, 386*fcfd1436STali Perry NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC}, 387*fcfd1436STali Perry /*15-11 MMCCKDIV*/ 388*fcfd1436STali Perry {NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3, 389*fcfd1436STali Perry NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3}, 390*fcfd1436STali Perry /*10-6 AHB3CKDIV*/ 391*fcfd1436STali Perry {NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI, 392*fcfd1436STali Perry NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI}, 393*fcfd1436STali Perry /*5-2 PCICKDIV*/ 394*fcfd1436STali Perry {NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI, 395*fcfd1436STali Perry NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL, 396*fcfd1436STali Perry NPCM7XX_CLK_AXI},/*0 CLK2DIV*/ 397*fcfd1436STali Perry 398*fcfd1436STali Perry {NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4, 399*fcfd1436STali Perry NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4}, 400*fcfd1436STali Perry /*31-30 APB4CKDIV*/ 401*fcfd1436STali Perry {NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3, 402*fcfd1436STali Perry NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3}, 403*fcfd1436STali Perry /*29-28 APB3CKDIV*/ 404*fcfd1436STali Perry {NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2, 405*fcfd1436STali Perry NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2}, 406*fcfd1436STali Perry /*27-26 APB2CKDIV*/ 407*fcfd1436STali Perry {NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1, 408*fcfd1436STali Perry NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1}, 409*fcfd1436STali Perry /*25-24 APB1CKDIV*/ 410*fcfd1436STali Perry {NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5, 411*fcfd1436STali Perry NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5}, 412*fcfd1436STali Perry /*23-22 APB5CKDIV*/ 413*fcfd1436STali Perry {NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT, 414*fcfd1436STali Perry NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT}, 415*fcfd1436STali Perry /*20-16 CLKOUTDIV*/ 416*fcfd1436STali Perry {NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX, 417*fcfd1436STali Perry NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX}, 418*fcfd1436STali Perry /*15-13 GFXCKDIV*/ 419*fcfd1436STali Perry {NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE, 420*fcfd1436STali Perry NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU}, 421*fcfd1436STali Perry /*12-8 SUCKDIV*/ 422*fcfd1436STali Perry {NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST, 423*fcfd1436STali Perry NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48}, 424*fcfd1436STali Perry /*7-4 SU48CKDIV*/ 425*fcfd1436STali Perry {NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC, 426*fcfd1436STali Perry NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC} 427*fcfd1436STali Perry ,/*3-0 SD1CKDIV*/ 428*fcfd1436STali Perry 429*fcfd1436STali Perry {NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0, 430*fcfd1436STali Perry NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0}, 431*fcfd1436STali Perry /*10-6 SPI0CKDV*/ 432*fcfd1436STali Perry {NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX, 433*fcfd1436STali Perry NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX}, 434*fcfd1436STali Perry /*5-1 SPIXCKDV*/ 435*fcfd1436STali Perry 436*fcfd1436STali Perry }; 437*fcfd1436STali Perry 438*fcfd1436STali Perry static const struct npcm7xx_clk_gate_data npcm7xx_gates[] __initconst = { 439*fcfd1436STali Perry {NPCM7XX_CLKEN1, 31, "smb1-gate", NPCM7XX_CLK_S_APB2, 0}, 440*fcfd1436STali Perry {NPCM7XX_CLKEN1, 30, "smb0-gate", NPCM7XX_CLK_S_APB2, 0}, 441*fcfd1436STali Perry {NPCM7XX_CLKEN1, 29, "smb7-gate", NPCM7XX_CLK_S_APB2, 0}, 442*fcfd1436STali Perry {NPCM7XX_CLKEN1, 28, "smb6-gate", NPCM7XX_CLK_S_APB2, 0}, 443*fcfd1436STali Perry {NPCM7XX_CLKEN1, 27, "adc-gate", NPCM7XX_CLK_S_APB1, 0}, 444*fcfd1436STali Perry {NPCM7XX_CLKEN1, 26, "wdt-gate", NPCM7XX_CLK_S_TIMER, 0}, 445*fcfd1436STali Perry {NPCM7XX_CLKEN1, 25, "usbdev3-gate", NPCM7XX_CLK_S_AHB, 0}, 446*fcfd1436STali Perry {NPCM7XX_CLKEN1, 24, "usbdev6-gate", NPCM7XX_CLK_S_AHB, 0}, 447*fcfd1436STali Perry {NPCM7XX_CLKEN1, 23, "usbdev5-gate", NPCM7XX_CLK_S_AHB, 0}, 448*fcfd1436STali Perry {NPCM7XX_CLKEN1, 22, "usbdev4-gate", NPCM7XX_CLK_S_AHB, 0}, 449*fcfd1436STali Perry {NPCM7XX_CLKEN1, 21, "emc2-gate", NPCM7XX_CLK_S_AHB, 0}, 450*fcfd1436STali Perry {NPCM7XX_CLKEN1, 20, "timer5_9-gate", NPCM7XX_CLK_S_APB1, 0}, 451*fcfd1436STali Perry {NPCM7XX_CLKEN1, 19, "timer0_4-gate", NPCM7XX_CLK_S_APB1, 0}, 452*fcfd1436STali Perry {NPCM7XX_CLKEN1, 18, "pwmm0-gate", NPCM7XX_CLK_S_APB3, 0}, 453*fcfd1436STali Perry {NPCM7XX_CLKEN1, 17, "huart-gate", NPCM7XX_CLK_S_UART, 0}, 454*fcfd1436STali Perry {NPCM7XX_CLKEN1, 16, "smb5-gate", NPCM7XX_CLK_S_APB2, 0}, 455*fcfd1436STali Perry {NPCM7XX_CLKEN1, 15, "smb4-gate", NPCM7XX_CLK_S_APB2, 0}, 456*fcfd1436STali Perry {NPCM7XX_CLKEN1, 14, "smb3-gate", NPCM7XX_CLK_S_APB2, 0}, 457*fcfd1436STali Perry {NPCM7XX_CLKEN1, 13, "smb2-gate", NPCM7XX_CLK_S_APB2, 0}, 458*fcfd1436STali Perry {NPCM7XX_CLKEN1, 12, "mc-gate", NPCM7XX_CLK_S_MC, 0}, 459*fcfd1436STali Perry {NPCM7XX_CLKEN1, 11, "uart01-gate", NPCM7XX_CLK_S_APB1, 0}, 460*fcfd1436STali Perry {NPCM7XX_CLKEN1, 10, "aes-gate", NPCM7XX_CLK_S_AHB, 0}, 461*fcfd1436STali Perry {NPCM7XX_CLKEN1, 9, "peci-gate", NPCM7XX_CLK_S_APB3, 0}, 462*fcfd1436STali Perry {NPCM7XX_CLKEN1, 8, "usbdev2-gate", NPCM7XX_CLK_S_AHB, 0}, 463*fcfd1436STali Perry {NPCM7XX_CLKEN1, 7, "uart23-gate", NPCM7XX_CLK_S_APB1, 0}, 464*fcfd1436STali Perry {NPCM7XX_CLKEN1, 6, "emc1-gate", NPCM7XX_CLK_S_AHB, 0}, 465*fcfd1436STali Perry {NPCM7XX_CLKEN1, 5, "usbdev1-gate", NPCM7XX_CLK_S_AHB, 0}, 466*fcfd1436STali Perry {NPCM7XX_CLKEN1, 4, "shm-gate", NPCM7XX_CLK_S_AHB, 0}, 467*fcfd1436STali Perry /* bit 3 is reserved */ 468*fcfd1436STali Perry {NPCM7XX_CLKEN1, 2, "kcs-gate", NPCM7XX_CLK_S_APB1, 0}, 469*fcfd1436STali Perry {NPCM7XX_CLKEN1, 1, "spi3-gate", NPCM7XX_CLK_S_AHB, 0}, 470*fcfd1436STali Perry {NPCM7XX_CLKEN1, 0, "spi0-gate", NPCM7XX_CLK_S_AHB, 0}, 471*fcfd1436STali Perry 472*fcfd1436STali Perry {NPCM7XX_CLKEN2, 31, "cp-gate", NPCM7XX_CLK_S_AHB, 0}, 473*fcfd1436STali Perry {NPCM7XX_CLKEN2, 30, "tock-gate", NPCM7XX_CLK_S_TOCK, 0}, 474*fcfd1436STali Perry /* bit 29 is reserved */ 475*fcfd1436STali Perry {NPCM7XX_CLKEN2, 28, "gmac1-gate", NPCM7XX_CLK_S_AHB, 0}, 476*fcfd1436STali Perry {NPCM7XX_CLKEN2, 27, "usbif-gate", NPCM7XX_CLK_S_USBIF, 0}, 477*fcfd1436STali Perry {NPCM7XX_CLKEN2, 26, "usbhost-gate", NPCM7XX_CLK_S_AHB, 0}, 478*fcfd1436STali Perry {NPCM7XX_CLKEN2, 25, "gmac2-gate", NPCM7XX_CLK_S_AHB, 0}, 479*fcfd1436STali Perry /* bit 24 is reserved */ 480*fcfd1436STali Perry {NPCM7XX_CLKEN2, 23, "pspi2-gate", NPCM7XX_CLK_S_APB5, 0}, 481*fcfd1436STali Perry {NPCM7XX_CLKEN2, 22, "pspi1-gate", NPCM7XX_CLK_S_APB5, 0}, 482*fcfd1436STali Perry {NPCM7XX_CLKEN2, 21, "3des-gate", NPCM7XX_CLK_S_AHB, 0}, 483*fcfd1436STali Perry /* bit 20 is reserved */ 484*fcfd1436STali Perry {NPCM7XX_CLKEN2, 19, "siox2-gate", NPCM7XX_CLK_S_APB3, 0}, 485*fcfd1436STali Perry {NPCM7XX_CLKEN2, 18, "siox1-gate", NPCM7XX_CLK_S_APB3, 0}, 486*fcfd1436STali Perry /* bit 17 is reserved */ 487*fcfd1436STali Perry {NPCM7XX_CLKEN2, 16, "fuse-gate", NPCM7XX_CLK_S_APB4, 0}, 488*fcfd1436STali Perry /* bit 15 is reserved */ 489*fcfd1436STali Perry {NPCM7XX_CLKEN2, 14, "vcd-gate", NPCM7XX_CLK_S_AHB, 0}, 490*fcfd1436STali Perry {NPCM7XX_CLKEN2, 13, "ece-gate", NPCM7XX_CLK_S_AHB, 0}, 491*fcfd1436STali Perry {NPCM7XX_CLKEN2, 12, "vdma-gate", NPCM7XX_CLK_S_AHB, 0}, 492*fcfd1436STali Perry {NPCM7XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM7XX_CLK_S_AHB, 0}, 493*fcfd1436STali Perry {NPCM7XX_CLKEN2, 10, "gfxsys-gate", NPCM7XX_CLK_S_APB1, 0}, 494*fcfd1436STali Perry {NPCM7XX_CLKEN2, 9, "sdhc-gate", NPCM7XX_CLK_S_AHB, 0}, 495*fcfd1436STali Perry {NPCM7XX_CLKEN2, 8, "mmc-gate", NPCM7XX_CLK_S_AHB, 0}, 496*fcfd1436STali Perry {NPCM7XX_CLKEN2, 7, "mft7-gate", NPCM7XX_CLK_S_APB4, 0}, 497*fcfd1436STali Perry {NPCM7XX_CLKEN2, 6, "mft6-gate", NPCM7XX_CLK_S_APB4, 0}, 498*fcfd1436STali Perry {NPCM7XX_CLKEN2, 5, "mft5-gate", NPCM7XX_CLK_S_APB4, 0}, 499*fcfd1436STali Perry {NPCM7XX_CLKEN2, 4, "mft4-gate", NPCM7XX_CLK_S_APB4, 0}, 500*fcfd1436STali Perry {NPCM7XX_CLKEN2, 3, "mft3-gate", NPCM7XX_CLK_S_APB4, 0}, 501*fcfd1436STali Perry {NPCM7XX_CLKEN2, 2, "mft2-gate", NPCM7XX_CLK_S_APB4, 0}, 502*fcfd1436STali Perry {NPCM7XX_CLKEN2, 1, "mft1-gate", NPCM7XX_CLK_S_APB4, 0}, 503*fcfd1436STali Perry {NPCM7XX_CLKEN2, 0, "mft0-gate", NPCM7XX_CLK_S_APB4, 0}, 504*fcfd1436STali Perry 505*fcfd1436STali Perry {NPCM7XX_CLKEN3, 31, "gpiom7-gate", NPCM7XX_CLK_S_APB1, 0}, 506*fcfd1436STali Perry {NPCM7XX_CLKEN3, 30, "gpiom6-gate", NPCM7XX_CLK_S_APB1, 0}, 507*fcfd1436STali Perry {NPCM7XX_CLKEN3, 29, "gpiom5-gate", NPCM7XX_CLK_S_APB1, 0}, 508*fcfd1436STali Perry {NPCM7XX_CLKEN3, 28, "gpiom4-gate", NPCM7XX_CLK_S_APB1, 0}, 509*fcfd1436STali Perry {NPCM7XX_CLKEN3, 27, "gpiom3-gate", NPCM7XX_CLK_S_APB1, 0}, 510*fcfd1436STali Perry {NPCM7XX_CLKEN3, 26, "gpiom2-gate", NPCM7XX_CLK_S_APB1, 0}, 511*fcfd1436STali Perry {NPCM7XX_CLKEN3, 25, "gpiom1-gate", NPCM7XX_CLK_S_APB1, 0}, 512*fcfd1436STali Perry {NPCM7XX_CLKEN3, 24, "gpiom0-gate", NPCM7XX_CLK_S_APB1, 0}, 513*fcfd1436STali Perry {NPCM7XX_CLKEN3, 23, "espi-gate", NPCM7XX_CLK_S_APB2, 0}, 514*fcfd1436STali Perry {NPCM7XX_CLKEN3, 22, "smb11-gate", NPCM7XX_CLK_S_APB2, 0}, 515*fcfd1436STali Perry {NPCM7XX_CLKEN3, 21, "smb10-gate", NPCM7XX_CLK_S_APB2, 0}, 516*fcfd1436STali Perry {NPCM7XX_CLKEN3, 20, "smb9-gate", NPCM7XX_CLK_S_APB2, 0}, 517*fcfd1436STali Perry {NPCM7XX_CLKEN3, 19, "smb8-gate", NPCM7XX_CLK_S_APB2, 0}, 518*fcfd1436STali Perry {NPCM7XX_CLKEN3, 18, "smb15-gate", NPCM7XX_CLK_S_APB2, 0}, 519*fcfd1436STali Perry {NPCM7XX_CLKEN3, 17, "rng-gate", NPCM7XX_CLK_S_APB1, 0}, 520*fcfd1436STali Perry {NPCM7XX_CLKEN3, 16, "timer10_14-gate", NPCM7XX_CLK_S_APB1, 0}, 521*fcfd1436STali Perry {NPCM7XX_CLKEN3, 15, "pcirc-gate", NPCM7XX_CLK_S_AHB, 0}, 522*fcfd1436STali Perry {NPCM7XX_CLKEN3, 14, "sececc-gate", NPCM7XX_CLK_S_AHB, 0}, 523*fcfd1436STali Perry {NPCM7XX_CLKEN3, 13, "sha-gate", NPCM7XX_CLK_S_AHB, 0}, 524*fcfd1436STali Perry {NPCM7XX_CLKEN3, 12, "smb14-gate", NPCM7XX_CLK_S_APB2, 0}, 525*fcfd1436STali Perry /* bit 11 is reserved */ 526*fcfd1436STali Perry /* bit 10 is reserved */ 527*fcfd1436STali Perry {NPCM7XX_CLKEN3, 9, "pcimbx-gate", NPCM7XX_CLK_S_AHB, 0}, 528*fcfd1436STali Perry /* bit 8 is reserved */ 529*fcfd1436STali Perry {NPCM7XX_CLKEN3, 7, "usbdev9-gate", NPCM7XX_CLK_S_AHB, 0}, 530*fcfd1436STali Perry {NPCM7XX_CLKEN3, 6, "usbdev8-gate", NPCM7XX_CLK_S_AHB, 0}, 531*fcfd1436STali Perry {NPCM7XX_CLKEN3, 5, "usbdev7-gate", NPCM7XX_CLK_S_AHB, 0}, 532*fcfd1436STali Perry {NPCM7XX_CLKEN3, 4, "usbdev0-gate", NPCM7XX_CLK_S_AHB, 0}, 533*fcfd1436STali Perry {NPCM7XX_CLKEN3, 3, "smb13-gate", NPCM7XX_CLK_S_APB2, 0}, 534*fcfd1436STali Perry {NPCM7XX_CLKEN3, 2, "spix-gate", NPCM7XX_CLK_S_AHB, 0}, 535*fcfd1436STali Perry {NPCM7XX_CLKEN3, 1, "smb12-gate", NPCM7XX_CLK_S_APB2, 0}, 536*fcfd1436STali Perry {NPCM7XX_CLKEN3, 0, "pwmm1-gate", NPCM7XX_CLK_S_APB3, 0}, 537*fcfd1436STali Perry }; 538*fcfd1436STali Perry 539*fcfd1436STali Perry static DEFINE_SPINLOCK(npcm7xx_clk_lock); 540*fcfd1436STali Perry 541*fcfd1436STali Perry static void __init npcm7xx_clk_init(struct device_node *clk_np) 542*fcfd1436STali Perry { 543*fcfd1436STali Perry struct clk_hw_onecell_data *npcm7xx_clk_data; 544*fcfd1436STali Perry void __iomem *clk_base; 545*fcfd1436STali Perry struct resource res; 546*fcfd1436STali Perry struct clk_hw *hw; 547*fcfd1436STali Perry int ret; 548*fcfd1436STali Perry int i; 549*fcfd1436STali Perry 550*fcfd1436STali Perry ret = of_address_to_resource(clk_np, 0, &res); 551*fcfd1436STali Perry if (ret) { 552*fcfd1436STali Perry pr_err("%s: failed to get resource, ret %d\n", clk_np->name, 553*fcfd1436STali Perry ret); 554*fcfd1436STali Perry return; 555*fcfd1436STali Perry } 556*fcfd1436STali Perry 557*fcfd1436STali Perry clk_base = ioremap(res.start, resource_size(&res)); 558*fcfd1436STali Perry if (IS_ERR(clk_base)) 559*fcfd1436STali Perry goto npcm7xx_init_error; 560*fcfd1436STali Perry 561*fcfd1436STali Perry npcm7xx_clk_data = kzalloc(sizeof(*npcm7xx_clk_data->hws) * 562*fcfd1436STali Perry NPCM7XX_NUM_CLOCKS + sizeof(npcm7xx_clk_data), GFP_KERNEL); 563*fcfd1436STali Perry if (!npcm7xx_clk_data) 564*fcfd1436STali Perry goto npcm7xx_init_np_err; 565*fcfd1436STali Perry 566*fcfd1436STali Perry npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS; 567*fcfd1436STali Perry 568*fcfd1436STali Perry for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++) 569*fcfd1436STali Perry npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 570*fcfd1436STali Perry 571*fcfd1436STali Perry /* Register plls */ 572*fcfd1436STali Perry for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) { 573*fcfd1436STali Perry const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i]; 574*fcfd1436STali Perry 575*fcfd1436STali Perry hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg, 576*fcfd1436STali Perry pll_data->name, pll_data->parent_name, pll_data->flags); 577*fcfd1436STali Perry if (IS_ERR(hw)) { 578*fcfd1436STali Perry pr_err("npcm7xx_clk: Can't register pll\n"); 579*fcfd1436STali Perry goto npcm7xx_init_fail; 580*fcfd1436STali Perry } 581*fcfd1436STali Perry 582*fcfd1436STali Perry if (pll_data->onecell_idx >= 0) 583*fcfd1436STali Perry npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw; 584*fcfd1436STali Perry } 585*fcfd1436STali Perry 586*fcfd1436STali Perry /* Register fixed dividers */ 587*fcfd1436STali Perry hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2, 588*fcfd1436STali Perry NPCM7XX_CLK_S_PLL1, 0, 1, 2); 589*fcfd1436STali Perry if (IS_ERR(hw)) { 590*fcfd1436STali Perry pr_err("npcm7xx_clk: Can't register fixed div\n"); 591*fcfd1436STali Perry goto npcm7xx_init_fail; 592*fcfd1436STali Perry } 593*fcfd1436STali Perry 594*fcfd1436STali Perry hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2, 595*fcfd1436STali Perry NPCM7XX_CLK_S_PLL2, 0, 1, 2); 596*fcfd1436STali Perry if (IS_ERR(hw)) { 597*fcfd1436STali Perry pr_err("npcm7xx_clk: Can't register div2\n"); 598*fcfd1436STali Perry goto npcm7xx_init_fail; 599*fcfd1436STali Perry } 600*fcfd1436STali Perry 601*fcfd1436STali Perry /* Register muxes */ 602*fcfd1436STali Perry for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) { 603*fcfd1436STali Perry const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i]; 604*fcfd1436STali Perry 605*fcfd1436STali Perry hw = clk_hw_register_mux_table(NULL, 606*fcfd1436STali Perry mux_data->name, 607*fcfd1436STali Perry mux_data->parent_names, mux_data->num_parents, 608*fcfd1436STali Perry mux_data->flags, clk_base + NPCM7XX_CLKSEL, 609*fcfd1436STali Perry mux_data->shift, mux_data->mask, 0, 610*fcfd1436STali Perry mux_data->table, &npcm7xx_clk_lock); 611*fcfd1436STali Perry 612*fcfd1436STali Perry if (IS_ERR(hw)) { 613*fcfd1436STali Perry pr_err("npcm7xx_clk: Can't register mux\n"); 614*fcfd1436STali Perry goto npcm7xx_init_fail; 615*fcfd1436STali Perry } 616*fcfd1436STali Perry 617*fcfd1436STali Perry if (mux_data->onecell_idx >= 0) 618*fcfd1436STali Perry npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw; 619*fcfd1436STali Perry } 620*fcfd1436STali Perry 621*fcfd1436STali Perry /* Register clock dividers specified in npcm7xx_divs */ 622*fcfd1436STali Perry for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) { 623*fcfd1436STali Perry const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i]; 624*fcfd1436STali Perry 625*fcfd1436STali Perry hw = clk_hw_register_divider(NULL, div_data->name, 626*fcfd1436STali Perry div_data->parent_name, 627*fcfd1436STali Perry div_data->flags, 628*fcfd1436STali Perry clk_base + div_data->reg, 629*fcfd1436STali Perry div_data->shift, div_data->width, 630*fcfd1436STali Perry div_data->clk_divider_flags, &npcm7xx_clk_lock); 631*fcfd1436STali Perry if (IS_ERR(hw)) { 632*fcfd1436STali Perry pr_err("npcm7xx_clk: Can't register div table\n"); 633*fcfd1436STali Perry goto npcm7xx_init_fail; 634*fcfd1436STali Perry } 635*fcfd1436STali Perry 636*fcfd1436STali Perry if (div_data->onecell_idx >= 0) 637*fcfd1436STali Perry npcm7xx_clk_data->hws[div_data->onecell_idx] = hw; 638*fcfd1436STali Perry } 639*fcfd1436STali Perry 640*fcfd1436STali Perry ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, 641*fcfd1436STali Perry npcm7xx_clk_data); 642*fcfd1436STali Perry if (ret) 643*fcfd1436STali Perry pr_err("failed to add DT provider: %d\n", ret); 644*fcfd1436STali Perry 645*fcfd1436STali Perry of_node_put(clk_np); 646*fcfd1436STali Perry 647*fcfd1436STali Perry return; 648*fcfd1436STali Perry 649*fcfd1436STali Perry npcm7xx_init_fail: 650*fcfd1436STali Perry kfree(npcm7xx_clk_data->hws); 651*fcfd1436STali Perry npcm7xx_init_np_err: 652*fcfd1436STali Perry iounmap(clk_base); 653*fcfd1436STali Perry npcm7xx_init_error: 654*fcfd1436STali Perry of_node_put(clk_np); 655*fcfd1436STali Perry } 656*fcfd1436STali Perry CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init); 657