1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner 4 * Pin compatible with the LMK0482x family 5 * 6 * Datasheet: https://www.ti.com/lit/ds/symlink/lmk04832.pdf 7 * 8 * Copyright (c) 2020, Xiphos Systems Corp. 9 * 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/device.h> 16 #include <linux/gcd.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/module.h> 19 #include <linux/regmap.h> 20 #include <linux/spi/spi.h> 21 22 /* 0x000 - 0x00d System Functions */ 23 #define LMK04832_REG_RST3W 0x000 24 #define LMK04832_BIT_RESET BIT(7) 25 #define LMK04832_BIT_SPI_3WIRE_DIS BIT(4) 26 #define LMK04832_REG_POWERDOWN 0x002 27 #define LMK04832_REG_ID_DEV_TYPE 0x003 28 #define LMK04832_REG_ID_PROD_MSB 0x004 29 #define LMK04832_REG_ID_PROD_LSB 0x005 30 #define LMK04832_REG_ID_MASKREV 0x006 31 #define LMK04832_REG_ID_VNDR_MSB 0x00c 32 #define LMK04832_REG_ID_VNDR_LSB 0x00d 33 34 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */ 35 #define LMK04832_REG_CLKOUT_CTRL0(ch) (0x100 + (ch >> 1) * 8) 36 #define LMK04832_BIT_DCLK_DIV_LSB GENMASK(7, 0) 37 #define LMK04832_REG_CLKOUT_CTRL1(ch) (0x101 + (ch >> 1) * 8) 38 #define LMK04832_BIT_DCLKX_Y_DDLY_LSB GENMASK(7, 0) 39 #define LMK04832_REG_CLKOUT_CTRL2(ch) (0x102 + (ch >> 1) * 8) 40 #define LMK04832_BIT_CLKOUTX_Y_PD BIT(7) 41 #define LMK04832_BIT_DCLKX_Y_DDLY_PD BIT(4) 42 #define LMK04832_BIT_DCLKX_Y_DDLY_MSB GENMASK(3, 2) 43 #define LMK04832_BIT_DCLK_DIV_MSB GENMASK(1, 0) 44 #define LMK04832_REG_CLKOUT_SRC_MUX(ch) (0x103 + (ch % 2) + (ch >> 1) * 8) 45 #define LMK04832_BIT_CLKOUT_SRC_MUX BIT(5) 46 #define LMK04832_REG_CLKOUT_CTRL3(ch) (0x103 + (ch >> 1) * 8) 47 #define LMK04832_BIT_DCLKX_Y_PD BIT(4) 48 #define LMK04832_BIT_DCLKX_Y_DCC BIT(2) 49 #define LMK04832_BIT_DCLKX_Y_HS BIT(0) 50 #define LMK04832_REG_CLKOUT_CTRL4(ch) (0x104 + (ch >> 1) * 8) 51 #define LMK04832_BIT_SCLK_PD BIT(4) 52 #define LMK04832_BIT_SCLKX_Y_DIS_MODE GENMASK(3, 2) 53 #define LMK04832_REG_SCLKX_Y_ADLY(ch) (0x105 + (ch >> 1) * 8) 54 #define LMK04832_REG_SCLKX_Y_DDLY(ch) (0x106 + (ch >> 1) * 8) 55 #define LMK04832_BIT_SCLKX_Y_DDLY GENMASK(3, 0) 56 #define LMK04832_REG_CLKOUT_FMT(ch) (0x107 + (ch >> 1) * 8) 57 #define LMK04832_BIT_CLKOUT_FMT(ch) (ch % 2 ? 0xf0 : 0x0f) 58 #define LMK04832_VAL_CLKOUT_FMT_POWERDOWN 0x00 59 #define LMK04832_VAL_CLKOUT_FMT_LVDS 0x01 60 #define LMK04832_VAL_CLKOUT_FMT_HSDS6 0x02 61 #define LMK04832_VAL_CLKOUT_FMT_HSDS8 0x03 62 #define LMK04832_VAL_CLKOUT_FMT_LVPECL1600 0x04 63 #define LMK04832_VAL_CLKOUT_FMT_LVPECL2000 0x05 64 #define LMK04832_VAL_CLKOUT_FMT_LCPECL 0x06 65 #define LMK04832_VAL_CLKOUT_FMT_CML16 0x07 66 #define LMK04832_VAL_CLKOUT_FMT_CML24 0x08 67 #define LMK04832_VAL_CLKOUT_FMT_CML32 0x09 68 #define LMK04832_VAL_CLKOUT_FMT_CMOS_OFF_INV 0x0a 69 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_OFF 0x0b 70 #define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_INV 0x0c 71 #define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_NOR 0x0d 72 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_INV 0x0e 73 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_NOR 0x0f 74 75 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */ 76 #define LMK04832_REG_VCO_OSCOUT 0x138 77 #define LMK04832_BIT_VCO_MUX GENMASK(6, 5) 78 #define LMK04832_VAL_VCO_MUX_VCO0 0x00 79 #define LMK04832_VAL_VCO_MUX_VCO1 0x01 80 #define LMK04832_VAL_VCO_MUX_EXT 0x02 81 #define LMK04832_REG_SYSREF_OUT 0x139 82 #define LMK04832_BIT_SYSREF_REQ_EN BIT(6) 83 #define LMK04832_BIT_SYSREF_MUX GENMASK(1, 0) 84 #define LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC 0x00 85 #define LMK04832_VAL_SYSREF_MUX_RECLK 0x01 86 #define LMK04832_VAL_SYSREF_MUX_PULSER 0x02 87 #define LMK04832_VAL_SYSREF_MUX_CONTINUOUS 0x03 88 #define LMK04832_REG_SYSREF_DIV_MSB 0x13a 89 #define LMK04832_BIT_SYSREF_DIV_MSB GENMASK(4, 0) 90 #define LMK04832_REG_SYSREF_DIV_LSB 0x13b 91 #define LMK04832_REG_SYSREF_DDLY_MSB 0x13c 92 #define LMK04832_BIT_SYSREF_DDLY_MSB GENMASK(4, 0) 93 #define LMK04832_REG_SYSREF_DDLY_LSB 0x13d 94 #define LMK04832_REG_SYSREF_PULSE_CNT 0x13e 95 #define LMK04832_REG_FB_CTRL 0x13f 96 #define LMK04832_BIT_PLL2_RCLK_MUX BIT(7) 97 #define LMK04832_VAL_PLL2_RCLK_MUX_OSCIN 0x00 98 #define LMK04832_VAL_PLL2_RCLK_MUX_CLKIN 0x01 99 #define LMK04832_BIT_PLL2_NCLK_MUX BIT(5) 100 #define LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P 0x00 101 #define LMK04832_VAL_PLL2_NCLK_MUX_FB_MUX 0x01 102 #define LMK04832_BIT_FB_MUX_EN BIT(0) 103 #define LMK04832_REG_MAIN_PD 0x140 104 #define LMK04832_BIT_PLL1_PD BIT(7) 105 #define LMK04832_BIT_VCO_LDO_PD BIT(6) 106 #define LMK04832_BIT_VCO_PD BIT(5) 107 #define LMK04832_BIT_OSCIN_PD BIT(4) 108 #define LMK04832_BIT_SYSREF_GBL_PD BIT(3) 109 #define LMK04832_BIT_SYSREF_PD BIT(2) 110 #define LMK04832_BIT_SYSREF_DDLY_PD BIT(1) 111 #define LMK04832_BIT_SYSREF_PLSR_PD BIT(0) 112 #define LMK04832_REG_SYNC 0x143 113 #define LMK04832_BIT_SYNC_CLR BIT(7) 114 #define LMK04832_BIT_SYNC_1SHOT_EN BIT(6) 115 #define LMK04832_BIT_SYNC_POL BIT(5) 116 #define LMK04832_BIT_SYNC_EN BIT(4) 117 #define LMK04832_BIT_SYNC_MODE GENMASK(1, 0) 118 #define LMK04832_VAL_SYNC_MODE_OFF 0x00 119 #define LMK04832_VAL_SYNC_MODE_ON 0x01 120 #define LMK04832_VAL_SYNC_MODE_PULSER_PIN 0x02 121 #define LMK04832_VAL_SYNC_MODE_PULSER_SPI 0x03 122 #define LMK04832_REG_SYNC_DIS 0x144 123 124 /* 0x146 - 0x14a CLKin Control */ 125 #define LMK04832_REG_CLKIN_SEL0 0x148 126 #define LMK04832_REG_CLKIN_SEL1 0x149 127 #define LMK04832_REG_CLKIN_RST 0x14a 128 #define LMK04832_BIT_SDIO_RDBK_TYPE BIT(6) 129 #define LMK04832_BIT_CLKIN_SEL_MUX GENMASK(5, 3) 130 #define LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK 0x06 131 #define LMK04832_BIT_CLKIN_SEL_TYPE GENMASK(2, 0) 132 #define LMK04832_VAL_CLKIN_SEL_TYPE_OUT 0x03 133 134 /* 0x14b - 0x152 Holdover */ 135 136 /* 0x153 - 0x15f PLL1 Configuration */ 137 138 /* 0x160 - 0x16e PLL2 Configuration */ 139 #define LMK04832_REG_PLL2_R_MSB 0x160 140 #define LMK04832_BIT_PLL2_R_MSB GENMASK(3, 0) 141 #define LMK04832_REG_PLL2_R_LSB 0x161 142 #define LMK04832_REG_PLL2_MISC 0x162 143 #define LMK04832_BIT_PLL2_MISC_P GENMASK(7, 5) 144 #define LMK04832_BIT_PLL2_MISC_REF_2X_EN BIT(0) 145 #define LMK04832_REG_PLL2_N_CAL_0 0x163 146 #define LMK04832_BIT_PLL2_N_CAL_0 GENMASK(1, 0) 147 #define LMK04832_REG_PLL2_N_CAL_1 0x164 148 #define LMK04832_REG_PLL2_N_CAL_2 0x165 149 #define LMK04832_REG_PLL2_N_0 0x166 150 #define LMK04832_BIT_PLL2_N_0 GENMASK(1, 0) 151 #define LMK04832_REG_PLL2_N_1 0x167 152 #define LMK04832_REG_PLL2_N_2 0x168 153 #define LMK04832_REG_PLL2_DLD_CNT_MSB 0x16a 154 #define LMK04832_REG_PLL2_DLD_CNT_LSB 0x16b 155 #define LMK04832_REG_PLL2_LD 0x16e 156 #define LMK04832_BIT_PLL2_LD_MUX GENMASK(7, 3) 157 #define LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD 0x02 158 #define LMK04832_BIT_PLL2_LD_TYPE GENMASK(2, 0) 159 #define LMK04832_VAL_PLL2_LD_TYPE_OUT_PP 0x03 160 161 /* 0x16F - 0x555 Misc Registers */ 162 #define LMK04832_REG_PLL2_PD 0x173 163 #define LMK04832_BIT_PLL2_PRE_PD BIT(6) 164 #define LMK04832_BIT_PLL2_PD BIT(5) 165 #define LMK04832_REG_PLL1R_RST 0x177 166 #define LMK04832_REG_CLR_PLL_LOST 0x182 167 #define LMK04832_REG_RB_PLL_LD 0x183 168 #define LMK04832_REG_RB_CLK_DAC_VAL_MSB 0x184 169 #define LMK04832_REG_RB_DAC_VAL_LSB 0x185 170 #define LMK04832_REG_RB_HOLDOVER 0x188 171 #define LMK04832_REG_SPI_LOCK 0x555 172 173 enum lmk04832_device_types { 174 LMK04832, 175 }; 176 177 /** 178 * struct lmk04832_device_info - Holds static device information that is 179 * specific to the chip revision 180 * 181 * @pid: Product Identifier 182 * @maskrev: IC version identifier 183 * @num_channels: Number of available output channels (clkout count) 184 * @vco0_range: {min, max} of the VCO0 operating range (in MHz) 185 * @vco1_range: {min, max} of the VCO1 operating range (in MHz) 186 */ 187 struct lmk04832_device_info { 188 u16 pid; 189 u8 maskrev; 190 size_t num_channels; 191 unsigned int vco0_range[2]; 192 unsigned int vco1_range[2]; 193 }; 194 195 static const struct lmk04832_device_info lmk04832_device_info[] = { 196 [LMK04832] = { 197 .pid = 0x63d1, /* WARNING PROD_ID is inverted in the datasheet */ 198 .maskrev = 0x70, 199 .num_channels = 14, 200 .vco0_range = { 2440, 2580 }, 201 .vco1_range = { 2945, 3255 }, 202 }, 203 }; 204 205 enum lmk04832_rdbk_type { 206 RDBK_CLKIN_SEL0, 207 RDBK_CLKIN_SEL1, 208 RDBK_RESET, 209 }; 210 211 struct lmk_dclk { 212 struct lmk04832 *lmk; 213 struct clk_hw hw; 214 u8 id; 215 }; 216 217 struct lmk_clkout { 218 struct lmk04832 *lmk; 219 struct clk_hw hw; 220 bool sysref; 221 u32 format; 222 u8 id; 223 }; 224 225 /** 226 * struct lmk04832 - The LMK04832 device structure 227 * 228 * @dev: reference to a struct device, linked to the spi_device 229 * @regmap: struct regmap instance use to access the chip 230 * @sync_mode: operational mode for SYNC signal 231 * @sysref_mux: select SYSREF source 232 * @sysref_pulse_cnt: number of SYSREF pulses generated while not in continuous 233 * mode. 234 * @sysref_ddly: SYSREF digital delay value 235 * @oscin: PLL2 input clock 236 * @vco: reference to the internal VCO clock 237 * @sclk: reference to the internal sysref clock (SCLK) 238 * @vco_rate: user provided VCO rate 239 * @reset_gpio: reference to the reset GPIO 240 * @dclk: list of internal device clock references. 241 * Each pair of clkout clocks share a single device clock (DCLKX_Y) 242 * @clkout: list of output clock references 243 * @clk_data: holds clkout related data like clk_hw* and number of clocks 244 */ 245 struct lmk04832 { 246 struct device *dev; 247 struct regmap *regmap; 248 249 unsigned int sync_mode; 250 unsigned int sysref_mux; 251 unsigned int sysref_pulse_cnt; 252 unsigned int sysref_ddly; 253 254 struct clk *oscin; 255 struct clk_hw vco; 256 struct clk_hw sclk; 257 unsigned int vco_rate; 258 259 struct gpio_desc *reset_gpio; 260 261 struct lmk_dclk *dclk; 262 struct lmk_clkout *clkout; 263 struct clk_hw_onecell_data *clk_data; 264 }; 265 266 static bool lmk04832_regmap_rd_regs(struct device *dev, unsigned int reg) 267 { 268 switch (reg) { 269 case LMK04832_REG_RST3W ... LMK04832_REG_ID_MASKREV: 270 case LMK04832_REG_ID_VNDR_MSB: 271 case LMK04832_REG_ID_VNDR_LSB: 272 case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB: 273 case LMK04832_REG_PLL2_LD: 274 case LMK04832_REG_PLL2_PD: 275 case LMK04832_REG_PLL1R_RST: 276 case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB: 277 case LMK04832_REG_RB_HOLDOVER: 278 case LMK04832_REG_SPI_LOCK: 279 return true; 280 default: 281 return false; 282 }; 283 } 284 285 static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg) 286 { 287 switch (reg) { 288 case LMK04832_REG_RST3W: 289 case LMK04832_REG_POWERDOWN: 290 return true; 291 case LMK04832_REG_ID_DEV_TYPE ... LMK04832_REG_ID_MASKREV: 292 case LMK04832_REG_ID_VNDR_MSB: 293 case LMK04832_REG_ID_VNDR_LSB: 294 return false; 295 case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB: 296 case LMK04832_REG_PLL2_LD: 297 case LMK04832_REG_PLL2_PD: 298 case LMK04832_REG_PLL1R_RST: 299 case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB: 300 case LMK04832_REG_RB_HOLDOVER: 301 case LMK04832_REG_SPI_LOCK: 302 return true; 303 default: 304 return false; 305 }; 306 } 307 308 static const struct regmap_config regmap_config = { 309 .name = "lmk04832", 310 .reg_bits = 16, 311 .val_bits = 8, 312 .use_single_read = 1, 313 .use_single_write = 1, 314 .read_flag_mask = 0x80, 315 .write_flag_mask = 0x00, 316 .readable_reg = lmk04832_regmap_rd_regs, 317 .writeable_reg = lmk04832_regmap_wr_regs, 318 .cache_type = REGCACHE_NONE, 319 .max_register = LMK04832_REG_SPI_LOCK, 320 }; 321 322 static int lmk04832_vco_is_enabled(struct clk_hw *hw) 323 { 324 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); 325 unsigned int tmp; 326 int ret; 327 328 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp); 329 if (ret) 330 return ret; 331 332 return !(FIELD_GET(LMK04832_BIT_OSCIN_PD, tmp) | 333 FIELD_GET(LMK04832_BIT_VCO_PD, tmp) | 334 FIELD_GET(LMK04832_BIT_VCO_LDO_PD, tmp)); 335 } 336 337 static int lmk04832_vco_prepare(struct clk_hw *hw) 338 { 339 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); 340 int ret; 341 342 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD, 343 LMK04832_BIT_PLL2_PRE_PD | 344 LMK04832_BIT_PLL2_PD, 345 0x00); 346 if (ret) 347 return ret; 348 349 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, 350 LMK04832_BIT_VCO_LDO_PD | 351 LMK04832_BIT_VCO_PD | 352 LMK04832_BIT_OSCIN_PD, 0x00); 353 } 354 355 static void lmk04832_vco_unprepare(struct clk_hw *hw) 356 { 357 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); 358 359 regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD, 360 LMK04832_BIT_PLL2_PRE_PD | LMK04832_BIT_PLL2_PD, 361 0xff); 362 363 /* Don't set LMK04832_BIT_OSCIN_PD since other clocks depend on it */ 364 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, 365 LMK04832_BIT_VCO_LDO_PD | LMK04832_BIT_VCO_PD, 0xff); 366 } 367 368 static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw, 369 unsigned long prate) 370 { 371 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); 372 const unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7}; 373 unsigned int pll2_n, p, pll2_r; 374 unsigned int pll2_misc; 375 unsigned long vco_rate; 376 u8 tmp[3]; 377 int ret; 378 379 ret = regmap_read(lmk->regmap, LMK04832_REG_PLL2_MISC, &pll2_misc); 380 if (ret) 381 return ret; 382 383 p = FIELD_GET(LMK04832_BIT_PLL2_MISC_P, pll2_misc); 384 385 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_N_0, &tmp, 3); 386 if (ret) 387 return ret; 388 389 pll2_n = FIELD_PREP(0x030000, tmp[0]) | 390 FIELD_PREP(0x00ff00, tmp[1]) | 391 FIELD_PREP(0x0000ff, tmp[2]); 392 393 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_R_MSB, &tmp, 2); 394 if (ret) 395 return ret; 396 397 pll2_r = FIELD_PREP(0x0f00, tmp[0]) | 398 FIELD_PREP(0x00ff, tmp[1]); 399 400 vco_rate = (prate << FIELD_GET(LMK04832_BIT_PLL2_MISC_REF_2X_EN, 401 pll2_misc)) * pll2_n * pll2_p[p] / pll2_r; 402 403 return vco_rate; 404 } 405 406 /** 407 * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges 408 * 409 * @lmk: Reference to the lmk device 410 * @rate: Desired output rate for the VCO 411 * 412 * The LMK04832 has 2 internal VCO, each with independent operating ranges. 413 * Use the device_info structure to determine which VCO to use based on rate. 414 * 415 * Returns: VCO_MUX value or negative errno. 416 */ 417 static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate) 418 { 419 struct spi_device *spi = to_spi_device(lmk->dev); 420 const struct lmk04832_device_info *info; 421 unsigned long mhz = rate / 1000000; 422 423 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data]; 424 425 if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1]) 426 return LMK04832_VAL_VCO_MUX_VCO0; 427 428 if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1]) 429 return LMK04832_VAL_VCO_MUX_VCO1; 430 431 dev_err(lmk->dev, "%lu Hz is out of VCO ranges\n", rate); 432 return -ERANGE; 433 } 434 435 /** 436 * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency 437 * 438 * @prate: parent rate to the PLL2, usually OSCin 439 * @rate: Desired output rate for the VCO 440 * @n: reference to PLL2_N 441 * @p: reference to PLL2_P 442 * @r: reference to PLL2_R 443 * 444 * This functions assumes LMK04832_BIT_PLL2_MISC_REF_2X_EN is set since it is 445 * recommended in the datasheet because a higher phase detector frequencies 446 * makes the design of wider loop bandwidth filters possible. 447 * 448 * the VCO rate can be calculated using the following expression: 449 * 450 * VCO = OSCin * 2 * PLL2_N * PLL2_P / PLL2_R 451 * 452 * Returns: vco rate or negative errno. 453 */ 454 static long lmk04832_calc_pll2_params(unsigned long prate, unsigned long rate, 455 unsigned int *n, unsigned int *p, 456 unsigned int *r) 457 { 458 unsigned int pll2_n, pll2_p, pll2_r; 459 unsigned long num, div; 460 461 /* Set PLL2_P to a fixed value to simplify optimizations */ 462 pll2_p = 2; 463 464 div = gcd(rate, prate); 465 466 num = DIV_ROUND_CLOSEST(rate, div); 467 pll2_r = DIV_ROUND_CLOSEST(prate, div); 468 469 if (num > 4) { 470 pll2_n = num >> 2; 471 } else { 472 pll2_r = pll2_r << 2; 473 pll2_n = num; 474 } 475 476 if (pll2_n < 1 || pll2_n > 0x03ffff) 477 return -EINVAL; 478 if (pll2_r < 1 || pll2_r > 0xfff) 479 return -EINVAL; 480 481 *n = pll2_n; 482 *p = pll2_p; 483 *r = pll2_r; 484 485 return DIV_ROUND_CLOSEST(prate * 2 * pll2_p * pll2_n, pll2_r); 486 } 487 488 static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate, 489 unsigned long *prate) 490 { 491 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); 492 unsigned int n, p, r; 493 long vco_rate; 494 int ret; 495 496 ret = lmk04832_check_vco_ranges(lmk, rate); 497 if (ret < 0) 498 return ret; 499 500 vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r); 501 if (vco_rate < 0) { 502 dev_err(lmk->dev, "PLL2 parameters out of range\n"); 503 return vco_rate; 504 } 505 506 if (rate != vco_rate) 507 return -EINVAL; 508 509 return vco_rate; 510 } 511 512 static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate, 513 unsigned long prate) 514 { 515 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); 516 unsigned int n, p, r; 517 long vco_rate; 518 int vco_mux; 519 int ret; 520 521 vco_mux = lmk04832_check_vco_ranges(lmk, rate); 522 if (vco_mux < 0) 523 return vco_mux; 524 525 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT, 526 LMK04832_BIT_VCO_MUX, 527 FIELD_PREP(LMK04832_BIT_VCO_MUX, vco_mux)); 528 if (ret) 529 return ret; 530 531 vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r); 532 if (vco_rate < 0) { 533 dev_err(lmk->dev, "failed to determine PLL2 parameters\n"); 534 return vco_rate; 535 } 536 537 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_R_MSB, 538 LMK04832_BIT_PLL2_R_MSB, 539 FIELD_GET(0x000700, r)); 540 if (ret) 541 return ret; 542 543 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_R_LSB, 544 FIELD_GET(0x0000ff, r)); 545 if (ret) 546 return ret; 547 548 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC, 549 LMK04832_BIT_PLL2_MISC_P, 550 FIELD_PREP(LMK04832_BIT_PLL2_MISC_P, p)); 551 if (ret) 552 return ret; 553 554 /* 555 * PLL2_N registers must be programmed after other PLL2 dividers are 556 * programmed to ensure proper VCO frequency calibration 557 */ 558 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0, 559 FIELD_GET(0x030000, n)); 560 if (ret) 561 return ret; 562 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_1, 563 FIELD_GET(0x00ff00, n)); 564 if (ret) 565 return ret; 566 567 return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2, 568 FIELD_GET(0x0000ff, n)); 569 } 570 571 static const struct clk_ops lmk04832_vco_ops = { 572 .is_enabled = lmk04832_vco_is_enabled, 573 .prepare = lmk04832_vco_prepare, 574 .unprepare = lmk04832_vco_unprepare, 575 .recalc_rate = lmk04832_vco_recalc_rate, 576 .round_rate = lmk04832_vco_round_rate, 577 .set_rate = lmk04832_vco_set_rate, 578 }; 579 580 /* 581 * lmk04832_register_vco - Initialize the internal VCO and clock distribution 582 * path in PLL2 single loop mode. 583 */ 584 static int lmk04832_register_vco(struct lmk04832 *lmk) 585 { 586 const char *parent_names[1]; 587 struct clk_init_data init; 588 int ret; 589 590 init.name = "lmk-vco"; 591 parent_names[0] = __clk_get_name(lmk->oscin); 592 init.parent_names = parent_names; 593 594 init.ops = &lmk04832_vco_ops; 595 init.num_parents = 1; 596 597 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT, 598 LMK04832_BIT_VCO_MUX, 599 FIELD_PREP(LMK04832_BIT_VCO_MUX, 600 LMK04832_VAL_VCO_MUX_VCO1)); 601 if (ret) 602 return ret; 603 604 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_FB_CTRL, 605 LMK04832_BIT_PLL2_RCLK_MUX | 606 LMK04832_BIT_PLL2_NCLK_MUX, 607 FIELD_PREP(LMK04832_BIT_PLL2_RCLK_MUX, 608 LMK04832_VAL_PLL2_RCLK_MUX_OSCIN)| 609 FIELD_PREP(LMK04832_BIT_PLL2_NCLK_MUX, 610 LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P)); 611 if (ret) 612 return ret; 613 614 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC, 615 LMK04832_BIT_PLL2_MISC_REF_2X_EN, 616 LMK04832_BIT_PLL2_MISC_REF_2X_EN); 617 if (ret) 618 return ret; 619 620 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_LD, 621 FIELD_PREP(LMK04832_BIT_PLL2_LD_MUX, 622 LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD) | 623 FIELD_PREP(LMK04832_BIT_PLL2_LD_TYPE, 624 LMK04832_VAL_PLL2_LD_TYPE_OUT_PP)); 625 if (ret) 626 return ret; 627 628 lmk->vco.init = &init; 629 return devm_clk_hw_register(lmk->dev, &lmk->vco); 630 } 631 632 static int lmk04832_clkout_set_ddly(struct lmk04832 *lmk, int id) 633 { 634 const int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0}; 635 unsigned int sclkx_y_ddly = 10; 636 unsigned int dclkx_y_ddly; 637 unsigned int dclkx_y_div; 638 unsigned int sysref_ddly; 639 unsigned int dclkx_y_hs; 640 unsigned int lsb, msb; 641 int ret; 642 643 ret = regmap_update_bits(lmk->regmap, 644 LMK04832_REG_CLKOUT_CTRL2(id), 645 LMK04832_BIT_DCLKX_Y_DDLY_PD, 646 FIELD_PREP(LMK04832_BIT_DCLKX_Y_DDLY_PD, 0)); 647 if (ret) 648 return ret; 649 650 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb); 651 if (ret) 652 return ret; 653 654 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb); 655 if (ret) 656 return ret; 657 658 sysref_ddly = FIELD_GET(LMK04832_BIT_SYSREF_DDLY_MSB, msb) << 8 | lsb; 659 660 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb); 661 if (ret) 662 return ret; 663 664 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb); 665 if (ret) 666 return ret; 667 668 dclkx_y_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb; 669 670 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb); 671 if (ret) 672 return ret; 673 674 dclkx_y_hs = FIELD_GET(LMK04832_BIT_DCLKX_Y_HS, lsb); 675 676 dclkx_y_ddly = sysref_ddly + 1 - 677 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7] - 678 dclkx_y_hs + sclkx_y_ddly; 679 680 if (dclkx_y_ddly < 7 || dclkx_y_ddly > 0x3fff) { 681 dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n", 682 dclkx_y_ddly); 683 return -EINVAL; 684 } 685 686 ret = regmap_write(lmk->regmap, 687 LMK04832_REG_SCLKX_Y_DDLY(id), 688 FIELD_GET(LMK04832_BIT_SCLKX_Y_DDLY, sclkx_y_ddly)); 689 if (ret) 690 return ret; 691 692 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id), 693 FIELD_GET(0x00ff, dclkx_y_ddly)); 694 if (ret) 695 return ret; 696 697 dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, " 698 "dclk_div_adj=%+d, dclkx_y_hs=%u, sclkx_y_ddly=%u\n", 699 id, sysref_ddly, dclkx_y_ddly, 700 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7], 701 dclkx_y_hs, sclkx_y_ddly); 702 703 return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), 704 LMK04832_BIT_DCLKX_Y_DDLY_MSB, 705 FIELD_GET(0x0300, dclkx_y_ddly)); 706 } 707 708 /** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk 709 * and dclk 710 * 711 * @lmk: Reference to the lmk device 712 * 713 * The synchronization sequence: 714 * - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31 715 * (8.3.3.1 How to enable SYSREF) 716 * - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972 717 * 718 * Returns 0 or negative errno. 719 */ 720 static int lmk04832_sclk_sync_sequence(struct lmk04832 *lmk) 721 { 722 int ret; 723 int i; 724 725 /* 1. (optional) mute all sysref_outputs during synchronization */ 726 /* 2. Enable and write device clock digital delay to applicable clocks */ 727 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, 728 LMK04832_BIT_SYSREF_DDLY_PD, 729 FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0)); 730 if (ret) 731 return ret; 732 733 for (i = 0; i < lmk->clk_data->num; i += 2) { 734 ret = lmk04832_clkout_set_ddly(lmk, i); 735 if (ret) 736 return ret; 737 } 738 739 /* 740 * 3. Configure SYNC_MODE to SYNC_PIN and SYSREF_MUX to Normal SYNC, 741 * and clear SYSREF_REQ_EN (see 6.) 742 */ 743 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, 744 LMK04832_BIT_SYSREF_REQ_EN | 745 LMK04832_BIT_SYSREF_MUX, 746 FIELD_PREP(LMK04832_BIT_SYSREF_REQ_EN, 0) | 747 FIELD_PREP(LMK04832_BIT_SYSREF_MUX, 748 LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC)); 749 if (ret) 750 return ret; 751 752 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, 753 LMK04832_BIT_SYNC_MODE, 754 FIELD_PREP(LMK04832_BIT_SYNC_MODE, 755 LMK04832_VAL_SYNC_MODE_ON)); 756 if (ret) 757 return ret; 758 759 /* 4. Clear SYNXC_DISx or applicable clocks and clear SYNC_DISSYSREF */ 760 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00); 761 if (ret) 762 return ret; 763 764 /* 765 * 5. If SCLKX_Y_DDLY != 0, Set SYSREF_CLR=1 for at least 15 clock 766 * distribution path cycles (VCO cycles), then back to 0. In 767 * PLL2-only use case, this will be complete in less than one SPI 768 * transaction. If SYSREF local digital delay is not used, this step 769 * can be skipped. 770 */ 771 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, 772 LMK04832_BIT_SYNC_CLR, 773 FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x01)); 774 if (ret) 775 return ret; 776 777 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, 778 LMK04832_BIT_SYNC_CLR, 779 FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x00)); 780 if (ret) 781 return ret; 782 783 /* 784 * 6. Toggle SYNC_POL state between inverted and not inverted. 785 * If you use an external signal on the SYNC pin instead of toggling 786 * SYNC_POL, make sure that SYSREF_REQ_EN=0 so that the SYSREF_MUX 787 * does not shift into continuous SYSREF mode. 788 */ 789 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, 790 LMK04832_BIT_SYNC_POL, 791 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x01)); 792 if (ret) 793 return ret; 794 795 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, 796 LMK04832_BIT_SYNC_POL, 797 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x00)); 798 if (ret) 799 return ret; 800 801 /* 7. Set all SYNC_DISx=1, including SYNC_DISSYSREF */ 802 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff); 803 if (ret) 804 return ret; 805 806 /* 8. Restore state of SYNC_MODE and SYSREF_MUX to desired values */ 807 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, 808 LMK04832_BIT_SYSREF_MUX, 809 FIELD_PREP(LMK04832_BIT_SYSREF_MUX, 810 lmk->sysref_mux)); 811 if (ret) 812 return ret; 813 814 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, 815 LMK04832_BIT_SYNC_MODE, 816 FIELD_PREP(LMK04832_BIT_SYNC_MODE, 817 lmk->sync_mode)); 818 if (ret) 819 return ret; 820 821 /* 822 * 9. (optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs 823 * during the SYNC event, restore SCLKx_y_DIS_MODE=0 for active state, 824 * or set SYSREF_GBL_PD=0 if SCLKx_y_DIS_MODE is set to a conditional 825 * option. 826 */ 827 828 /* 829 * 10. (optional) To reduce power consumption, after the synchronization 830 * event is complete, DCLKx_y_DDLY_PD=1 and SYSREF_DDLY_PD=1 disable the 831 * digital delay counters (which are only used immediately after the 832 * SYNC pulse to delay the output by some number of VCO counts). 833 */ 834 835 return ret; 836 } 837 838 static int lmk04832_sclk_is_enabled(struct clk_hw *hw) 839 { 840 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); 841 unsigned int tmp; 842 int ret; 843 844 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp); 845 if (ret) 846 return ret; 847 848 return FIELD_GET(LMK04832_BIT_SYSREF_PD, tmp); 849 } 850 851 static int lmk04832_sclk_prepare(struct clk_hw *hw) 852 { 853 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); 854 855 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, 856 LMK04832_BIT_SYSREF_PD, 0x00); 857 } 858 859 static void lmk04832_sclk_unprepare(struct clk_hw *hw) 860 { 861 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); 862 863 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, 864 LMK04832_BIT_SYSREF_PD, LMK04832_BIT_SYSREF_PD); 865 } 866 867 static unsigned long lmk04832_sclk_recalc_rate(struct clk_hw *hw, 868 unsigned long prate) 869 { 870 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); 871 unsigned int sysref_div; 872 u8 tmp[2]; 873 int ret; 874 875 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, &tmp, 2); 876 if (ret) 877 return ret; 878 879 sysref_div = FIELD_GET(LMK04832_BIT_SYSREF_DIV_MSB, tmp[0]) << 8 | 880 tmp[1]; 881 882 return DIV_ROUND_CLOSEST(prate, sysref_div); 883 } 884 885 static long lmk04832_sclk_round_rate(struct clk_hw *hw, unsigned long rate, 886 unsigned long *prate) 887 { 888 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); 889 unsigned long sclk_rate; 890 unsigned int sysref_div; 891 892 sysref_div = DIV_ROUND_CLOSEST(*prate, rate); 893 sclk_rate = DIV_ROUND_CLOSEST(*prate, sysref_div); 894 895 if (sysref_div < 0x07 || sysref_div > 0x1fff) { 896 dev_err(lmk->dev, "SYSREF divider out of range\n"); 897 return -EINVAL; 898 } 899 900 if (rate != sclk_rate) 901 return -EINVAL; 902 903 return sclk_rate; 904 } 905 906 static int lmk04832_sclk_set_rate(struct clk_hw *hw, unsigned long rate, 907 unsigned long prate) 908 { 909 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); 910 unsigned int sysref_div; 911 int ret; 912 913 sysref_div = DIV_ROUND_CLOSEST(prate, rate); 914 915 if (sysref_div < 0x07 || sysref_div > 0x1fff) { 916 dev_err(lmk->dev, "SYSREF divider out of range\n"); 917 return -EINVAL; 918 } 919 920 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, 921 FIELD_GET(0x1f00, sysref_div)); 922 if (ret) 923 return ret; 924 925 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB, 926 FIELD_GET(0x00ff, sysref_div)); 927 if (ret) 928 return ret; 929 930 ret = lmk04832_sclk_sync_sequence(lmk); 931 if (ret) 932 dev_err(lmk->dev, "SYNC sequence failed\n"); 933 934 return ret; 935 } 936 937 static const struct clk_ops lmk04832_sclk_ops = { 938 .is_enabled = lmk04832_sclk_is_enabled, 939 .prepare = lmk04832_sclk_prepare, 940 .unprepare = lmk04832_sclk_unprepare, 941 .recalc_rate = lmk04832_sclk_recalc_rate, 942 .round_rate = lmk04832_sclk_round_rate, 943 .set_rate = lmk04832_sclk_set_rate, 944 }; 945 946 static int lmk04832_register_sclk(struct lmk04832 *lmk) 947 { 948 const char *parent_names[1]; 949 struct clk_init_data init; 950 int ret; 951 952 init.name = "lmk-sclk"; 953 parent_names[0] = clk_hw_get_name(&lmk->vco); 954 init.parent_names = parent_names; 955 956 init.ops = &lmk04832_sclk_ops; 957 init.flags = CLK_SET_RATE_PARENT; 958 init.num_parents = 1; 959 960 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, 961 LMK04832_BIT_SYSREF_MUX, 962 FIELD_PREP(LMK04832_BIT_SYSREF_MUX, 963 lmk->sysref_mux)); 964 if (ret) 965 return ret; 966 967 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, 968 FIELD_GET(0x00ff, lmk->sysref_ddly)); 969 if (ret) 970 return ret; 971 972 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, 973 FIELD_GET(0x1f00, lmk->sysref_ddly)); 974 if (ret) 975 return ret; 976 977 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT, 978 ilog2(lmk->sysref_pulse_cnt)); 979 if (ret) 980 return ret; 981 982 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, 983 LMK04832_BIT_SYSREF_DDLY_PD | 984 LMK04832_BIT_SYSREF_PLSR_PD, 985 FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0) | 986 FIELD_PREP(LMK04832_BIT_SYSREF_PLSR_PD, 0)); 987 if (ret) 988 return ret; 989 990 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC, 991 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0) | 992 FIELD_PREP(LMK04832_BIT_SYNC_EN, 1) | 993 FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode)); 994 if (ret) 995 return ret; 996 997 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff); 998 if (ret) 999 return ret; 1000 1001 lmk->sclk.init = &init; 1002 return devm_clk_hw_register(lmk->dev, &lmk->sclk); 1003 } 1004 1005 static int lmk04832_dclk_is_enabled(struct clk_hw *hw) 1006 { 1007 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); 1008 struct lmk04832 *lmk = dclk->lmk; 1009 unsigned int tmp; 1010 int ret; 1011 1012 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id), 1013 &tmp); 1014 if (ret) 1015 return ret; 1016 1017 return !FIELD_GET(LMK04832_BIT_DCLKX_Y_PD, tmp); 1018 } 1019 1020 static int lmk04832_dclk_prepare(struct clk_hw *hw) 1021 { 1022 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); 1023 struct lmk04832 *lmk = dclk->lmk; 1024 1025 return regmap_update_bits(lmk->regmap, 1026 LMK04832_REG_CLKOUT_CTRL3(dclk->id), 1027 LMK04832_BIT_DCLKX_Y_PD, 0x00); 1028 } 1029 1030 static void lmk04832_dclk_unprepare(struct clk_hw *hw) 1031 { 1032 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); 1033 struct lmk04832 *lmk = dclk->lmk; 1034 1035 regmap_update_bits(lmk->regmap, 1036 LMK04832_REG_CLKOUT_CTRL3(dclk->id), 1037 LMK04832_BIT_DCLKX_Y_PD, 0xff); 1038 } 1039 1040 static unsigned long lmk04832_dclk_recalc_rate(struct clk_hw *hw, 1041 unsigned long prate) 1042 { 1043 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); 1044 struct lmk04832 *lmk = dclk->lmk; 1045 unsigned int dclk_div; 1046 unsigned int lsb, msb; 1047 unsigned long rate; 1048 int ret; 1049 1050 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id), 1051 &lsb); 1052 if (ret) 1053 return ret; 1054 1055 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(dclk->id), 1056 &msb); 1057 if (ret) 1058 return ret; 1059 1060 dclk_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb; 1061 rate = DIV_ROUND_CLOSEST(prate, dclk_div); 1062 1063 return rate; 1064 } 1065 1066 static long lmk04832_dclk_round_rate(struct clk_hw *hw, unsigned long rate, 1067 unsigned long *prate) 1068 { 1069 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); 1070 struct lmk04832 *lmk = dclk->lmk; 1071 unsigned long dclk_rate; 1072 unsigned int dclk_div; 1073 1074 dclk_div = DIV_ROUND_CLOSEST(*prate, rate); 1075 dclk_rate = DIV_ROUND_CLOSEST(*prate, dclk_div); 1076 1077 if (dclk_div < 1 || dclk_div > 0x3ff) { 1078 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw)); 1079 return -EINVAL; 1080 } 1081 1082 if (rate != dclk_rate) 1083 return -EINVAL; 1084 1085 return dclk_rate; 1086 } 1087 1088 static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate, 1089 unsigned long prate) 1090 { 1091 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); 1092 struct lmk04832 *lmk = dclk->lmk; 1093 unsigned int dclk_div; 1094 int ret; 1095 1096 dclk_div = DIV_ROUND_CLOSEST(prate, rate); 1097 1098 if (dclk_div > 0x3ff) { 1099 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw)); 1100 return -EINVAL; 1101 } 1102 1103 /* Enable Duty Cycle Correction */ 1104 if (dclk_div == 1) { 1105 ret = regmap_update_bits(lmk->regmap, 1106 LMK04832_REG_CLKOUT_CTRL3(dclk->id), 1107 LMK04832_BIT_DCLKX_Y_DCC, 1108 FIELD_PREP(LMK04832_BIT_DCLKX_Y_DCC, 1)); 1109 if (ret) 1110 return ret; 1111 } 1112 1113 /* 1114 * While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC 1115 * procedure requires to first program Divide-by-4 and then back to 1116 * Divide-by-2 or Divide-by-3 before doing SYNC. 1117 */ 1118 if (dclk_div == 2 || dclk_div == 3) { 1119 ret = regmap_update_bits(lmk->regmap, 1120 LMK04832_REG_CLKOUT_CTRL2(dclk->id), 1121 LMK04832_BIT_DCLK_DIV_MSB, 0x00); 1122 if (ret) 1123 return ret; 1124 1125 ret = regmap_write(lmk->regmap, 1126 LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04); 1127 if (ret) 1128 return ret; 1129 } 1130 1131 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id), 1132 FIELD_GET(0x0ff, dclk_div)); 1133 if (ret) 1134 return ret; 1135 1136 ret = regmap_update_bits(lmk->regmap, 1137 LMK04832_REG_CLKOUT_CTRL2(dclk->id), 1138 LMK04832_BIT_DCLK_DIV_MSB, 1139 FIELD_GET(0x300, dclk_div)); 1140 if (ret) 1141 return ret; 1142 1143 ret = lmk04832_sclk_sync_sequence(lmk); 1144 if (ret) 1145 dev_err(lmk->dev, "SYNC sequence failed\n"); 1146 1147 return ret; 1148 } 1149 1150 static const struct clk_ops lmk04832_dclk_ops = { 1151 .is_enabled = lmk04832_dclk_is_enabled, 1152 .prepare = lmk04832_dclk_prepare, 1153 .unprepare = lmk04832_dclk_unprepare, 1154 .recalc_rate = lmk04832_dclk_recalc_rate, 1155 .round_rate = lmk04832_dclk_round_rate, 1156 .set_rate = lmk04832_dclk_set_rate, 1157 }; 1158 1159 static int lmk04832_clkout_is_enabled(struct clk_hw *hw) 1160 { 1161 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); 1162 struct lmk04832 *lmk = clkout->lmk; 1163 unsigned int clkoutx_y_pd; 1164 unsigned int sclkx_y_pd; 1165 unsigned int tmp; 1166 u32 enabled; 1167 int ret; 1168 u8 fmt; 1169 1170 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(clkout->id), 1171 &clkoutx_y_pd); 1172 if (ret) 1173 return ret; 1174 1175 enabled = !FIELD_GET(LMK04832_BIT_CLKOUTX_Y_PD, clkoutx_y_pd); 1176 1177 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), 1178 &tmp); 1179 if (ret) 1180 return ret; 1181 1182 if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) { 1183 ret = regmap_read(lmk->regmap, 1184 LMK04832_REG_CLKOUT_CTRL4(clkout->id), 1185 &sclkx_y_pd); 1186 if (ret) 1187 return ret; 1188 1189 enabled = enabled && !FIELD_GET(LMK04832_BIT_SCLK_PD, sclkx_y_pd); 1190 } 1191 1192 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id), 1193 &tmp); 1194 if (ret) 1195 return ret; 1196 1197 if (clkout->id % 2) 1198 fmt = FIELD_GET(0xf0, tmp); 1199 else 1200 fmt = FIELD_GET(0x0f, tmp); 1201 1202 return enabled && !fmt; 1203 } 1204 1205 static int lmk04832_clkout_prepare(struct clk_hw *hw) 1206 { 1207 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); 1208 struct lmk04832 *lmk = clkout->lmk; 1209 unsigned int tmp; 1210 int ret; 1211 1212 if (clkout->format == LMK04832_VAL_CLKOUT_FMT_POWERDOWN) 1213 dev_err(lmk->dev, "prepared %s but format is powerdown\n", 1214 clk_hw_get_name(hw)); 1215 1216 ret = regmap_update_bits(lmk->regmap, 1217 LMK04832_REG_CLKOUT_CTRL2(clkout->id), 1218 LMK04832_BIT_CLKOUTX_Y_PD, 0x00); 1219 if (ret) 1220 return ret; 1221 1222 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), 1223 &tmp); 1224 if (ret) 1225 return ret; 1226 1227 if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) { 1228 ret = regmap_update_bits(lmk->regmap, 1229 LMK04832_REG_CLKOUT_CTRL4(clkout->id), 1230 LMK04832_BIT_SCLK_PD, 0x00); 1231 if (ret) 1232 return ret; 1233 } 1234 1235 return regmap_update_bits(lmk->regmap, 1236 LMK04832_REG_CLKOUT_FMT(clkout->id), 1237 LMK04832_BIT_CLKOUT_FMT(clkout->id), 1238 clkout->format << 4 * (clkout->id % 2)); 1239 } 1240 1241 static void lmk04832_clkout_unprepare(struct clk_hw *hw) 1242 { 1243 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); 1244 struct lmk04832 *lmk = clkout->lmk; 1245 1246 regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id), 1247 LMK04832_BIT_CLKOUT_FMT(clkout->id), 1248 0x00); 1249 } 1250 1251 static int lmk04832_clkout_set_parent(struct clk_hw *hw, uint8_t index) 1252 { 1253 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); 1254 struct lmk04832 *lmk = clkout->lmk; 1255 1256 return regmap_update_bits(lmk->regmap, 1257 LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), 1258 LMK04832_BIT_CLKOUT_SRC_MUX, 1259 FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX, 1260 index)); 1261 } 1262 1263 static uint8_t lmk04832_clkout_get_parent(struct clk_hw *hw) 1264 { 1265 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); 1266 struct lmk04832 *lmk = clkout->lmk; 1267 unsigned int tmp; 1268 int ret; 1269 1270 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), 1271 &tmp); 1272 if (ret) 1273 return ret; 1274 1275 return FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp); 1276 } 1277 1278 static const struct clk_ops lmk04832_clkout_ops = { 1279 .is_enabled = lmk04832_clkout_is_enabled, 1280 .prepare = lmk04832_clkout_prepare, 1281 .unprepare = lmk04832_clkout_unprepare, 1282 .set_parent = lmk04832_clkout_set_parent, 1283 .get_parent = lmk04832_clkout_get_parent, 1284 }; 1285 1286 static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num) 1287 { 1288 char name[] = "lmk-clkoutXX"; 1289 char dclk_name[] = "lmk-dclkXX_YY"; 1290 const char *parent_names[2]; 1291 struct clk_init_data init; 1292 int dclk_num = num / 2; 1293 int ret; 1294 1295 if (num % 2 == 0) { 1296 sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1); 1297 init.name = dclk_name; 1298 parent_names[0] = clk_hw_get_name(&lmk->vco); 1299 init.ops = &lmk04832_dclk_ops; 1300 init.flags = CLK_SET_RATE_PARENT; 1301 init.num_parents = 1; 1302 1303 lmk->dclk[dclk_num].id = num; 1304 lmk->dclk[dclk_num].lmk = lmk; 1305 lmk->dclk[dclk_num].hw.init = &init; 1306 1307 ret = devm_clk_hw_register(lmk->dev, &lmk->dclk[dclk_num].hw); 1308 if (ret) 1309 return ret; 1310 } else { 1311 sprintf(dclk_name, "lmk-dclk%02d_%02d", num - 1, num); 1312 } 1313 1314 if (of_property_read_string_index(lmk->dev->of_node, 1315 "clock-output-names", 1316 num, &init.name)) { 1317 sprintf(name, "lmk-clkout%02d", num); 1318 init.name = name; 1319 } 1320 1321 parent_names[0] = dclk_name; 1322 parent_names[1] = clk_hw_get_name(&lmk->sclk); 1323 init.parent_names = parent_names; 1324 init.ops = &lmk04832_clkout_ops; 1325 init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT; 1326 init.num_parents = ARRAY_SIZE(parent_names); 1327 1328 lmk->clkout[num].id = num; 1329 lmk->clkout[num].lmk = lmk; 1330 lmk->clkout[num].hw.init = &init; 1331 lmk->clk_data->hws[num] = &lmk->clkout[num].hw; 1332 1333 /* Set initial parent */ 1334 regmap_update_bits(lmk->regmap, 1335 LMK04832_REG_CLKOUT_SRC_MUX(num), 1336 LMK04832_BIT_CLKOUT_SRC_MUX, 1337 FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX, 1338 lmk->clkout[num].sysref)); 1339 1340 return devm_clk_hw_register(lmk->dev, &lmk->clkout[num].hw); 1341 } 1342 1343 static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin) 1344 { 1345 int reg; 1346 int ret; 1347 1348 dev_info(lmk->dev, "setting up 4-wire mode\n"); 1349 ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W, 1350 LMK04832_BIT_SPI_3WIRE_DIS); 1351 if (ret) 1352 return ret; 1353 1354 switch (rdbk_pin) { 1355 case RDBK_CLKIN_SEL0: 1356 reg = LMK04832_REG_CLKIN_SEL0; 1357 break; 1358 case RDBK_CLKIN_SEL1: 1359 reg = LMK04832_REG_CLKIN_SEL1; 1360 break; 1361 case RDBK_RESET: 1362 reg = LMK04832_REG_CLKIN_RST; 1363 break; 1364 default: 1365 return -EINVAL; 1366 } 1367 1368 return regmap_write(lmk->regmap, reg, 1369 FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX, 1370 LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) | 1371 FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE, 1372 LMK04832_VAL_CLKIN_SEL_TYPE_OUT)); 1373 } 1374 1375 static int lmk04832_probe(struct spi_device *spi) 1376 { 1377 const struct lmk04832_device_info *info; 1378 int rdbk_pin = RDBK_CLKIN_SEL1; 1379 struct device_node *child; 1380 struct lmk04832 *lmk; 1381 u8 tmp[3]; 1382 int ret; 1383 int i; 1384 1385 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data]; 1386 1387 lmk = devm_kzalloc(&spi->dev, sizeof(struct lmk04832), GFP_KERNEL); 1388 if (!lmk) 1389 return -ENOMEM; 1390 1391 lmk->dev = &spi->dev; 1392 1393 lmk->oscin = devm_clk_get(lmk->dev, "oscin"); 1394 if (IS_ERR(lmk->oscin)) { 1395 dev_err(lmk->dev, "failed to get oscin clock\n"); 1396 return PTR_ERR(lmk->oscin); 1397 } 1398 1399 ret = clk_prepare_enable(lmk->oscin); 1400 if (ret) 1401 return ret; 1402 1403 lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", 1404 GPIOD_OUT_LOW); 1405 1406 lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1, 1407 sizeof(struct lmk_dclk), GFP_KERNEL); 1408 if (!lmk->dclk) { 1409 ret = -ENOMEM; 1410 goto err_disable_oscin; 1411 } 1412 1413 lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels, 1414 sizeof(*lmk->clkout), GFP_KERNEL); 1415 if (!lmk->clkout) { 1416 ret = -ENOMEM; 1417 goto err_disable_oscin; 1418 } 1419 1420 lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws, 1421 info->num_channels), 1422 GFP_KERNEL); 1423 if (!lmk->clk_data) { 1424 ret = -ENOMEM; 1425 goto err_disable_oscin; 1426 } 1427 1428 device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate); 1429 1430 lmk->sysref_ddly = 8; 1431 device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly); 1432 1433 lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS; 1434 device_property_read_u32(lmk->dev, "ti,sysref-mux", 1435 &lmk->sysref_mux); 1436 1437 lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF; 1438 device_property_read_u32(lmk->dev, "ti,sync-mode", 1439 &lmk->sync_mode); 1440 1441 lmk->sysref_pulse_cnt = 4; 1442 device_property_read_u32(lmk->dev, "ti,sysref-pulse-count", 1443 &lmk->sysref_pulse_cnt); 1444 1445 for_each_child_of_node(lmk->dev->of_node, child) { 1446 int reg; 1447 1448 ret = of_property_read_u32(child, "reg", ®); 1449 if (ret) { 1450 dev_err(lmk->dev, "missing reg property in child: %s\n", 1451 child->full_name); 1452 of_node_put(child); 1453 goto err_disable_oscin; 1454 } 1455 1456 of_property_read_u32(child, "ti,clkout-fmt", 1457 &lmk->clkout[reg].format); 1458 1459 if (lmk->clkout[reg].format >= 0x0a && reg % 2 == 0 1460 && reg != 8 && reg != 10) 1461 dev_err(lmk->dev, "invalid format for clkout%02d\n", 1462 reg); 1463 1464 lmk->clkout[reg].sysref = 1465 of_property_read_bool(child, "ti,clkout-sysref"); 1466 } 1467 1468 lmk->regmap = devm_regmap_init_spi(spi, ®map_config); 1469 if (IS_ERR(lmk->regmap)) { 1470 dev_err(lmk->dev, "%s: regmap allocation failed: %ld\n", 1471 1472 __func__, PTR_ERR(lmk->regmap)); 1473 ret = PTR_ERR(lmk->regmap); 1474 goto err_disable_oscin; 1475 } 1476 1477 regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET); 1478 1479 if (!(spi->mode & SPI_3WIRE)) { 1480 device_property_read_u32(lmk->dev, "ti,spi-4wire-rdbk", 1481 &rdbk_pin); 1482 ret = lmk04832_set_spi_rdbk(lmk, rdbk_pin); 1483 if (ret) 1484 goto err_disable_oscin; 1485 } 1486 1487 regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3); 1488 if ((tmp[0] << 8 | tmp[1]) != info->pid || tmp[2] != info->maskrev) { 1489 dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n", 1490 tmp[0] << 8 | tmp[1], tmp[2]); 1491 ret = -EINVAL; 1492 goto err_disable_oscin; 1493 } 1494 1495 ret = lmk04832_register_vco(lmk); 1496 if (ret) { 1497 dev_err(lmk->dev, "failed to init device clock path\n"); 1498 goto err_disable_oscin; 1499 } 1500 1501 if (lmk->vco_rate) { 1502 dev_info(lmk->dev, "setting VCO rate to %u Hz\n", lmk->vco_rate); 1503 ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate); 1504 if (ret) { 1505 dev_err(lmk->dev, "failed to set VCO rate\n"); 1506 goto err_disable_vco; 1507 } 1508 } 1509 1510 ret = lmk04832_register_sclk(lmk); 1511 if (ret) { 1512 dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n"); 1513 goto err_disable_vco; 1514 } 1515 1516 for (i = 0; i < info->num_channels; i++) { 1517 ret = lmk04832_register_clkout(lmk, i); 1518 if (ret) { 1519 dev_err(lmk->dev, "failed to register clk %d\n", i); 1520 goto err_disable_vco; 1521 } 1522 } 1523 1524 lmk->clk_data->num = info->num_channels; 1525 ret = devm_of_clk_add_hw_provider(lmk->dev, of_clk_hw_onecell_get, 1526 lmk->clk_data); 1527 if (ret) { 1528 dev_err(lmk->dev, "failed to add provider (%d)\n", ret); 1529 goto err_disable_vco; 1530 } 1531 1532 spi_set_drvdata(spi, lmk); 1533 1534 return 0; 1535 1536 err_disable_vco: 1537 clk_disable_unprepare(lmk->vco.clk); 1538 1539 err_disable_oscin: 1540 clk_disable_unprepare(lmk->oscin); 1541 1542 return ret; 1543 } 1544 1545 static void lmk04832_remove(struct spi_device *spi) 1546 { 1547 struct lmk04832 *lmk = spi_get_drvdata(spi); 1548 1549 clk_disable_unprepare(lmk->oscin); 1550 } 1551 1552 static const struct spi_device_id lmk04832_id[] = { 1553 { "lmk04832", LMK04832 }, 1554 {} 1555 }; 1556 MODULE_DEVICE_TABLE(spi, lmk04832_id); 1557 1558 static const struct of_device_id lmk04832_of_id[] = { 1559 { .compatible = "ti,lmk04832" }, 1560 {} 1561 }; 1562 MODULE_DEVICE_TABLE(of, lmk04832_of_id); 1563 1564 static struct spi_driver lmk04832_driver = { 1565 .driver = { 1566 .name = "lmk04832", 1567 .of_match_table = lmk04832_of_id, 1568 }, 1569 .probe = lmk04832_probe, 1570 .remove = lmk04832_remove, 1571 .id_table = lmk04832_id, 1572 }; 1573 module_spi_driver(lmk04832_driver); 1574 1575 MODULE_AUTHOR("Liam Beguin <lvb@xiphos.com>"); 1576 MODULE_DESCRIPTION("Texas Instruments LMK04832"); 1577 MODULE_LICENSE("GPL v2"); 1578