xref: /linux/drivers/clk/clk-highbank.c (revision e3966940559d52aa1800a008dcfeec218dd31f88) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright 2011-2012 Calxeda, Inc.
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/slab.h>
8 #include <linux/err.h>
9 #include <linux/clk-provider.h>
10 #include <linux/io.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 
14 #define HB_PLL_LOCK_500		0x20000000
15 #define HB_PLL_LOCK		0x10000000
16 #define HB_PLL_DIVF_SHIFT	20
17 #define HB_PLL_DIVF_MASK	0x0ff00000
18 #define HB_PLL_DIVQ_SHIFT	16
19 #define HB_PLL_DIVQ_MASK	0x00070000
20 #define HB_PLL_DIVR_SHIFT	8
21 #define HB_PLL_DIVR_MASK	0x00001f00
22 #define HB_PLL_RANGE_SHIFT	4
23 #define HB_PLL_RANGE_MASK	0x00000070
24 #define HB_PLL_BYPASS		0x00000008
25 #define HB_PLL_RESET		0x00000004
26 #define HB_PLL_EXT_BYPASS	0x00000002
27 #define HB_PLL_EXT_ENA		0x00000001
28 
29 #define HB_PLL_VCO_MIN_FREQ	2133000000
30 #define HB_PLL_MAX_FREQ		HB_PLL_VCO_MIN_FREQ
31 #define HB_PLL_MIN_FREQ		(HB_PLL_VCO_MIN_FREQ / 64)
32 
33 #define HB_A9_BCLK_DIV_MASK	0x00000006
34 #define HB_A9_BCLK_DIV_SHIFT	1
35 #define HB_A9_PCLK_DIV		0x00000001
36 
37 struct hb_clk {
38         struct clk_hw	hw;
39 	void __iomem	*reg;
40 };
41 #define to_hb_clk(p) container_of(p, struct hb_clk, hw)
42 
43 static int clk_pll_prepare(struct clk_hw *hwclk)
44 	{
45 	struct hb_clk *hbclk = to_hb_clk(hwclk);
46 	u32 reg;
47 
48 	reg = readl(hbclk->reg);
49 	reg &= ~HB_PLL_RESET;
50 	writel(reg, hbclk->reg);
51 
52 	while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
53 		;
54 	while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
55 		;
56 
57 	return 0;
58 }
59 
60 static void clk_pll_unprepare(struct clk_hw *hwclk)
61 {
62 	struct hb_clk *hbclk = to_hb_clk(hwclk);
63 	u32 reg;
64 
65 	reg = readl(hbclk->reg);
66 	reg |= HB_PLL_RESET;
67 	writel(reg, hbclk->reg);
68 }
69 
70 static int clk_pll_enable(struct clk_hw *hwclk)
71 {
72 	struct hb_clk *hbclk = to_hb_clk(hwclk);
73 	u32 reg;
74 
75 	reg = readl(hbclk->reg);
76 	reg |= HB_PLL_EXT_ENA;
77 	writel(reg, hbclk->reg);
78 
79 	return 0;
80 }
81 
82 static void clk_pll_disable(struct clk_hw *hwclk)
83 {
84 	struct hb_clk *hbclk = to_hb_clk(hwclk);
85 	u32 reg;
86 
87 	reg = readl(hbclk->reg);
88 	reg &= ~HB_PLL_EXT_ENA;
89 	writel(reg, hbclk->reg);
90 }
91 
92 static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
93 					 unsigned long parent_rate)
94 {
95 	struct hb_clk *hbclk = to_hb_clk(hwclk);
96 	unsigned long divf, divq, vco_freq, reg;
97 
98 	reg = readl(hbclk->reg);
99 	if (reg & HB_PLL_EXT_BYPASS)
100 		return parent_rate;
101 
102 	divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
103 	divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
104 	vco_freq = parent_rate * (divf + 1);
105 
106 	return vco_freq / (1 << divq);
107 }
108 
109 static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
110 			u32 *pdivq, u32 *pdivf)
111 {
112 	u32 divq, divf;
113 	unsigned long vco_freq;
114 
115 	if (rate < HB_PLL_MIN_FREQ)
116 		rate = HB_PLL_MIN_FREQ;
117 	if (rate > HB_PLL_MAX_FREQ)
118 		rate = HB_PLL_MAX_FREQ;
119 
120 	for (divq = 1; divq <= 6; divq++) {
121 		if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
122 			break;
123 	}
124 
125 	vco_freq = rate * (1 << divq);
126 	divf = (vco_freq + (ref_freq / 2)) / ref_freq;
127 	divf--;
128 
129 	*pdivq = divq;
130 	*pdivf = divf;
131 }
132 
133 static int clk_pll_determine_rate(struct clk_hw *hw,
134 				  struct clk_rate_request *req)
135 {
136 	u32 divq, divf;
137 	unsigned long ref_freq = req->best_parent_rate;
138 
139 	clk_pll_calc(req->rate, ref_freq, &divq, &divf);
140 
141 	req->rate = (ref_freq * (divf + 1)) / (1 << divq);
142 
143 	return 0;
144 }
145 
146 static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
147 			    unsigned long parent_rate)
148 {
149 	struct hb_clk *hbclk = to_hb_clk(hwclk);
150 	u32 divq, divf;
151 	u32 reg;
152 
153 	clk_pll_calc(rate, parent_rate, &divq, &divf);
154 
155 	reg = readl(hbclk->reg);
156 	if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
157 		/* Need to re-lock PLL, so put it into bypass mode */
158 		reg |= HB_PLL_EXT_BYPASS;
159 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
160 
161 		writel(reg | HB_PLL_RESET, hbclk->reg);
162 		reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
163 		reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
164 		writel(reg | HB_PLL_RESET, hbclk->reg);
165 		writel(reg, hbclk->reg);
166 
167 		while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
168 			;
169 		while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
170 			;
171 		reg |= HB_PLL_EXT_ENA;
172 		reg &= ~HB_PLL_EXT_BYPASS;
173 	} else {
174 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
175 		reg &= ~HB_PLL_DIVQ_MASK;
176 		reg |= divq << HB_PLL_DIVQ_SHIFT;
177 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
178 	}
179 	writel(reg, hbclk->reg);
180 
181 	return 0;
182 }
183 
184 static const struct clk_ops clk_pll_ops = {
185 	.prepare = clk_pll_prepare,
186 	.unprepare = clk_pll_unprepare,
187 	.enable = clk_pll_enable,
188 	.disable = clk_pll_disable,
189 	.recalc_rate = clk_pll_recalc_rate,
190 	.determine_rate = clk_pll_determine_rate,
191 	.set_rate = clk_pll_set_rate,
192 };
193 
194 static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *hwclk,
195 						   unsigned long parent_rate)
196 {
197 	struct hb_clk *hbclk = to_hb_clk(hwclk);
198 	u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;
199 	return parent_rate / div;
200 }
201 
202 static const struct clk_ops a9periphclk_ops = {
203 	.recalc_rate = clk_cpu_periphclk_recalc_rate,
204 };
205 
206 static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *hwclk,
207 						unsigned long parent_rate)
208 {
209 	struct hb_clk *hbclk = to_hb_clk(hwclk);
210 	u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;
211 
212 	return parent_rate / (div + 2);
213 }
214 
215 static const struct clk_ops a9bclk_ops = {
216 	.recalc_rate = clk_cpu_a9bclk_recalc_rate,
217 };
218 
219 static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
220 					     unsigned long parent_rate)
221 {
222 	struct hb_clk *hbclk = to_hb_clk(hwclk);
223 	u32 div;
224 
225 	div = readl(hbclk->reg) & 0x1f;
226 	div++;
227 	div *= 2;
228 
229 	return parent_rate / div;
230 }
231 
232 static int clk_periclk_determine_rate(struct clk_hw *hw,
233 				      struct clk_rate_request *req)
234 {
235 	u32 div;
236 
237 	div = req->best_parent_rate / req->rate;
238 	div++;
239 	div &= ~0x1;
240 
241 	req->rate = req->best_parent_rate / div;
242 
243 	return 0;
244 }
245 
246 static int clk_periclk_set_rate(struct clk_hw *hwclk, unsigned long rate,
247 				unsigned long parent_rate)
248 {
249 	struct hb_clk *hbclk = to_hb_clk(hwclk);
250 	u32 div;
251 
252 	div = parent_rate / rate;
253 	if (div & 0x1)
254 		return -EINVAL;
255 
256 	writel(div >> 1, hbclk->reg);
257 	return 0;
258 }
259 
260 static const struct clk_ops periclk_ops = {
261 	.recalc_rate = clk_periclk_recalc_rate,
262 	.determine_rate = clk_periclk_determine_rate,
263 	.set_rate = clk_periclk_set_rate,
264 };
265 
266 static void __init hb_clk_init(struct device_node *node, const struct clk_ops *ops, unsigned long clkflags)
267 {
268 	u32 reg;
269 	struct hb_clk *hb_clk;
270 	const char *clk_name = node->name;
271 	const char *parent_name;
272 	struct clk_init_data init;
273 	struct device_node *srnp;
274 	int rc;
275 
276 	rc = of_property_read_u32(node, "reg", &reg);
277 	if (WARN_ON(rc))
278 		return;
279 
280 	hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
281 	if (WARN_ON(!hb_clk))
282 		return;
283 
284 	/* Map system registers */
285 	srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
286 	hb_clk->reg = of_iomap(srnp, 0);
287 	of_node_put(srnp);
288 	BUG_ON(!hb_clk->reg);
289 	hb_clk->reg += reg;
290 
291 	of_property_read_string(node, "clock-output-names", &clk_name);
292 
293 	init.name = clk_name;
294 	init.ops = ops;
295 	init.flags = clkflags;
296 	parent_name = of_clk_get_parent_name(node, 0);
297 	init.parent_names = &parent_name;
298 	init.num_parents = 1;
299 
300 	hb_clk->hw.init = &init;
301 
302 	rc = clk_hw_register(NULL, &hb_clk->hw);
303 	if (WARN_ON(rc)) {
304 		kfree(hb_clk);
305 		return;
306 	}
307 	of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw);
308 }
309 
310 static void __init hb_pll_init(struct device_node *node)
311 {
312 	hb_clk_init(node, &clk_pll_ops, 0);
313 }
314 CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init);
315 
316 static void __init hb_a9periph_init(struct device_node *node)
317 {
318 	hb_clk_init(node, &a9periphclk_ops, 0);
319 }
320 CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init);
321 
322 static void __init hb_a9bus_init(struct device_node *node)
323 {
324 	hb_clk_init(node, &a9bclk_ops, CLK_IS_CRITICAL);
325 }
326 CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init);
327 
328 static void __init hb_emmc_init(struct device_node *node)
329 {
330 	hb_clk_init(node, &periclk_ops, 0);
331 }
332 CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);
333