xref: /linux/drivers/clk/clk-highbank.c (revision 4b132aacb0768ac1e652cf517097ea6f237214b9) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright 2011-2012 Calxeda, Inc.
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/slab.h>
8 #include <linux/err.h>
9 #include <linux/clk-provider.h>
10 #include <linux/io.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 
14 #define HB_PLL_LOCK_500		0x20000000
15 #define HB_PLL_LOCK		0x10000000
16 #define HB_PLL_DIVF_SHIFT	20
17 #define HB_PLL_DIVF_MASK	0x0ff00000
18 #define HB_PLL_DIVQ_SHIFT	16
19 #define HB_PLL_DIVQ_MASK	0x00070000
20 #define HB_PLL_DIVR_SHIFT	8
21 #define HB_PLL_DIVR_MASK	0x00001f00
22 #define HB_PLL_RANGE_SHIFT	4
23 #define HB_PLL_RANGE_MASK	0x00000070
24 #define HB_PLL_BYPASS		0x00000008
25 #define HB_PLL_RESET		0x00000004
26 #define HB_PLL_EXT_BYPASS	0x00000002
27 #define HB_PLL_EXT_ENA		0x00000001
28 
29 #define HB_PLL_VCO_MIN_FREQ	2133000000
30 #define HB_PLL_MAX_FREQ		HB_PLL_VCO_MIN_FREQ
31 #define HB_PLL_MIN_FREQ		(HB_PLL_VCO_MIN_FREQ / 64)
32 
33 #define HB_A9_BCLK_DIV_MASK	0x00000006
34 #define HB_A9_BCLK_DIV_SHIFT	1
35 #define HB_A9_PCLK_DIV		0x00000001
36 
37 struct hb_clk {
38         struct clk_hw	hw;
39 	void __iomem	*reg;
40 };
41 #define to_hb_clk(p) container_of(p, struct hb_clk, hw)
42 
43 static int clk_pll_prepare(struct clk_hw *hwclk)
44 	{
45 	struct hb_clk *hbclk = to_hb_clk(hwclk);
46 	u32 reg;
47 
48 	reg = readl(hbclk->reg);
49 	reg &= ~HB_PLL_RESET;
50 	writel(reg, hbclk->reg);
51 
52 	while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
53 		;
54 	while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
55 		;
56 
57 	return 0;
58 }
59 
60 static void clk_pll_unprepare(struct clk_hw *hwclk)
61 {
62 	struct hb_clk *hbclk = to_hb_clk(hwclk);
63 	u32 reg;
64 
65 	reg = readl(hbclk->reg);
66 	reg |= HB_PLL_RESET;
67 	writel(reg, hbclk->reg);
68 }
69 
70 static int clk_pll_enable(struct clk_hw *hwclk)
71 {
72 	struct hb_clk *hbclk = to_hb_clk(hwclk);
73 	u32 reg;
74 
75 	reg = readl(hbclk->reg);
76 	reg |= HB_PLL_EXT_ENA;
77 	writel(reg, hbclk->reg);
78 
79 	return 0;
80 }
81 
82 static void clk_pll_disable(struct clk_hw *hwclk)
83 {
84 	struct hb_clk *hbclk = to_hb_clk(hwclk);
85 	u32 reg;
86 
87 	reg = readl(hbclk->reg);
88 	reg &= ~HB_PLL_EXT_ENA;
89 	writel(reg, hbclk->reg);
90 }
91 
92 static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
93 					 unsigned long parent_rate)
94 {
95 	struct hb_clk *hbclk = to_hb_clk(hwclk);
96 	unsigned long divf, divq, vco_freq, reg;
97 
98 	reg = readl(hbclk->reg);
99 	if (reg & HB_PLL_EXT_BYPASS)
100 		return parent_rate;
101 
102 	divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
103 	divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
104 	vco_freq = parent_rate * (divf + 1);
105 
106 	return vco_freq / (1 << divq);
107 }
108 
109 static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
110 			u32 *pdivq, u32 *pdivf)
111 {
112 	u32 divq, divf;
113 	unsigned long vco_freq;
114 
115 	if (rate < HB_PLL_MIN_FREQ)
116 		rate = HB_PLL_MIN_FREQ;
117 	if (rate > HB_PLL_MAX_FREQ)
118 		rate = HB_PLL_MAX_FREQ;
119 
120 	for (divq = 1; divq <= 6; divq++) {
121 		if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
122 			break;
123 	}
124 
125 	vco_freq = rate * (1 << divq);
126 	divf = (vco_freq + (ref_freq / 2)) / ref_freq;
127 	divf--;
128 
129 	*pdivq = divq;
130 	*pdivf = divf;
131 }
132 
133 static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate,
134 			       unsigned long *parent_rate)
135 {
136 	u32 divq, divf;
137 	unsigned long ref_freq = *parent_rate;
138 
139 	clk_pll_calc(rate, ref_freq, &divq, &divf);
140 
141 	return (ref_freq * (divf + 1)) / (1 << divq);
142 }
143 
144 static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
145 			    unsigned long parent_rate)
146 {
147 	struct hb_clk *hbclk = to_hb_clk(hwclk);
148 	u32 divq, divf;
149 	u32 reg;
150 
151 	clk_pll_calc(rate, parent_rate, &divq, &divf);
152 
153 	reg = readl(hbclk->reg);
154 	if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
155 		/* Need to re-lock PLL, so put it into bypass mode */
156 		reg |= HB_PLL_EXT_BYPASS;
157 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
158 
159 		writel(reg | HB_PLL_RESET, hbclk->reg);
160 		reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
161 		reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
162 		writel(reg | HB_PLL_RESET, hbclk->reg);
163 		writel(reg, hbclk->reg);
164 
165 		while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
166 			;
167 		while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
168 			;
169 		reg |= HB_PLL_EXT_ENA;
170 		reg &= ~HB_PLL_EXT_BYPASS;
171 	} else {
172 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
173 		reg &= ~HB_PLL_DIVQ_MASK;
174 		reg |= divq << HB_PLL_DIVQ_SHIFT;
175 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
176 	}
177 	writel(reg, hbclk->reg);
178 
179 	return 0;
180 }
181 
182 static const struct clk_ops clk_pll_ops = {
183 	.prepare = clk_pll_prepare,
184 	.unprepare = clk_pll_unprepare,
185 	.enable = clk_pll_enable,
186 	.disable = clk_pll_disable,
187 	.recalc_rate = clk_pll_recalc_rate,
188 	.round_rate = clk_pll_round_rate,
189 	.set_rate = clk_pll_set_rate,
190 };
191 
192 static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *hwclk,
193 						   unsigned long parent_rate)
194 {
195 	struct hb_clk *hbclk = to_hb_clk(hwclk);
196 	u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;
197 	return parent_rate / div;
198 }
199 
200 static const struct clk_ops a9periphclk_ops = {
201 	.recalc_rate = clk_cpu_periphclk_recalc_rate,
202 };
203 
204 static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *hwclk,
205 						unsigned long parent_rate)
206 {
207 	struct hb_clk *hbclk = to_hb_clk(hwclk);
208 	u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;
209 
210 	return parent_rate / (div + 2);
211 }
212 
213 static const struct clk_ops a9bclk_ops = {
214 	.recalc_rate = clk_cpu_a9bclk_recalc_rate,
215 };
216 
217 static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
218 					     unsigned long parent_rate)
219 {
220 	struct hb_clk *hbclk = to_hb_clk(hwclk);
221 	u32 div;
222 
223 	div = readl(hbclk->reg) & 0x1f;
224 	div++;
225 	div *= 2;
226 
227 	return parent_rate / div;
228 }
229 
230 static long clk_periclk_round_rate(struct clk_hw *hwclk, unsigned long rate,
231 				   unsigned long *parent_rate)
232 {
233 	u32 div;
234 
235 	div = *parent_rate / rate;
236 	div++;
237 	div &= ~0x1;
238 
239 	return *parent_rate / div;
240 }
241 
242 static int clk_periclk_set_rate(struct clk_hw *hwclk, unsigned long rate,
243 				unsigned long parent_rate)
244 {
245 	struct hb_clk *hbclk = to_hb_clk(hwclk);
246 	u32 div;
247 
248 	div = parent_rate / rate;
249 	if (div & 0x1)
250 		return -EINVAL;
251 
252 	writel(div >> 1, hbclk->reg);
253 	return 0;
254 }
255 
256 static const struct clk_ops periclk_ops = {
257 	.recalc_rate = clk_periclk_recalc_rate,
258 	.round_rate = clk_periclk_round_rate,
259 	.set_rate = clk_periclk_set_rate,
260 };
261 
262 static void __init hb_clk_init(struct device_node *node, const struct clk_ops *ops, unsigned long clkflags)
263 {
264 	u32 reg;
265 	struct hb_clk *hb_clk;
266 	const char *clk_name = node->name;
267 	const char *parent_name;
268 	struct clk_init_data init;
269 	struct device_node *srnp;
270 	int rc;
271 
272 	rc = of_property_read_u32(node, "reg", &reg);
273 	if (WARN_ON(rc))
274 		return;
275 
276 	hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
277 	if (WARN_ON(!hb_clk))
278 		return;
279 
280 	/* Map system registers */
281 	srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
282 	hb_clk->reg = of_iomap(srnp, 0);
283 	of_node_put(srnp);
284 	BUG_ON(!hb_clk->reg);
285 	hb_clk->reg += reg;
286 
287 	of_property_read_string(node, "clock-output-names", &clk_name);
288 
289 	init.name = clk_name;
290 	init.ops = ops;
291 	init.flags = clkflags;
292 	parent_name = of_clk_get_parent_name(node, 0);
293 	init.parent_names = &parent_name;
294 	init.num_parents = 1;
295 
296 	hb_clk->hw.init = &init;
297 
298 	rc = clk_hw_register(NULL, &hb_clk->hw);
299 	if (WARN_ON(rc)) {
300 		kfree(hb_clk);
301 		return;
302 	}
303 	of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw);
304 }
305 
306 static void __init hb_pll_init(struct device_node *node)
307 {
308 	hb_clk_init(node, &clk_pll_ops, 0);
309 }
310 CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init);
311 
312 static void __init hb_a9periph_init(struct device_node *node)
313 {
314 	hb_clk_init(node, &a9periphclk_ops, 0);
315 }
316 CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init);
317 
318 static void __init hb_a9bus_init(struct device_node *node)
319 {
320 	hb_clk_init(node, &a9bclk_ops, CLK_IS_CRITICAL);
321 }
322 CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init);
323 
324 static void __init hb_emmc_init(struct device_node *node)
325 {
326 	hb_clk_init(node, &periclk_ops, 0);
327 }
328 CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);
329