1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2013 - 2014 Texas Instruments Incorporated - http://www.ti.com 4 * 5 * Authors: 6 * Jyri Sarha <jsarha@ti.com> 7 * Sergej Sawazki <ce3a@gmx.de> 8 * 9 * Gpio controlled clock implementation 10 */ 11 12 #include <linux/clk-provider.h> 13 #include <linux/export.h> 14 #include <linux/slab.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/err.h> 17 #include <linux/device.h> 18 #include <linux/platform_device.h> 19 #include <linux/of_device.h> 20 21 /** 22 * DOC: basic gpio gated clock which can be enabled and disabled 23 * with gpio output 24 * Traits of this clock: 25 * prepare - clk_(un)prepare only ensures parent is (un)prepared 26 * enable - clk_enable and clk_disable are functional & control gpio 27 * rate - inherits rate from parent. No clk_set_rate support 28 * parent - fixed parent. No clk_set_parent support 29 */ 30 31 static int clk_gpio_gate_enable(struct clk_hw *hw) 32 { 33 struct clk_gpio *clk = to_clk_gpio(hw); 34 35 gpiod_set_value(clk->gpiod, 1); 36 37 return 0; 38 } 39 40 static void clk_gpio_gate_disable(struct clk_hw *hw) 41 { 42 struct clk_gpio *clk = to_clk_gpio(hw); 43 44 gpiod_set_value(clk->gpiod, 0); 45 } 46 47 static int clk_gpio_gate_is_enabled(struct clk_hw *hw) 48 { 49 struct clk_gpio *clk = to_clk_gpio(hw); 50 51 return gpiod_get_value(clk->gpiod); 52 } 53 54 const struct clk_ops clk_gpio_gate_ops = { 55 .enable = clk_gpio_gate_enable, 56 .disable = clk_gpio_gate_disable, 57 .is_enabled = clk_gpio_gate_is_enabled, 58 }; 59 EXPORT_SYMBOL_GPL(clk_gpio_gate_ops); 60 61 /** 62 * DOC: basic clock multiplexer which can be controlled with a gpio output 63 * Traits of this clock: 64 * prepare - clk_prepare only ensures that parents are prepared 65 * rate - rate is only affected by parent switching. No clk_set_rate support 66 * parent - parent is adjustable through clk_set_parent 67 */ 68 69 static u8 clk_gpio_mux_get_parent(struct clk_hw *hw) 70 { 71 struct clk_gpio *clk = to_clk_gpio(hw); 72 73 return gpiod_get_value_cansleep(clk->gpiod); 74 } 75 76 static int clk_gpio_mux_set_parent(struct clk_hw *hw, u8 index) 77 { 78 struct clk_gpio *clk = to_clk_gpio(hw); 79 80 gpiod_set_value_cansleep(clk->gpiod, index); 81 82 return 0; 83 } 84 85 const struct clk_ops clk_gpio_mux_ops = { 86 .get_parent = clk_gpio_mux_get_parent, 87 .set_parent = clk_gpio_mux_set_parent, 88 .determine_rate = __clk_mux_determine_rate, 89 }; 90 EXPORT_SYMBOL_GPL(clk_gpio_mux_ops); 91 92 static struct clk_hw *clk_register_gpio(struct device *dev, const char *name, 93 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, 94 unsigned long flags, const struct clk_ops *clk_gpio_ops) 95 { 96 struct clk_gpio *clk_gpio; 97 struct clk_hw *hw; 98 struct clk_init_data init = {}; 99 int err; 100 101 if (dev) 102 clk_gpio = devm_kzalloc(dev, sizeof(*clk_gpio), GFP_KERNEL); 103 else 104 clk_gpio = kzalloc(sizeof(*clk_gpio), GFP_KERNEL); 105 106 if (!clk_gpio) 107 return ERR_PTR(-ENOMEM); 108 109 init.name = name; 110 init.ops = clk_gpio_ops; 111 init.flags = flags | CLK_IS_BASIC; 112 init.parent_names = parent_names; 113 init.num_parents = num_parents; 114 115 clk_gpio->gpiod = gpiod; 116 clk_gpio->hw.init = &init; 117 118 hw = &clk_gpio->hw; 119 if (dev) 120 err = devm_clk_hw_register(dev, hw); 121 else 122 err = clk_hw_register(NULL, hw); 123 124 if (!err) 125 return hw; 126 127 if (!dev) { 128 kfree(clk_gpio); 129 } 130 131 return ERR_PTR(err); 132 } 133 134 /** 135 * clk_hw_register_gpio_gate - register a gpio clock gate with the clock 136 * framework 137 * @dev: device that is registering this clock 138 * @name: name of this clock 139 * @parent_name: name of this clock's parent 140 * @gpiod: gpio descriptor to gate this clock 141 * @flags: clock flags 142 */ 143 struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, 144 const char *parent_name, struct gpio_desc *gpiod, 145 unsigned long flags) 146 { 147 return clk_register_gpio(dev, name, 148 (parent_name ? &parent_name : NULL), 149 (parent_name ? 1 : 0), gpiod, flags, 150 &clk_gpio_gate_ops); 151 } 152 EXPORT_SYMBOL_GPL(clk_hw_register_gpio_gate); 153 154 struct clk *clk_register_gpio_gate(struct device *dev, const char *name, 155 const char *parent_name, struct gpio_desc *gpiod, 156 unsigned long flags) 157 { 158 struct clk_hw *hw; 159 160 hw = clk_hw_register_gpio_gate(dev, name, parent_name, gpiod, flags); 161 if (IS_ERR(hw)) 162 return ERR_CAST(hw); 163 return hw->clk; 164 } 165 EXPORT_SYMBOL_GPL(clk_register_gpio_gate); 166 167 /** 168 * clk_hw_register_gpio_mux - register a gpio clock mux with the clock framework 169 * @dev: device that is registering this clock 170 * @name: name of this clock 171 * @parent_names: names of this clock's parents 172 * @num_parents: number of parents listed in @parent_names 173 * @gpiod: gpio descriptor to gate this clock 174 * @flags: clock flags 175 */ 176 struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, 177 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, 178 unsigned long flags) 179 { 180 if (num_parents != 2) { 181 pr_err("mux-clock %s must have 2 parents\n", name); 182 return ERR_PTR(-EINVAL); 183 } 184 185 return clk_register_gpio(dev, name, parent_names, num_parents, 186 gpiod, flags, &clk_gpio_mux_ops); 187 } 188 EXPORT_SYMBOL_GPL(clk_hw_register_gpio_mux); 189 190 struct clk *clk_register_gpio_mux(struct device *dev, const char *name, 191 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, 192 unsigned long flags) 193 { 194 struct clk_hw *hw; 195 196 hw = clk_hw_register_gpio_mux(dev, name, parent_names, num_parents, 197 gpiod, flags); 198 if (IS_ERR(hw)) 199 return ERR_CAST(hw); 200 return hw->clk; 201 } 202 EXPORT_SYMBOL_GPL(clk_register_gpio_mux); 203 204 static int gpio_clk_driver_probe(struct platform_device *pdev) 205 { 206 struct device_node *node = pdev->dev.of_node; 207 const char **parent_names, *gpio_name; 208 unsigned int num_parents; 209 struct gpio_desc *gpiod; 210 struct clk *clk; 211 bool is_mux; 212 int ret; 213 214 num_parents = of_clk_get_parent_count(node); 215 if (num_parents) { 216 parent_names = devm_kcalloc(&pdev->dev, num_parents, 217 sizeof(char *), GFP_KERNEL); 218 if (!parent_names) 219 return -ENOMEM; 220 221 of_clk_parent_fill(node, parent_names, num_parents); 222 } else { 223 parent_names = NULL; 224 } 225 226 is_mux = of_device_is_compatible(node, "gpio-mux-clock"); 227 228 gpio_name = is_mux ? "select" : "enable"; 229 gpiod = devm_gpiod_get(&pdev->dev, gpio_name, GPIOD_OUT_LOW); 230 if (IS_ERR(gpiod)) { 231 ret = PTR_ERR(gpiod); 232 if (ret == -EPROBE_DEFER) 233 pr_debug("%pOFn: %s: GPIOs not yet available, retry later\n", 234 node, __func__); 235 else 236 pr_err("%pOFn: %s: Can't get '%s' named GPIO property\n", 237 node, __func__, 238 gpio_name); 239 return ret; 240 } 241 242 if (is_mux) 243 clk = clk_register_gpio_mux(&pdev->dev, node->name, 244 parent_names, num_parents, gpiod, 0); 245 else 246 clk = clk_register_gpio_gate(&pdev->dev, node->name, 247 parent_names ? parent_names[0] : NULL, gpiod, 248 0); 249 if (IS_ERR(clk)) 250 return PTR_ERR(clk); 251 252 return of_clk_add_provider(node, of_clk_src_simple_get, clk); 253 } 254 255 static const struct of_device_id gpio_clk_match_table[] = { 256 { .compatible = "gpio-mux-clock" }, 257 { .compatible = "gpio-gate-clock" }, 258 { } 259 }; 260 261 static struct platform_driver gpio_clk_driver = { 262 .probe = gpio_clk_driver_probe, 263 .driver = { 264 .name = "gpio-clk", 265 .of_match_table = gpio_clk_match_table, 266 }, 267 }; 268 builtin_platform_driver(gpio_clk_driver); 269