1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/delay.h> 4 #include <linux/clk-provider.h> 5 #include <linux/io.h> 6 #include <linux/mfd/syscon.h> 7 #include <linux/platform_device.h> 8 #include <linux/property.h> 9 #include <linux/regmap.h> 10 #include <linux/reset-controller.h> 11 #include <dt-bindings/clock/en7523-clk.h> 12 #include <dt-bindings/reset/airoha,en7523-reset.h> 13 #include <dt-bindings/reset/airoha,en7581-reset.h> 14 15 #define RST_NR_PER_BANK 32 16 17 #define REG_PCI_CONTROL 0x88 18 #define REG_PCI_CONTROL_PERSTOUT BIT(29) 19 #define REG_PCI_CONTROL_PERSTOUT1 BIT(26) 20 #define REG_PCI_CONTROL_REFCLK_EN0 BIT(23) 21 #define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) 22 #define REG_PCI_CONTROL_PERSTOUT2 BIT(16) 23 #define REG_GSW_CLK_DIV_SEL 0x1b4 24 #define REG_EMI_CLK_DIV_SEL 0x1b8 25 #define REG_BUS_CLK_DIV_SEL 0x1bc 26 #define REG_SPI_CLK_DIV_SEL 0x1c4 27 #define REG_SPI_CLK_FREQ_SEL 0x1c8 28 #define REG_NPU_CLK_DIV_SEL 0x1fc 29 #define REG_CRYPTO_CLKSRC 0x200 30 #define REG_RESET_CONTROL2 0x830 31 #define REG_RESET2_CONTROL_PCIE2 BIT(27) 32 #define REG_RESET_CONTROL1 0x834 33 #define REG_RESET_CONTROL_PCIEHB BIT(29) 34 #define REG_RESET_CONTROL_PCIE1 BIT(27) 35 #define REG_RESET_CONTROL_PCIE2 BIT(26) 36 /* EN7581 */ 37 #define REG_NP_SCU_PCIC 0x88 38 #define REG_NP_SCU_SSTR 0x9c 39 #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) 40 #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) 41 #define REG_CRYPTO_CLKSRC2 0x20c 42 43 #define REG_RST_CTRL2 0x830 44 #define REG_RST_CTRL1 0x834 45 46 struct en_clk_desc { 47 int id; 48 const char *name; 49 u32 base_reg; 50 u8 base_bits; 51 u8 base_shift; 52 union { 53 const unsigned int *base_values; 54 unsigned int base_value; 55 }; 56 size_t n_base_values; 57 58 u16 div_reg; 59 u8 div_bits; 60 u8 div_shift; 61 u16 div_val0; 62 u8 div_step; 63 u8 div_offset; 64 }; 65 66 struct en_clk_gate { 67 void __iomem *base; 68 struct clk_hw hw; 69 }; 70 71 struct en_rst_data { 72 const u16 *bank_ofs; 73 const u16 *idx_map; 74 void __iomem *base; 75 struct reset_controller_dev rcdev; 76 }; 77 78 struct en_clk_soc_data { 79 u32 num_clocks; 80 const struct clk_ops pcie_ops; 81 int (*hw_init)(struct platform_device *pdev, 82 struct clk_hw_onecell_data *clk_data); 83 }; 84 85 static const u32 gsw_base[] = { 400000000, 500000000 }; 86 static const u32 emi_base[] = { 333000000, 400000000 }; 87 static const u32 bus_base[] = { 500000000, 540000000 }; 88 static const u32 slic_base[] = { 100000000, 3125000 }; 89 static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; 90 /* EN7581 */ 91 static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 }; 92 static const u32 bus7581_base[] = { 600000000, 540000000 }; 93 static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 }; 94 static const u32 crypto_base[] = { 540000000, 480000000 }; 95 static const u32 emmc7581_base[] = { 200000000, 150000000 }; 96 97 static const struct en_clk_desc en7523_base_clks[] = { 98 { 99 .id = EN7523_CLK_GSW, 100 .name = "gsw", 101 102 .base_reg = REG_GSW_CLK_DIV_SEL, 103 .base_bits = 1, 104 .base_shift = 8, 105 .base_values = gsw_base, 106 .n_base_values = ARRAY_SIZE(gsw_base), 107 108 .div_bits = 3, 109 .div_shift = 0, 110 .div_step = 1, 111 .div_offset = 1, 112 }, { 113 .id = EN7523_CLK_EMI, 114 .name = "emi", 115 116 .base_reg = REG_EMI_CLK_DIV_SEL, 117 .base_bits = 1, 118 .base_shift = 8, 119 .base_values = emi_base, 120 .n_base_values = ARRAY_SIZE(emi_base), 121 122 .div_bits = 3, 123 .div_shift = 0, 124 .div_step = 1, 125 .div_offset = 1, 126 }, { 127 .id = EN7523_CLK_BUS, 128 .name = "bus", 129 130 .base_reg = REG_BUS_CLK_DIV_SEL, 131 .base_bits = 1, 132 .base_shift = 8, 133 .base_values = bus_base, 134 .n_base_values = ARRAY_SIZE(bus_base), 135 136 .div_bits = 3, 137 .div_shift = 0, 138 .div_step = 1, 139 .div_offset = 1, 140 }, { 141 .id = EN7523_CLK_SLIC, 142 .name = "slic", 143 144 .base_reg = REG_SPI_CLK_FREQ_SEL, 145 .base_bits = 1, 146 .base_shift = 0, 147 .base_values = slic_base, 148 .n_base_values = ARRAY_SIZE(slic_base), 149 150 .div_reg = REG_SPI_CLK_DIV_SEL, 151 .div_bits = 5, 152 .div_shift = 24, 153 .div_val0 = 20, 154 .div_step = 2, 155 }, { 156 .id = EN7523_CLK_SPI, 157 .name = "spi", 158 159 .base_reg = REG_SPI_CLK_DIV_SEL, 160 161 .base_value = 400000000, 162 163 .div_bits = 5, 164 .div_shift = 8, 165 .div_val0 = 40, 166 .div_step = 2, 167 }, { 168 .id = EN7523_CLK_NPU, 169 .name = "npu", 170 171 .base_reg = REG_NPU_CLK_DIV_SEL, 172 .base_bits = 2, 173 .base_shift = 8, 174 .base_values = npu_base, 175 .n_base_values = ARRAY_SIZE(npu_base), 176 177 .div_bits = 3, 178 .div_shift = 0, 179 .div_step = 1, 180 .div_offset = 1, 181 }, { 182 .id = EN7523_CLK_CRYPTO, 183 .name = "crypto", 184 185 .base_reg = REG_CRYPTO_CLKSRC, 186 .base_bits = 1, 187 .base_shift = 0, 188 .base_values = emi_base, 189 .n_base_values = ARRAY_SIZE(emi_base), 190 } 191 }; 192 193 static const struct en_clk_desc en7581_base_clks[] = { 194 { 195 .id = EN7523_CLK_GSW, 196 .name = "gsw", 197 198 .base_reg = REG_GSW_CLK_DIV_SEL, 199 .base_bits = 1, 200 .base_shift = 8, 201 .base_values = gsw_base, 202 .n_base_values = ARRAY_SIZE(gsw_base), 203 204 .div_bits = 3, 205 .div_shift = 0, 206 .div_step = 1, 207 .div_offset = 1, 208 }, { 209 .id = EN7523_CLK_EMI, 210 .name = "emi", 211 212 .base_reg = REG_EMI_CLK_DIV_SEL, 213 .base_bits = 2, 214 .base_shift = 8, 215 .base_values = emi7581_base, 216 .n_base_values = ARRAY_SIZE(emi7581_base), 217 218 .div_bits = 3, 219 .div_shift = 0, 220 .div_step = 1, 221 .div_offset = 1, 222 }, { 223 .id = EN7523_CLK_BUS, 224 .name = "bus", 225 226 .base_reg = REG_BUS_CLK_DIV_SEL, 227 .base_bits = 1, 228 .base_shift = 8, 229 .base_values = bus7581_base, 230 .n_base_values = ARRAY_SIZE(bus7581_base), 231 232 .div_bits = 3, 233 .div_shift = 0, 234 .div_step = 1, 235 .div_offset = 1, 236 }, { 237 .id = EN7523_CLK_SLIC, 238 .name = "slic", 239 240 .base_reg = REG_SPI_CLK_FREQ_SEL, 241 .base_bits = 1, 242 .base_shift = 0, 243 .base_values = slic_base, 244 .n_base_values = ARRAY_SIZE(slic_base), 245 246 .div_reg = REG_SPI_CLK_DIV_SEL, 247 .div_bits = 5, 248 .div_shift = 24, 249 .div_val0 = 20, 250 .div_step = 2, 251 }, { 252 .id = EN7523_CLK_SPI, 253 .name = "spi", 254 255 .base_reg = REG_SPI_CLK_DIV_SEL, 256 257 .base_value = 400000000, 258 259 .div_bits = 5, 260 .div_shift = 8, 261 .div_val0 = 40, 262 .div_step = 2, 263 }, { 264 .id = EN7523_CLK_NPU, 265 .name = "npu", 266 267 .base_reg = REG_NPU_CLK_DIV_SEL, 268 .base_bits = 2, 269 .base_shift = 8, 270 .base_values = npu7581_base, 271 .n_base_values = ARRAY_SIZE(npu7581_base), 272 273 .div_bits = 3, 274 .div_shift = 0, 275 .div_step = 1, 276 .div_offset = 1, 277 }, { 278 .id = EN7523_CLK_CRYPTO, 279 .name = "crypto", 280 281 .base_reg = REG_CRYPTO_CLKSRC2, 282 .base_bits = 1, 283 .base_shift = 0, 284 .base_values = crypto_base, 285 .n_base_values = ARRAY_SIZE(crypto_base), 286 }, { 287 .id = EN7581_CLK_EMMC, 288 .name = "emmc", 289 290 .base_reg = REG_CRYPTO_CLKSRC2, 291 .base_bits = 1, 292 .base_shift = 12, 293 .base_values = emmc7581_base, 294 .n_base_values = ARRAY_SIZE(emmc7581_base), 295 } 296 }; 297 298 static const u16 en7581_rst_ofs[] = { 299 REG_RST_CTRL2, 300 REG_RST_CTRL1, 301 }; 302 303 static const u16 en7523_rst_map[] = { 304 /* RST_CTRL2 */ 305 [EN7523_XPON_PHY_RST] = 0, 306 [EN7523_XSI_MAC_RST] = 7, 307 [EN7523_XSI_PHY_RST] = 8, 308 [EN7523_NPU_RST] = 9, 309 [EN7523_I2S_RST] = 10, 310 [EN7523_TRNG_RST] = 11, 311 [EN7523_TRNG_MSTART_RST] = 12, 312 [EN7523_DUAL_HSI0_RST] = 13, 313 [EN7523_DUAL_HSI1_RST] = 14, 314 [EN7523_HSI_RST] = 15, 315 [EN7523_DUAL_HSI0_MAC_RST] = 16, 316 [EN7523_DUAL_HSI1_MAC_RST] = 17, 317 [EN7523_HSI_MAC_RST] = 18, 318 [EN7523_WDMA_RST] = 19, 319 [EN7523_WOE0_RST] = 20, 320 [EN7523_WOE1_RST] = 21, 321 [EN7523_HSDMA_RST] = 22, 322 [EN7523_I2C2RBUS_RST] = 23, 323 [EN7523_TDMA_RST] = 24, 324 /* RST_CTRL1 */ 325 [EN7523_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, 326 [EN7523_FE_PDMA_RST] = RST_NR_PER_BANK + 1, 327 [EN7523_FE_QDMA_RST] = RST_NR_PER_BANK + 2, 328 [EN7523_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, 329 [EN7523_CRYPTO_RST] = RST_NR_PER_BANK + 6, 330 [EN7523_TIMER_RST] = RST_NR_PER_BANK + 8, 331 [EN7523_PCM1_RST] = RST_NR_PER_BANK + 11, 332 [EN7523_UART_RST] = RST_NR_PER_BANK + 12, 333 [EN7523_GPIO_RST] = RST_NR_PER_BANK + 13, 334 [EN7523_GDMA_RST] = RST_NR_PER_BANK + 14, 335 [EN7523_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, 336 [EN7523_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, 337 [EN7523_SFC_RST] = RST_NR_PER_BANK + 18, 338 [EN7523_UART2_RST] = RST_NR_PER_BANK + 19, 339 [EN7523_GDMP_RST] = RST_NR_PER_BANK + 20, 340 [EN7523_FE_RST] = RST_NR_PER_BANK + 21, 341 [EN7523_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, 342 [EN7523_GSW_RST] = RST_NR_PER_BANK + 23, 343 [EN7523_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, 344 [EN7523_PCIE0_RST] = RST_NR_PER_BANK + 26, 345 [EN7523_PCIE1_RST] = RST_NR_PER_BANK + 27, 346 [EN7523_PCIE_HB_RST] = RST_NR_PER_BANK + 29, 347 [EN7523_XPON_MAC_RST] = RST_NR_PER_BANK + 31, 348 }; 349 350 static const u16 en7581_rst_map[] = { 351 /* RST_CTRL2 */ 352 [EN7581_XPON_PHY_RST] = 0, 353 [EN7581_CPU_TIMER2_RST] = 2, 354 [EN7581_HSUART_RST] = 3, 355 [EN7581_UART4_RST] = 4, 356 [EN7581_UART5_RST] = 5, 357 [EN7581_I2C2_RST] = 6, 358 [EN7581_XSI_MAC_RST] = 7, 359 [EN7581_XSI_PHY_RST] = 8, 360 [EN7581_NPU_RST] = 9, 361 [EN7581_I2S_RST] = 10, 362 [EN7581_TRNG_RST] = 11, 363 [EN7581_TRNG_MSTART_RST] = 12, 364 [EN7581_DUAL_HSI0_RST] = 13, 365 [EN7581_DUAL_HSI1_RST] = 14, 366 [EN7581_HSI_RST] = 15, 367 [EN7581_DUAL_HSI0_MAC_RST] = 16, 368 [EN7581_DUAL_HSI1_MAC_RST] = 17, 369 [EN7581_HSI_MAC_RST] = 18, 370 [EN7581_WDMA_RST] = 19, 371 [EN7581_WOE0_RST] = 20, 372 [EN7581_WOE1_RST] = 21, 373 [EN7581_HSDMA_RST] = 22, 374 [EN7581_TDMA_RST] = 24, 375 [EN7581_EMMC_RST] = 25, 376 [EN7581_SOE_RST] = 26, 377 [EN7581_PCIE2_RST] = 27, 378 [EN7581_XFP_MAC_RST] = 28, 379 [EN7581_USB_HOST_P1_RST] = 29, 380 [EN7581_USB_HOST_P1_U3_PHY_RST] = 30, 381 /* RST_CTRL1 */ 382 [EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, 383 [EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1, 384 [EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2, 385 [EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, 386 [EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6, 387 [EN7581_TIMER_RST] = RST_NR_PER_BANK + 8, 388 [EN7581_PCM1_RST] = RST_NR_PER_BANK + 11, 389 [EN7581_UART_RST] = RST_NR_PER_BANK + 12, 390 [EN7581_GPIO_RST] = RST_NR_PER_BANK + 13, 391 [EN7581_GDMA_RST] = RST_NR_PER_BANK + 14, 392 [EN7581_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, 393 [EN7581_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, 394 [EN7581_SFC_RST] = RST_NR_PER_BANK + 18, 395 [EN7581_UART2_RST] = RST_NR_PER_BANK + 19, 396 [EN7581_GDMP_RST] = RST_NR_PER_BANK + 20, 397 [EN7581_FE_RST] = RST_NR_PER_BANK + 21, 398 [EN7581_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, 399 [EN7581_GSW_RST] = RST_NR_PER_BANK + 23, 400 [EN7581_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, 401 [EN7581_PCIE0_RST] = RST_NR_PER_BANK + 26, 402 [EN7581_PCIE1_RST] = RST_NR_PER_BANK + 27, 403 [EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28, 404 [EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29, 405 [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31, 406 }; 407 408 static int en7581_reset_register(struct device *dev, void __iomem *base, 409 const u16 *rst_map, int nr_resets); 410 411 static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val) 412 { 413 if (!desc->base_bits) 414 return desc->base_value; 415 416 val >>= desc->base_shift; 417 val &= (1 << desc->base_bits) - 1; 418 419 if (val >= desc->n_base_values) 420 return 0; 421 422 return desc->base_values[val]; 423 } 424 425 static u32 en7523_get_div(const struct en_clk_desc *desc, u32 val) 426 { 427 if (!desc->div_bits) 428 return 1; 429 430 val >>= desc->div_shift; 431 val &= (1 << desc->div_bits) - 1; 432 433 if (!val && desc->div_val0) 434 return desc->div_val0; 435 436 return (val + desc->div_offset) * desc->div_step; 437 } 438 439 static int en7523_pci_is_enabled(struct clk_hw *hw) 440 { 441 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 442 443 return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); 444 } 445 446 static int en7523_pci_prepare(struct clk_hw *hw) 447 { 448 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 449 void __iomem *np_base = cg->base; 450 u32 val, mask; 451 452 /* Need to pull device low before reset */ 453 val = readl(np_base + REG_PCI_CONTROL); 454 val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); 455 writel(val, np_base + REG_PCI_CONTROL); 456 usleep_range(1000, 2000); 457 458 /* Enable PCIe port 1 */ 459 val |= REG_PCI_CONTROL_REFCLK_EN1; 460 writel(val, np_base + REG_PCI_CONTROL); 461 usleep_range(1000, 2000); 462 463 /* Reset to default */ 464 val = readl(np_base + REG_RESET_CONTROL1); 465 mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | 466 REG_RESET_CONTROL_PCIEHB; 467 writel(val & ~mask, np_base + REG_RESET_CONTROL1); 468 usleep_range(1000, 2000); 469 writel(val | mask, np_base + REG_RESET_CONTROL1); 470 msleep(100); 471 writel(val & ~mask, np_base + REG_RESET_CONTROL1); 472 usleep_range(5000, 10000); 473 474 /* Release device */ 475 mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; 476 val = readl(np_base + REG_PCI_CONTROL); 477 writel(val & ~mask, np_base + REG_PCI_CONTROL); 478 usleep_range(1000, 2000); 479 writel(val | mask, np_base + REG_PCI_CONTROL); 480 msleep(250); 481 482 return 0; 483 } 484 485 static void en7523_pci_unprepare(struct clk_hw *hw) 486 { 487 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 488 void __iomem *np_base = cg->base; 489 u32 val; 490 491 val = readl(np_base + REG_PCI_CONTROL); 492 val &= ~REG_PCI_CONTROL_REFCLK_EN1; 493 writel(val, np_base + REG_PCI_CONTROL); 494 } 495 496 static struct clk_hw *en7523_register_pcie_clk(struct device *dev, 497 void __iomem *np_base) 498 { 499 const struct en_clk_soc_data *soc_data = device_get_match_data(dev); 500 struct clk_init_data init = { 501 .name = "pcie", 502 .ops = &soc_data->pcie_ops, 503 }; 504 struct en_clk_gate *cg; 505 506 cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); 507 if (!cg) 508 return NULL; 509 510 cg->base = np_base; 511 cg->hw.init = &init; 512 513 if (init.ops->unprepare) 514 init.ops->unprepare(&cg->hw); 515 516 if (clk_hw_register(dev, &cg->hw)) 517 return NULL; 518 519 return &cg->hw; 520 } 521 522 static int en7581_pci_is_enabled(struct clk_hw *hw) 523 { 524 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 525 u32 val, mask; 526 527 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; 528 val = readl(cg->base + REG_PCI_CONTROL); 529 return (val & mask) == mask; 530 } 531 532 static int en7581_pci_enable(struct clk_hw *hw) 533 { 534 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 535 void __iomem *np_base = cg->base; 536 u32 val, mask; 537 538 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | 539 REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | 540 REG_PCI_CONTROL_PERSTOUT; 541 val = readl(np_base + REG_PCI_CONTROL); 542 writel(val | mask, np_base + REG_PCI_CONTROL); 543 544 return 0; 545 } 546 547 static void en7581_pci_disable(struct clk_hw *hw) 548 { 549 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 550 void __iomem *np_base = cg->base; 551 u32 val, mask; 552 553 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | 554 REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | 555 REG_PCI_CONTROL_PERSTOUT; 556 val = readl(np_base + REG_PCI_CONTROL); 557 writel(val & ~mask, np_base + REG_PCI_CONTROL); 558 usleep_range(1000, 2000); 559 } 560 561 static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, 562 void __iomem *base, void __iomem *np_base) 563 { 564 struct clk_hw *hw; 565 u32 rate; 566 int i; 567 568 for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { 569 const struct en_clk_desc *desc = &en7523_base_clks[i]; 570 u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg; 571 u32 val = readl(base + desc->base_reg); 572 573 rate = en7523_get_base_rate(desc, val); 574 val = readl(base + reg); 575 rate /= en7523_get_div(desc, val); 576 577 hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); 578 if (IS_ERR(hw)) { 579 pr_err("Failed to register clk %s: %ld\n", 580 desc->name, PTR_ERR(hw)); 581 continue; 582 } 583 584 clk_data->hws[desc->id] = hw; 585 } 586 587 hw = en7523_register_pcie_clk(dev, np_base); 588 clk_data->hws[EN7523_CLK_PCIE] = hw; 589 } 590 591 static int en7523_clk_hw_init(struct platform_device *pdev, 592 struct clk_hw_onecell_data *clk_data) 593 { 594 void __iomem *base, *np_base; 595 596 base = devm_platform_ioremap_resource(pdev, 0); 597 if (IS_ERR(base)) 598 return PTR_ERR(base); 599 600 np_base = devm_platform_ioremap_resource(pdev, 1); 601 if (IS_ERR(np_base)) 602 return PTR_ERR(np_base); 603 604 en7523_register_clocks(&pdev->dev, clk_data, base, np_base); 605 606 return en7581_reset_register(&pdev->dev, np_base, en7523_rst_map, 607 ARRAY_SIZE(en7523_rst_map)); 608 } 609 610 static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, 611 struct regmap *map, void __iomem *base) 612 { 613 struct clk_hw *hw; 614 u32 rate; 615 int i; 616 617 for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) { 618 const struct en_clk_desc *desc = &en7581_base_clks[i]; 619 u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; 620 int err; 621 622 err = regmap_read(map, desc->base_reg, &val); 623 if (err) { 624 pr_err("Failed reading fixed clk rate %s: %d\n", 625 desc->name, err); 626 continue; 627 } 628 rate = en7523_get_base_rate(desc, val); 629 630 err = regmap_read(map, reg, &val); 631 if (err) { 632 pr_err("Failed reading fixed clk div %s: %d\n", 633 desc->name, err); 634 continue; 635 } 636 rate /= en7523_get_div(desc, val); 637 638 hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); 639 if (IS_ERR(hw)) { 640 pr_err("Failed to register clk %s: %ld\n", 641 desc->name, PTR_ERR(hw)); 642 continue; 643 } 644 645 clk_data->hws[desc->id] = hw; 646 } 647 648 hw = en7523_register_pcie_clk(dev, base); 649 clk_data->hws[EN7523_CLK_PCIE] = hw; 650 } 651 652 static int en7523_reset_update(struct reset_controller_dev *rcdev, 653 unsigned long id, bool assert) 654 { 655 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 656 void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; 657 u32 val; 658 659 val = readl(addr); 660 if (assert) 661 val |= BIT(id % RST_NR_PER_BANK); 662 else 663 val &= ~BIT(id % RST_NR_PER_BANK); 664 writel(val, addr); 665 666 return 0; 667 } 668 669 static int en7523_reset_assert(struct reset_controller_dev *rcdev, 670 unsigned long id) 671 { 672 return en7523_reset_update(rcdev, id, true); 673 } 674 675 static int en7523_reset_deassert(struct reset_controller_dev *rcdev, 676 unsigned long id) 677 { 678 return en7523_reset_update(rcdev, id, false); 679 } 680 681 static int en7523_reset_status(struct reset_controller_dev *rcdev, 682 unsigned long id) 683 { 684 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 685 void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; 686 687 return !!(readl(addr) & BIT(id % RST_NR_PER_BANK)); 688 } 689 690 static int en7523_reset_xlate(struct reset_controller_dev *rcdev, 691 const struct of_phandle_args *reset_spec) 692 { 693 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 694 695 if (reset_spec->args[0] >= rcdev->nr_resets) 696 return -EINVAL; 697 698 return rst_data->idx_map[reset_spec->args[0]]; 699 } 700 701 static const struct reset_control_ops en7581_reset_ops = { 702 .assert = en7523_reset_assert, 703 .deassert = en7523_reset_deassert, 704 .status = en7523_reset_status, 705 }; 706 707 static int en7581_reset_register(struct device *dev, void __iomem *base, 708 const u16 *rst_map, int nr_resets) 709 { 710 struct en_rst_data *rst_data; 711 712 rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); 713 if (!rst_data) 714 return -ENOMEM; 715 716 rst_data->bank_ofs = en7581_rst_ofs; 717 rst_data->idx_map = rst_map; 718 rst_data->base = base; 719 720 rst_data->rcdev.nr_resets = nr_resets; 721 rst_data->rcdev.of_xlate = en7523_reset_xlate; 722 rst_data->rcdev.ops = &en7581_reset_ops; 723 rst_data->rcdev.of_node = dev->of_node; 724 rst_data->rcdev.of_reset_n_cells = 1; 725 rst_data->rcdev.owner = THIS_MODULE; 726 rst_data->rcdev.dev = dev; 727 728 return devm_reset_controller_register(dev, &rst_data->rcdev); 729 } 730 731 static int en7581_clk_hw_init(struct platform_device *pdev, 732 struct clk_hw_onecell_data *clk_data) 733 { 734 struct regmap *map; 735 void __iomem *base; 736 u32 val; 737 738 map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); 739 if (IS_ERR(map)) 740 return PTR_ERR(map); 741 742 base = devm_platform_ioremap_resource(pdev, 0); 743 if (IS_ERR(base)) 744 return PTR_ERR(base); 745 746 en7581_register_clocks(&pdev->dev, clk_data, map, base); 747 748 val = readl(base + REG_NP_SCU_SSTR); 749 val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); 750 writel(val, base + REG_NP_SCU_SSTR); 751 val = readl(base + REG_NP_SCU_PCIC); 752 writel(val | 3, base + REG_NP_SCU_PCIC); 753 754 return en7581_reset_register(&pdev->dev, base, en7581_rst_map, 755 ARRAY_SIZE(en7581_rst_map)); 756 } 757 758 static int en7523_clk_probe(struct platform_device *pdev) 759 { 760 struct device_node *node = pdev->dev.of_node; 761 const struct en_clk_soc_data *soc_data; 762 struct clk_hw_onecell_data *clk_data; 763 int r; 764 765 soc_data = device_get_match_data(&pdev->dev); 766 767 clk_data = devm_kzalloc(&pdev->dev, 768 struct_size(clk_data, hws, soc_data->num_clocks), 769 GFP_KERNEL); 770 if (!clk_data) 771 return -ENOMEM; 772 773 clk_data->num = soc_data->num_clocks; 774 r = soc_data->hw_init(pdev, clk_data); 775 if (r) 776 return r; 777 778 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 779 } 780 781 static const struct en_clk_soc_data en7523_data = { 782 .num_clocks = ARRAY_SIZE(en7523_base_clks) + 1, 783 .pcie_ops = { 784 .is_enabled = en7523_pci_is_enabled, 785 .prepare = en7523_pci_prepare, 786 .unprepare = en7523_pci_unprepare, 787 }, 788 .hw_init = en7523_clk_hw_init, 789 }; 790 791 static const struct en_clk_soc_data en7581_data = { 792 /* We increment num_clocks by 1 to account for additional PCIe clock */ 793 .num_clocks = ARRAY_SIZE(en7581_base_clks) + 1, 794 .pcie_ops = { 795 .is_enabled = en7581_pci_is_enabled, 796 .enable = en7581_pci_enable, 797 .disable = en7581_pci_disable, 798 }, 799 .hw_init = en7581_clk_hw_init, 800 }; 801 802 static const struct of_device_id of_match_clk_en7523[] = { 803 { .compatible = "airoha,en7523-scu", .data = &en7523_data }, 804 { .compatible = "airoha,en7581-scu", .data = &en7581_data }, 805 { /* sentinel */ } 806 }; 807 808 static struct platform_driver clk_en7523_drv = { 809 .probe = en7523_clk_probe, 810 .driver = { 811 .name = "clk-en7523", 812 .of_match_table = of_match_clk_en7523, 813 .suppress_bind_attrs = true, 814 }, 815 }; 816 817 static int __init clk_en7523_init(void) 818 { 819 return platform_driver_register(&clk_en7523_drv); 820 } 821 822 arch_initcall(clk_en7523_init); 823