1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/delay.h> 4 #include <linux/clk-provider.h> 5 #include <linux/io.h> 6 #include <linux/mfd/syscon.h> 7 #include <linux/platform_device.h> 8 #include <linux/property.h> 9 #include <linux/regmap.h> 10 #include <linux/reset-controller.h> 11 #include <dt-bindings/clock/en7523-clk.h> 12 #include <dt-bindings/reset/airoha,en7581-reset.h> 13 14 #define RST_NR_PER_BANK 32 15 16 #define REG_PCI_CONTROL 0x88 17 #define REG_PCI_CONTROL_PERSTOUT BIT(29) 18 #define REG_PCI_CONTROL_PERSTOUT1 BIT(26) 19 #define REG_PCI_CONTROL_REFCLK_EN0 BIT(23) 20 #define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) 21 #define REG_PCI_CONTROL_PERSTOUT2 BIT(16) 22 #define REG_GSW_CLK_DIV_SEL 0x1b4 23 #define REG_EMI_CLK_DIV_SEL 0x1b8 24 #define REG_BUS_CLK_DIV_SEL 0x1bc 25 #define REG_SPI_CLK_DIV_SEL 0x1c4 26 #define REG_SPI_CLK_FREQ_SEL 0x1c8 27 #define REG_NPU_CLK_DIV_SEL 0x1fc 28 #define REG_CRYPTO_CLKSRC 0x200 29 #define REG_RESET_CONTROL2 0x830 30 #define REG_RESET2_CONTROL_PCIE2 BIT(27) 31 #define REG_RESET_CONTROL1 0x834 32 #define REG_RESET_CONTROL_PCIEHB BIT(29) 33 #define REG_RESET_CONTROL_PCIE1 BIT(27) 34 #define REG_RESET_CONTROL_PCIE2 BIT(26) 35 /* EN7581 */ 36 #define REG_NP_SCU_PCIC 0x88 37 #define REG_NP_SCU_SSTR 0x9c 38 #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) 39 #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) 40 #define REG_CRYPTO_CLKSRC2 0x20c 41 42 #define REG_RST_CTRL2 0x830 43 #define REG_RST_CTRL1 0x834 44 45 struct en_clk_desc { 46 int id; 47 const char *name; 48 u32 base_reg; 49 u8 base_bits; 50 u8 base_shift; 51 union { 52 const unsigned int *base_values; 53 unsigned int base_value; 54 }; 55 size_t n_base_values; 56 57 u16 div_reg; 58 u8 div_bits; 59 u8 div_shift; 60 u16 div_val0; 61 u8 div_step; 62 u8 div_offset; 63 }; 64 65 struct en_clk_gate { 66 void __iomem *base; 67 struct clk_hw hw; 68 }; 69 70 struct en_rst_data { 71 const u16 *bank_ofs; 72 const u16 *idx_map; 73 void __iomem *base; 74 struct reset_controller_dev rcdev; 75 }; 76 77 struct en_clk_soc_data { 78 const struct clk_ops pcie_ops; 79 int (*hw_init)(struct platform_device *pdev, 80 struct clk_hw_onecell_data *clk_data); 81 }; 82 83 static const u32 gsw_base[] = { 400000000, 500000000 }; 84 static const u32 emi_base[] = { 333000000, 400000000 }; 85 static const u32 bus_base[] = { 500000000, 540000000 }; 86 static const u32 slic_base[] = { 100000000, 3125000 }; 87 static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; 88 /* EN7581 */ 89 static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 }; 90 static const u32 bus7581_base[] = { 600000000, 540000000 }; 91 static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 }; 92 static const u32 crypto_base[] = { 540000000, 480000000 }; 93 94 static const struct en_clk_desc en7523_base_clks[] = { 95 { 96 .id = EN7523_CLK_GSW, 97 .name = "gsw", 98 99 .base_reg = REG_GSW_CLK_DIV_SEL, 100 .base_bits = 1, 101 .base_shift = 8, 102 .base_values = gsw_base, 103 .n_base_values = ARRAY_SIZE(gsw_base), 104 105 .div_bits = 3, 106 .div_shift = 0, 107 .div_step = 1, 108 .div_offset = 1, 109 }, { 110 .id = EN7523_CLK_EMI, 111 .name = "emi", 112 113 .base_reg = REG_EMI_CLK_DIV_SEL, 114 .base_bits = 1, 115 .base_shift = 8, 116 .base_values = emi_base, 117 .n_base_values = ARRAY_SIZE(emi_base), 118 119 .div_bits = 3, 120 .div_shift = 0, 121 .div_step = 1, 122 .div_offset = 1, 123 }, { 124 .id = EN7523_CLK_BUS, 125 .name = "bus", 126 127 .base_reg = REG_BUS_CLK_DIV_SEL, 128 .base_bits = 1, 129 .base_shift = 8, 130 .base_values = bus_base, 131 .n_base_values = ARRAY_SIZE(bus_base), 132 133 .div_bits = 3, 134 .div_shift = 0, 135 .div_step = 1, 136 .div_offset = 1, 137 }, { 138 .id = EN7523_CLK_SLIC, 139 .name = "slic", 140 141 .base_reg = REG_SPI_CLK_FREQ_SEL, 142 .base_bits = 1, 143 .base_shift = 0, 144 .base_values = slic_base, 145 .n_base_values = ARRAY_SIZE(slic_base), 146 147 .div_reg = REG_SPI_CLK_DIV_SEL, 148 .div_bits = 5, 149 .div_shift = 24, 150 .div_val0 = 20, 151 .div_step = 2, 152 }, { 153 .id = EN7523_CLK_SPI, 154 .name = "spi", 155 156 .base_reg = REG_SPI_CLK_DIV_SEL, 157 158 .base_value = 400000000, 159 160 .div_bits = 5, 161 .div_shift = 8, 162 .div_val0 = 40, 163 .div_step = 2, 164 }, { 165 .id = EN7523_CLK_NPU, 166 .name = "npu", 167 168 .base_reg = REG_NPU_CLK_DIV_SEL, 169 .base_bits = 2, 170 .base_shift = 8, 171 .base_values = npu_base, 172 .n_base_values = ARRAY_SIZE(npu_base), 173 174 .div_bits = 3, 175 .div_shift = 0, 176 .div_step = 1, 177 .div_offset = 1, 178 }, { 179 .id = EN7523_CLK_CRYPTO, 180 .name = "crypto", 181 182 .base_reg = REG_CRYPTO_CLKSRC, 183 .base_bits = 1, 184 .base_shift = 0, 185 .base_values = emi_base, 186 .n_base_values = ARRAY_SIZE(emi_base), 187 } 188 }; 189 190 static const struct en_clk_desc en7581_base_clks[] = { 191 { 192 .id = EN7523_CLK_GSW, 193 .name = "gsw", 194 195 .base_reg = REG_GSW_CLK_DIV_SEL, 196 .base_bits = 1, 197 .base_shift = 8, 198 .base_values = gsw_base, 199 .n_base_values = ARRAY_SIZE(gsw_base), 200 201 .div_bits = 3, 202 .div_shift = 0, 203 .div_step = 1, 204 .div_offset = 1, 205 }, { 206 .id = EN7523_CLK_EMI, 207 .name = "emi", 208 209 .base_reg = REG_EMI_CLK_DIV_SEL, 210 .base_bits = 2, 211 .base_shift = 8, 212 .base_values = emi7581_base, 213 .n_base_values = ARRAY_SIZE(emi7581_base), 214 215 .div_bits = 3, 216 .div_shift = 0, 217 .div_step = 1, 218 .div_offset = 1, 219 }, { 220 .id = EN7523_CLK_BUS, 221 .name = "bus", 222 223 .base_reg = REG_BUS_CLK_DIV_SEL, 224 .base_bits = 1, 225 .base_shift = 8, 226 .base_values = bus7581_base, 227 .n_base_values = ARRAY_SIZE(bus7581_base), 228 229 .div_bits = 3, 230 .div_shift = 0, 231 .div_step = 1, 232 .div_offset = 1, 233 }, { 234 .id = EN7523_CLK_SLIC, 235 .name = "slic", 236 237 .base_reg = REG_SPI_CLK_FREQ_SEL, 238 .base_bits = 1, 239 .base_shift = 0, 240 .base_values = slic_base, 241 .n_base_values = ARRAY_SIZE(slic_base), 242 243 .div_reg = REG_SPI_CLK_DIV_SEL, 244 .div_bits = 5, 245 .div_shift = 24, 246 .div_val0 = 20, 247 .div_step = 2, 248 }, { 249 .id = EN7523_CLK_SPI, 250 .name = "spi", 251 252 .base_reg = REG_SPI_CLK_DIV_SEL, 253 254 .base_value = 400000000, 255 256 .div_bits = 5, 257 .div_shift = 8, 258 .div_val0 = 40, 259 .div_step = 2, 260 }, { 261 .id = EN7523_CLK_NPU, 262 .name = "npu", 263 264 .base_reg = REG_NPU_CLK_DIV_SEL, 265 .base_bits = 2, 266 .base_shift = 8, 267 .base_values = npu7581_base, 268 .n_base_values = ARRAY_SIZE(npu7581_base), 269 270 .div_bits = 3, 271 .div_shift = 0, 272 .div_step = 1, 273 .div_offset = 1, 274 }, { 275 .id = EN7523_CLK_CRYPTO, 276 .name = "crypto", 277 278 .base_reg = REG_CRYPTO_CLKSRC2, 279 .base_bits = 1, 280 .base_shift = 0, 281 .base_values = crypto_base, 282 .n_base_values = ARRAY_SIZE(crypto_base), 283 } 284 }; 285 286 static const u16 en7581_rst_ofs[] = { 287 REG_RST_CTRL2, 288 REG_RST_CTRL1, 289 }; 290 291 static const u16 en7581_rst_map[] = { 292 /* RST_CTRL2 */ 293 [EN7581_XPON_PHY_RST] = 0, 294 [EN7581_CPU_TIMER2_RST] = 2, 295 [EN7581_HSUART_RST] = 3, 296 [EN7581_UART4_RST] = 4, 297 [EN7581_UART5_RST] = 5, 298 [EN7581_I2C2_RST] = 6, 299 [EN7581_XSI_MAC_RST] = 7, 300 [EN7581_XSI_PHY_RST] = 8, 301 [EN7581_NPU_RST] = 9, 302 [EN7581_I2S_RST] = 10, 303 [EN7581_TRNG_RST] = 11, 304 [EN7581_TRNG_MSTART_RST] = 12, 305 [EN7581_DUAL_HSI0_RST] = 13, 306 [EN7581_DUAL_HSI1_RST] = 14, 307 [EN7581_HSI_RST] = 15, 308 [EN7581_DUAL_HSI0_MAC_RST] = 16, 309 [EN7581_DUAL_HSI1_MAC_RST] = 17, 310 [EN7581_HSI_MAC_RST] = 18, 311 [EN7581_WDMA_RST] = 19, 312 [EN7581_WOE0_RST] = 20, 313 [EN7581_WOE1_RST] = 21, 314 [EN7581_HSDMA_RST] = 22, 315 [EN7581_TDMA_RST] = 24, 316 [EN7581_EMMC_RST] = 25, 317 [EN7581_SOE_RST] = 26, 318 [EN7581_PCIE2_RST] = 27, 319 [EN7581_XFP_MAC_RST] = 28, 320 [EN7581_USB_HOST_P1_RST] = 29, 321 [EN7581_USB_HOST_P1_U3_PHY_RST] = 30, 322 /* RST_CTRL1 */ 323 [EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, 324 [EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1, 325 [EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2, 326 [EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, 327 [EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6, 328 [EN7581_TIMER_RST] = RST_NR_PER_BANK + 8, 329 [EN7581_PCM1_RST] = RST_NR_PER_BANK + 11, 330 [EN7581_UART_RST] = RST_NR_PER_BANK + 12, 331 [EN7581_GPIO_RST] = RST_NR_PER_BANK + 13, 332 [EN7581_GDMA_RST] = RST_NR_PER_BANK + 14, 333 [EN7581_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, 334 [EN7581_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, 335 [EN7581_SFC_RST] = RST_NR_PER_BANK + 18, 336 [EN7581_UART2_RST] = RST_NR_PER_BANK + 19, 337 [EN7581_GDMP_RST] = RST_NR_PER_BANK + 20, 338 [EN7581_FE_RST] = RST_NR_PER_BANK + 21, 339 [EN7581_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, 340 [EN7581_GSW_RST] = RST_NR_PER_BANK + 23, 341 [EN7581_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, 342 [EN7581_PCIE0_RST] = RST_NR_PER_BANK + 26, 343 [EN7581_PCIE1_RST] = RST_NR_PER_BANK + 27, 344 [EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28, 345 [EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29, 346 [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31, 347 }; 348 349 static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val) 350 { 351 if (!desc->base_bits) 352 return desc->base_value; 353 354 val >>= desc->base_shift; 355 val &= (1 << desc->base_bits) - 1; 356 357 if (val >= desc->n_base_values) 358 return 0; 359 360 return desc->base_values[val]; 361 } 362 363 static u32 en7523_get_div(const struct en_clk_desc *desc, u32 val) 364 { 365 if (!desc->div_bits) 366 return 1; 367 368 val >>= desc->div_shift; 369 val &= (1 << desc->div_bits) - 1; 370 371 if (!val && desc->div_val0) 372 return desc->div_val0; 373 374 return (val + desc->div_offset) * desc->div_step; 375 } 376 377 static int en7523_pci_is_enabled(struct clk_hw *hw) 378 { 379 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 380 381 return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); 382 } 383 384 static int en7523_pci_prepare(struct clk_hw *hw) 385 { 386 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 387 void __iomem *np_base = cg->base; 388 u32 val, mask; 389 390 /* Need to pull device low before reset */ 391 val = readl(np_base + REG_PCI_CONTROL); 392 val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); 393 writel(val, np_base + REG_PCI_CONTROL); 394 usleep_range(1000, 2000); 395 396 /* Enable PCIe port 1 */ 397 val |= REG_PCI_CONTROL_REFCLK_EN1; 398 writel(val, np_base + REG_PCI_CONTROL); 399 usleep_range(1000, 2000); 400 401 /* Reset to default */ 402 val = readl(np_base + REG_RESET_CONTROL1); 403 mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | 404 REG_RESET_CONTROL_PCIEHB; 405 writel(val & ~mask, np_base + REG_RESET_CONTROL1); 406 usleep_range(1000, 2000); 407 writel(val | mask, np_base + REG_RESET_CONTROL1); 408 msleep(100); 409 writel(val & ~mask, np_base + REG_RESET_CONTROL1); 410 usleep_range(5000, 10000); 411 412 /* Release device */ 413 mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; 414 val = readl(np_base + REG_PCI_CONTROL); 415 writel(val & ~mask, np_base + REG_PCI_CONTROL); 416 usleep_range(1000, 2000); 417 writel(val | mask, np_base + REG_PCI_CONTROL); 418 msleep(250); 419 420 return 0; 421 } 422 423 static void en7523_pci_unprepare(struct clk_hw *hw) 424 { 425 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 426 void __iomem *np_base = cg->base; 427 u32 val; 428 429 val = readl(np_base + REG_PCI_CONTROL); 430 val &= ~REG_PCI_CONTROL_REFCLK_EN1; 431 writel(val, np_base + REG_PCI_CONTROL); 432 } 433 434 static struct clk_hw *en7523_register_pcie_clk(struct device *dev, 435 void __iomem *np_base) 436 { 437 const struct en_clk_soc_data *soc_data = device_get_match_data(dev); 438 struct clk_init_data init = { 439 .name = "pcie", 440 .ops = &soc_data->pcie_ops, 441 }; 442 struct en_clk_gate *cg; 443 444 cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); 445 if (!cg) 446 return NULL; 447 448 cg->base = np_base; 449 cg->hw.init = &init; 450 451 if (init.ops->unprepare) 452 init.ops->unprepare(&cg->hw); 453 454 if (clk_hw_register(dev, &cg->hw)) 455 return NULL; 456 457 return &cg->hw; 458 } 459 460 static int en7581_pci_is_enabled(struct clk_hw *hw) 461 { 462 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 463 u32 val, mask; 464 465 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; 466 val = readl(cg->base + REG_PCI_CONTROL); 467 return (val & mask) == mask; 468 } 469 470 static int en7581_pci_enable(struct clk_hw *hw) 471 { 472 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 473 void __iomem *np_base = cg->base; 474 u32 val, mask; 475 476 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | 477 REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | 478 REG_PCI_CONTROL_PERSTOUT; 479 val = readl(np_base + REG_PCI_CONTROL); 480 writel(val | mask, np_base + REG_PCI_CONTROL); 481 msleep(250); 482 483 return 0; 484 } 485 486 static void en7581_pci_disable(struct clk_hw *hw) 487 { 488 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 489 void __iomem *np_base = cg->base; 490 u32 val, mask; 491 492 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | 493 REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | 494 REG_PCI_CONTROL_PERSTOUT; 495 val = readl(np_base + REG_PCI_CONTROL); 496 writel(val & ~mask, np_base + REG_PCI_CONTROL); 497 usleep_range(1000, 2000); 498 } 499 500 static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, 501 void __iomem *base, void __iomem *np_base) 502 { 503 struct clk_hw *hw; 504 u32 rate; 505 int i; 506 507 clk_data->num = EN7523_NUM_CLOCKS; 508 509 for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { 510 const struct en_clk_desc *desc = &en7523_base_clks[i]; 511 u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg; 512 u32 val = readl(base + desc->base_reg); 513 514 rate = en7523_get_base_rate(desc, val); 515 val = readl(base + reg); 516 rate /= en7523_get_div(desc, val); 517 518 hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); 519 if (IS_ERR(hw)) { 520 pr_err("Failed to register clk %s: %ld\n", 521 desc->name, PTR_ERR(hw)); 522 continue; 523 } 524 525 clk_data->hws[desc->id] = hw; 526 } 527 528 hw = en7523_register_pcie_clk(dev, np_base); 529 clk_data->hws[EN7523_CLK_PCIE] = hw; 530 } 531 532 static int en7523_clk_hw_init(struct platform_device *pdev, 533 struct clk_hw_onecell_data *clk_data) 534 { 535 void __iomem *base, *np_base; 536 537 base = devm_platform_ioremap_resource(pdev, 0); 538 if (IS_ERR(base)) 539 return PTR_ERR(base); 540 541 np_base = devm_platform_ioremap_resource(pdev, 1); 542 if (IS_ERR(np_base)) 543 return PTR_ERR(np_base); 544 545 en7523_register_clocks(&pdev->dev, clk_data, base, np_base); 546 547 return 0; 548 } 549 550 static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, 551 struct regmap *map, void __iomem *base) 552 { 553 struct clk_hw *hw; 554 u32 rate; 555 int i; 556 557 for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) { 558 const struct en_clk_desc *desc = &en7581_base_clks[i]; 559 u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; 560 int err; 561 562 err = regmap_read(map, desc->base_reg, &val); 563 if (err) { 564 pr_err("Failed reading fixed clk rate %s: %d\n", 565 desc->name, err); 566 continue; 567 } 568 rate = en7523_get_base_rate(desc, val); 569 570 err = regmap_read(map, reg, &val); 571 if (err) { 572 pr_err("Failed reading fixed clk div %s: %d\n", 573 desc->name, err); 574 continue; 575 } 576 rate /= en7523_get_div(desc, val); 577 578 hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); 579 if (IS_ERR(hw)) { 580 pr_err("Failed to register clk %s: %ld\n", 581 desc->name, PTR_ERR(hw)); 582 continue; 583 } 584 585 clk_data->hws[desc->id] = hw; 586 } 587 588 hw = en7523_register_pcie_clk(dev, base); 589 clk_data->hws[EN7523_CLK_PCIE] = hw; 590 591 clk_data->num = EN7523_NUM_CLOCKS; 592 } 593 594 static int en7523_reset_update(struct reset_controller_dev *rcdev, 595 unsigned long id, bool assert) 596 { 597 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 598 void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; 599 u32 val; 600 601 val = readl(addr); 602 if (assert) 603 val |= BIT(id % RST_NR_PER_BANK); 604 else 605 val &= ~BIT(id % RST_NR_PER_BANK); 606 writel(val, addr); 607 608 return 0; 609 } 610 611 static int en7523_reset_assert(struct reset_controller_dev *rcdev, 612 unsigned long id) 613 { 614 return en7523_reset_update(rcdev, id, true); 615 } 616 617 static int en7523_reset_deassert(struct reset_controller_dev *rcdev, 618 unsigned long id) 619 { 620 return en7523_reset_update(rcdev, id, false); 621 } 622 623 static int en7523_reset_status(struct reset_controller_dev *rcdev, 624 unsigned long id) 625 { 626 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 627 void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; 628 629 return !!(readl(addr) & BIT(id % RST_NR_PER_BANK)); 630 } 631 632 static int en7523_reset_xlate(struct reset_controller_dev *rcdev, 633 const struct of_phandle_args *reset_spec) 634 { 635 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 636 637 if (reset_spec->args[0] >= rcdev->nr_resets) 638 return -EINVAL; 639 640 return rst_data->idx_map[reset_spec->args[0]]; 641 } 642 643 static const struct reset_control_ops en7581_reset_ops = { 644 .assert = en7523_reset_assert, 645 .deassert = en7523_reset_deassert, 646 .status = en7523_reset_status, 647 }; 648 649 static int en7581_reset_register(struct device *dev, void __iomem *base) 650 { 651 struct en_rst_data *rst_data; 652 653 rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); 654 if (!rst_data) 655 return -ENOMEM; 656 657 rst_data->bank_ofs = en7581_rst_ofs; 658 rst_data->idx_map = en7581_rst_map; 659 rst_data->base = base; 660 661 rst_data->rcdev.nr_resets = ARRAY_SIZE(en7581_rst_map); 662 rst_data->rcdev.of_xlate = en7523_reset_xlate; 663 rst_data->rcdev.ops = &en7581_reset_ops; 664 rst_data->rcdev.of_node = dev->of_node; 665 rst_data->rcdev.of_reset_n_cells = 1; 666 rst_data->rcdev.owner = THIS_MODULE; 667 rst_data->rcdev.dev = dev; 668 669 return devm_reset_controller_register(dev, &rst_data->rcdev); 670 } 671 672 static int en7581_clk_hw_init(struct platform_device *pdev, 673 struct clk_hw_onecell_data *clk_data) 674 { 675 struct regmap *map; 676 void __iomem *base; 677 u32 val; 678 679 map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); 680 if (IS_ERR(map)) 681 return PTR_ERR(map); 682 683 base = devm_platform_ioremap_resource(pdev, 0); 684 if (IS_ERR(base)) 685 return PTR_ERR(base); 686 687 en7581_register_clocks(&pdev->dev, clk_data, map, base); 688 689 val = readl(base + REG_NP_SCU_SSTR); 690 val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); 691 writel(val, base + REG_NP_SCU_SSTR); 692 val = readl(base + REG_NP_SCU_PCIC); 693 writel(val | 3, base + REG_NP_SCU_PCIC); 694 695 return en7581_reset_register(&pdev->dev, base); 696 } 697 698 static int en7523_clk_probe(struct platform_device *pdev) 699 { 700 struct device_node *node = pdev->dev.of_node; 701 const struct en_clk_soc_data *soc_data; 702 struct clk_hw_onecell_data *clk_data; 703 int r; 704 705 clk_data = devm_kzalloc(&pdev->dev, 706 struct_size(clk_data, hws, EN7523_NUM_CLOCKS), 707 GFP_KERNEL); 708 if (!clk_data) 709 return -ENOMEM; 710 711 soc_data = device_get_match_data(&pdev->dev); 712 r = soc_data->hw_init(pdev, clk_data); 713 if (r) 714 return r; 715 716 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 717 } 718 719 static const struct en_clk_soc_data en7523_data = { 720 .pcie_ops = { 721 .is_enabled = en7523_pci_is_enabled, 722 .prepare = en7523_pci_prepare, 723 .unprepare = en7523_pci_unprepare, 724 }, 725 .hw_init = en7523_clk_hw_init, 726 }; 727 728 static const struct en_clk_soc_data en7581_data = { 729 .pcie_ops = { 730 .is_enabled = en7581_pci_is_enabled, 731 .enable = en7581_pci_enable, 732 .disable = en7581_pci_disable, 733 }, 734 .hw_init = en7581_clk_hw_init, 735 }; 736 737 static const struct of_device_id of_match_clk_en7523[] = { 738 { .compatible = "airoha,en7523-scu", .data = &en7523_data }, 739 { .compatible = "airoha,en7581-scu", .data = &en7581_data }, 740 { /* sentinel */ } 741 }; 742 743 static struct platform_driver clk_en7523_drv = { 744 .probe = en7523_clk_probe, 745 .driver = { 746 .name = "clk-en7523", 747 .of_match_table = of_match_clk_en7523, 748 .suppress_bind_attrs = true, 749 }, 750 }; 751 752 static int __init clk_en7523_init(void) 753 { 754 return platform_driver_register(&clk_en7523_drv); 755 } 756 757 arch_initcall(clk_en7523_init); 758