1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/delay.h> 4 #include <linux/clk-provider.h> 5 #include <linux/io.h> 6 #include <linux/mfd/syscon.h> 7 #include <linux/platform_device.h> 8 #include <linux/property.h> 9 #include <linux/regmap.h> 10 #include <linux/reset-controller.h> 11 #include <dt-bindings/clock/en7523-clk.h> 12 #include <dt-bindings/reset/airoha,en7581-reset.h> 13 14 #define RST_NR_PER_BANK 32 15 16 #define REG_PCI_CONTROL 0x88 17 #define REG_PCI_CONTROL_PERSTOUT BIT(29) 18 #define REG_PCI_CONTROL_PERSTOUT1 BIT(26) 19 #define REG_PCI_CONTROL_REFCLK_EN0 BIT(23) 20 #define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) 21 #define REG_PCI_CONTROL_PERSTOUT2 BIT(16) 22 #define REG_GSW_CLK_DIV_SEL 0x1b4 23 #define REG_EMI_CLK_DIV_SEL 0x1b8 24 #define REG_BUS_CLK_DIV_SEL 0x1bc 25 #define REG_SPI_CLK_DIV_SEL 0x1c4 26 #define REG_SPI_CLK_FREQ_SEL 0x1c8 27 #define REG_NPU_CLK_DIV_SEL 0x1fc 28 #define REG_CRYPTO_CLKSRC 0x200 29 #define REG_RESET_CONTROL2 0x830 30 #define REG_RESET2_CONTROL_PCIE2 BIT(27) 31 #define REG_RESET_CONTROL1 0x834 32 #define REG_RESET_CONTROL_PCIEHB BIT(29) 33 #define REG_RESET_CONTROL_PCIE1 BIT(27) 34 #define REG_RESET_CONTROL_PCIE2 BIT(26) 35 /* EN7581 */ 36 #define REG_NP_SCU_PCIC 0x88 37 #define REG_NP_SCU_SSTR 0x9c 38 #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) 39 #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) 40 #define REG_CRYPTO_CLKSRC2 0x20c 41 42 #define REG_RST_CTRL2 0x830 43 #define REG_RST_CTRL1 0x834 44 45 struct en_clk_desc { 46 int id; 47 const char *name; 48 u32 base_reg; 49 u8 base_bits; 50 u8 base_shift; 51 union { 52 const unsigned int *base_values; 53 unsigned int base_value; 54 }; 55 size_t n_base_values; 56 57 u16 div_reg; 58 u8 div_bits; 59 u8 div_shift; 60 u16 div_val0; 61 u8 div_step; 62 u8 div_offset; 63 }; 64 65 struct en_clk_gate { 66 void __iomem *base; 67 struct clk_hw hw; 68 }; 69 70 struct en_rst_data { 71 const u16 *bank_ofs; 72 const u16 *idx_map; 73 void __iomem *base; 74 struct reset_controller_dev rcdev; 75 }; 76 77 struct en_clk_soc_data { 78 const struct clk_ops pcie_ops; 79 int (*hw_init)(struct platform_device *pdev, 80 struct clk_hw_onecell_data *clk_data); 81 }; 82 83 static const u32 gsw_base[] = { 400000000, 500000000 }; 84 static const u32 emi_base[] = { 333000000, 400000000 }; 85 static const u32 bus_base[] = { 500000000, 540000000 }; 86 static const u32 slic_base[] = { 100000000, 3125000 }; 87 static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; 88 /* EN7581 */ 89 static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 }; 90 static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 }; 91 static const u32 crypto_base[] = { 540000000, 480000000 }; 92 93 static const struct en_clk_desc en7523_base_clks[] = { 94 { 95 .id = EN7523_CLK_GSW, 96 .name = "gsw", 97 98 .base_reg = REG_GSW_CLK_DIV_SEL, 99 .base_bits = 1, 100 .base_shift = 8, 101 .base_values = gsw_base, 102 .n_base_values = ARRAY_SIZE(gsw_base), 103 104 .div_bits = 3, 105 .div_shift = 0, 106 .div_step = 1, 107 .div_offset = 1, 108 }, { 109 .id = EN7523_CLK_EMI, 110 .name = "emi", 111 112 .base_reg = REG_EMI_CLK_DIV_SEL, 113 .base_bits = 1, 114 .base_shift = 8, 115 .base_values = emi_base, 116 .n_base_values = ARRAY_SIZE(emi_base), 117 118 .div_bits = 3, 119 .div_shift = 0, 120 .div_step = 1, 121 .div_offset = 1, 122 }, { 123 .id = EN7523_CLK_BUS, 124 .name = "bus", 125 126 .base_reg = REG_BUS_CLK_DIV_SEL, 127 .base_bits = 1, 128 .base_shift = 8, 129 .base_values = bus_base, 130 .n_base_values = ARRAY_SIZE(bus_base), 131 132 .div_bits = 3, 133 .div_shift = 0, 134 .div_step = 1, 135 .div_offset = 1, 136 }, { 137 .id = EN7523_CLK_SLIC, 138 .name = "slic", 139 140 .base_reg = REG_SPI_CLK_FREQ_SEL, 141 .base_bits = 1, 142 .base_shift = 0, 143 .base_values = slic_base, 144 .n_base_values = ARRAY_SIZE(slic_base), 145 146 .div_reg = REG_SPI_CLK_DIV_SEL, 147 .div_bits = 5, 148 .div_shift = 24, 149 .div_val0 = 20, 150 .div_step = 2, 151 }, { 152 .id = EN7523_CLK_SPI, 153 .name = "spi", 154 155 .base_reg = REG_SPI_CLK_DIV_SEL, 156 157 .base_value = 400000000, 158 159 .div_bits = 5, 160 .div_shift = 8, 161 .div_val0 = 40, 162 .div_step = 2, 163 }, { 164 .id = EN7523_CLK_NPU, 165 .name = "npu", 166 167 .base_reg = REG_NPU_CLK_DIV_SEL, 168 .base_bits = 2, 169 .base_shift = 8, 170 .base_values = npu_base, 171 .n_base_values = ARRAY_SIZE(npu_base), 172 173 .div_bits = 3, 174 .div_shift = 0, 175 .div_step = 1, 176 .div_offset = 1, 177 }, { 178 .id = EN7523_CLK_CRYPTO, 179 .name = "crypto", 180 181 .base_reg = REG_CRYPTO_CLKSRC, 182 .base_bits = 1, 183 .base_shift = 0, 184 .base_values = emi_base, 185 .n_base_values = ARRAY_SIZE(emi_base), 186 } 187 }; 188 189 static const struct en_clk_desc en7581_base_clks[] = { 190 { 191 .id = EN7523_CLK_GSW, 192 .name = "gsw", 193 194 .base_reg = REG_GSW_CLK_DIV_SEL, 195 .base_bits = 1, 196 .base_shift = 8, 197 .base_values = gsw_base, 198 .n_base_values = ARRAY_SIZE(gsw_base), 199 200 .div_bits = 3, 201 .div_shift = 0, 202 .div_step = 1, 203 .div_offset = 1, 204 }, { 205 .id = EN7523_CLK_EMI, 206 .name = "emi", 207 208 .base_reg = REG_EMI_CLK_DIV_SEL, 209 .base_bits = 2, 210 .base_shift = 8, 211 .base_values = emi7581_base, 212 .n_base_values = ARRAY_SIZE(emi7581_base), 213 214 .div_bits = 3, 215 .div_shift = 0, 216 .div_step = 1, 217 .div_offset = 1, 218 }, { 219 .id = EN7523_CLK_BUS, 220 .name = "bus", 221 222 .base_reg = REG_BUS_CLK_DIV_SEL, 223 .base_bits = 1, 224 .base_shift = 8, 225 .base_values = bus_base, 226 .n_base_values = ARRAY_SIZE(bus_base), 227 228 .div_bits = 3, 229 .div_shift = 0, 230 .div_step = 1, 231 .div_offset = 1, 232 }, { 233 .id = EN7523_CLK_SLIC, 234 .name = "slic", 235 236 .base_reg = REG_SPI_CLK_FREQ_SEL, 237 .base_bits = 1, 238 .base_shift = 0, 239 .base_values = slic_base, 240 .n_base_values = ARRAY_SIZE(slic_base), 241 242 .div_reg = REG_SPI_CLK_DIV_SEL, 243 .div_bits = 5, 244 .div_shift = 24, 245 .div_val0 = 20, 246 .div_step = 2, 247 }, { 248 .id = EN7523_CLK_SPI, 249 .name = "spi", 250 251 .base_reg = REG_SPI_CLK_DIV_SEL, 252 253 .base_value = 400000000, 254 255 .div_bits = 5, 256 .div_shift = 8, 257 .div_val0 = 40, 258 .div_step = 2, 259 }, { 260 .id = EN7523_CLK_NPU, 261 .name = "npu", 262 263 .base_reg = REG_NPU_CLK_DIV_SEL, 264 .base_bits = 2, 265 .base_shift = 8, 266 .base_values = npu7581_base, 267 .n_base_values = ARRAY_SIZE(npu7581_base), 268 269 .div_bits = 3, 270 .div_shift = 0, 271 .div_step = 1, 272 .div_offset = 1, 273 }, { 274 .id = EN7523_CLK_CRYPTO, 275 .name = "crypto", 276 277 .base_reg = REG_CRYPTO_CLKSRC2, 278 .base_bits = 1, 279 .base_shift = 0, 280 .base_values = crypto_base, 281 .n_base_values = ARRAY_SIZE(crypto_base), 282 } 283 }; 284 285 static const u16 en7581_rst_ofs[] = { 286 REG_RST_CTRL2, 287 REG_RST_CTRL1, 288 }; 289 290 static const u16 en7581_rst_map[] = { 291 /* RST_CTRL2 */ 292 [EN7581_XPON_PHY_RST] = 0, 293 [EN7581_CPU_TIMER2_RST] = 2, 294 [EN7581_HSUART_RST] = 3, 295 [EN7581_UART4_RST] = 4, 296 [EN7581_UART5_RST] = 5, 297 [EN7581_I2C2_RST] = 6, 298 [EN7581_XSI_MAC_RST] = 7, 299 [EN7581_XSI_PHY_RST] = 8, 300 [EN7581_NPU_RST] = 9, 301 [EN7581_I2S_RST] = 10, 302 [EN7581_TRNG_RST] = 11, 303 [EN7581_TRNG_MSTART_RST] = 12, 304 [EN7581_DUAL_HSI0_RST] = 13, 305 [EN7581_DUAL_HSI1_RST] = 14, 306 [EN7581_HSI_RST] = 15, 307 [EN7581_DUAL_HSI0_MAC_RST] = 16, 308 [EN7581_DUAL_HSI1_MAC_RST] = 17, 309 [EN7581_HSI_MAC_RST] = 18, 310 [EN7581_WDMA_RST] = 19, 311 [EN7581_WOE0_RST] = 20, 312 [EN7581_WOE1_RST] = 21, 313 [EN7581_HSDMA_RST] = 22, 314 [EN7581_TDMA_RST] = 24, 315 [EN7581_EMMC_RST] = 25, 316 [EN7581_SOE_RST] = 26, 317 [EN7581_PCIE2_RST] = 27, 318 [EN7581_XFP_MAC_RST] = 28, 319 [EN7581_USB_HOST_P1_RST] = 29, 320 [EN7581_USB_HOST_P1_U3_PHY_RST] = 30, 321 /* RST_CTRL1 */ 322 [EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, 323 [EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1, 324 [EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2, 325 [EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, 326 [EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6, 327 [EN7581_TIMER_RST] = RST_NR_PER_BANK + 8, 328 [EN7581_PCM1_RST] = RST_NR_PER_BANK + 11, 329 [EN7581_UART_RST] = RST_NR_PER_BANK + 12, 330 [EN7581_GPIO_RST] = RST_NR_PER_BANK + 13, 331 [EN7581_GDMA_RST] = RST_NR_PER_BANK + 14, 332 [EN7581_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, 333 [EN7581_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, 334 [EN7581_SFC_RST] = RST_NR_PER_BANK + 18, 335 [EN7581_UART2_RST] = RST_NR_PER_BANK + 19, 336 [EN7581_GDMP_RST] = RST_NR_PER_BANK + 20, 337 [EN7581_FE_RST] = RST_NR_PER_BANK + 21, 338 [EN7581_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, 339 [EN7581_GSW_RST] = RST_NR_PER_BANK + 23, 340 [EN7581_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, 341 [EN7581_PCIE0_RST] = RST_NR_PER_BANK + 26, 342 [EN7581_PCIE1_RST] = RST_NR_PER_BANK + 27, 343 [EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28, 344 [EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29, 345 [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31, 346 }; 347 348 static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val) 349 { 350 if (!desc->base_bits) 351 return desc->base_value; 352 353 val >>= desc->base_shift; 354 val &= (1 << desc->base_bits) - 1; 355 356 if (val >= desc->n_base_values) 357 return 0; 358 359 return desc->base_values[val]; 360 } 361 362 static u32 en7523_get_div(const struct en_clk_desc *desc, u32 val) 363 { 364 if (!desc->div_bits) 365 return 1; 366 367 val >>= desc->div_shift; 368 val &= (1 << desc->div_bits) - 1; 369 370 if (!val && desc->div_val0) 371 return desc->div_val0; 372 373 return (val + desc->div_offset) * desc->div_step; 374 } 375 376 static int en7523_pci_is_enabled(struct clk_hw *hw) 377 { 378 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 379 380 return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); 381 } 382 383 static int en7523_pci_prepare(struct clk_hw *hw) 384 { 385 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 386 void __iomem *np_base = cg->base; 387 u32 val, mask; 388 389 /* Need to pull device low before reset */ 390 val = readl(np_base + REG_PCI_CONTROL); 391 val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); 392 writel(val, np_base + REG_PCI_CONTROL); 393 usleep_range(1000, 2000); 394 395 /* Enable PCIe port 1 */ 396 val |= REG_PCI_CONTROL_REFCLK_EN1; 397 writel(val, np_base + REG_PCI_CONTROL); 398 usleep_range(1000, 2000); 399 400 /* Reset to default */ 401 val = readl(np_base + REG_RESET_CONTROL1); 402 mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | 403 REG_RESET_CONTROL_PCIEHB; 404 writel(val & ~mask, np_base + REG_RESET_CONTROL1); 405 usleep_range(1000, 2000); 406 writel(val | mask, np_base + REG_RESET_CONTROL1); 407 msleep(100); 408 writel(val & ~mask, np_base + REG_RESET_CONTROL1); 409 usleep_range(5000, 10000); 410 411 /* Release device */ 412 mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; 413 val = readl(np_base + REG_PCI_CONTROL); 414 writel(val & ~mask, np_base + REG_PCI_CONTROL); 415 usleep_range(1000, 2000); 416 writel(val | mask, np_base + REG_PCI_CONTROL); 417 msleep(250); 418 419 return 0; 420 } 421 422 static void en7523_pci_unprepare(struct clk_hw *hw) 423 { 424 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 425 void __iomem *np_base = cg->base; 426 u32 val; 427 428 val = readl(np_base + REG_PCI_CONTROL); 429 val &= ~REG_PCI_CONTROL_REFCLK_EN1; 430 writel(val, np_base + REG_PCI_CONTROL); 431 } 432 433 static struct clk_hw *en7523_register_pcie_clk(struct device *dev, 434 void __iomem *np_base) 435 { 436 const struct en_clk_soc_data *soc_data = device_get_match_data(dev); 437 struct clk_init_data init = { 438 .name = "pcie", 439 .ops = &soc_data->pcie_ops, 440 }; 441 struct en_clk_gate *cg; 442 443 cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); 444 if (!cg) 445 return NULL; 446 447 cg->base = np_base; 448 cg->hw.init = &init; 449 450 if (init.ops->unprepare) 451 init.ops->unprepare(&cg->hw); 452 453 if (clk_hw_register(dev, &cg->hw)) 454 return NULL; 455 456 return &cg->hw; 457 } 458 459 static int en7581_pci_is_enabled(struct clk_hw *hw) 460 { 461 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 462 u32 val, mask; 463 464 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; 465 val = readl(cg->base + REG_PCI_CONTROL); 466 return (val & mask) == mask; 467 } 468 469 static int en7581_pci_enable(struct clk_hw *hw) 470 { 471 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 472 void __iomem *np_base = cg->base; 473 u32 val, mask; 474 475 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | 476 REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | 477 REG_PCI_CONTROL_PERSTOUT; 478 val = readl(np_base + REG_PCI_CONTROL); 479 writel(val | mask, np_base + REG_PCI_CONTROL); 480 msleep(250); 481 482 return 0; 483 } 484 485 static void en7581_pci_disable(struct clk_hw *hw) 486 { 487 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 488 void __iomem *np_base = cg->base; 489 u32 val, mask; 490 491 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | 492 REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | 493 REG_PCI_CONTROL_PERSTOUT; 494 val = readl(np_base + REG_PCI_CONTROL); 495 writel(val & ~mask, np_base + REG_PCI_CONTROL); 496 usleep_range(1000, 2000); 497 } 498 499 static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, 500 void __iomem *base, void __iomem *np_base) 501 { 502 struct clk_hw *hw; 503 u32 rate; 504 int i; 505 506 for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { 507 const struct en_clk_desc *desc = &en7523_base_clks[i]; 508 u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg; 509 u32 val = readl(base + desc->base_reg); 510 511 rate = en7523_get_base_rate(desc, val); 512 val = readl(base + reg); 513 rate /= en7523_get_div(desc, val); 514 515 hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); 516 if (IS_ERR(hw)) { 517 pr_err("Failed to register clk %s: %ld\n", 518 desc->name, PTR_ERR(hw)); 519 continue; 520 } 521 522 clk_data->hws[desc->id] = hw; 523 } 524 525 hw = en7523_register_pcie_clk(dev, np_base); 526 clk_data->hws[EN7523_CLK_PCIE] = hw; 527 528 clk_data->num = EN7523_NUM_CLOCKS; 529 } 530 531 static int en7523_clk_hw_init(struct platform_device *pdev, 532 struct clk_hw_onecell_data *clk_data) 533 { 534 void __iomem *base, *np_base; 535 536 base = devm_platform_ioremap_resource(pdev, 0); 537 if (IS_ERR(base)) 538 return PTR_ERR(base); 539 540 np_base = devm_platform_ioremap_resource(pdev, 1); 541 if (IS_ERR(np_base)) 542 return PTR_ERR(np_base); 543 544 en7523_register_clocks(&pdev->dev, clk_data, base, np_base); 545 546 return 0; 547 } 548 549 static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, 550 struct regmap *map, void __iomem *base) 551 { 552 struct clk_hw *hw; 553 u32 rate; 554 int i; 555 556 for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) { 557 const struct en_clk_desc *desc = &en7581_base_clks[i]; 558 u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; 559 int err; 560 561 err = regmap_read(map, desc->base_reg, &val); 562 if (err) { 563 pr_err("Failed reading fixed clk rate %s: %d\n", 564 desc->name, err); 565 continue; 566 } 567 rate = en7523_get_base_rate(desc, val); 568 569 err = regmap_read(map, reg, &val); 570 if (err) { 571 pr_err("Failed reading fixed clk div %s: %d\n", 572 desc->name, err); 573 continue; 574 } 575 rate /= en7523_get_div(desc, val); 576 577 hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); 578 if (IS_ERR(hw)) { 579 pr_err("Failed to register clk %s: %ld\n", 580 desc->name, PTR_ERR(hw)); 581 continue; 582 } 583 584 clk_data->hws[desc->id] = hw; 585 } 586 587 hw = en7523_register_pcie_clk(dev, base); 588 clk_data->hws[EN7523_CLK_PCIE] = hw; 589 590 clk_data->num = EN7523_NUM_CLOCKS; 591 } 592 593 static int en7523_reset_update(struct reset_controller_dev *rcdev, 594 unsigned long id, bool assert) 595 { 596 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 597 void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; 598 u32 val; 599 600 val = readl(addr); 601 if (assert) 602 val |= BIT(id % RST_NR_PER_BANK); 603 else 604 val &= ~BIT(id % RST_NR_PER_BANK); 605 writel(val, addr); 606 607 return 0; 608 } 609 610 static int en7523_reset_assert(struct reset_controller_dev *rcdev, 611 unsigned long id) 612 { 613 return en7523_reset_update(rcdev, id, true); 614 } 615 616 static int en7523_reset_deassert(struct reset_controller_dev *rcdev, 617 unsigned long id) 618 { 619 return en7523_reset_update(rcdev, id, false); 620 } 621 622 static int en7523_reset_status(struct reset_controller_dev *rcdev, 623 unsigned long id) 624 { 625 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 626 void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; 627 628 return !!(readl(addr) & BIT(id % RST_NR_PER_BANK)); 629 } 630 631 static int en7523_reset_xlate(struct reset_controller_dev *rcdev, 632 const struct of_phandle_args *reset_spec) 633 { 634 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 635 636 if (reset_spec->args[0] >= rcdev->nr_resets) 637 return -EINVAL; 638 639 return rst_data->idx_map[reset_spec->args[0]]; 640 } 641 642 static const struct reset_control_ops en7581_reset_ops = { 643 .assert = en7523_reset_assert, 644 .deassert = en7523_reset_deassert, 645 .status = en7523_reset_status, 646 }; 647 648 static int en7581_reset_register(struct device *dev, void __iomem *base) 649 { 650 struct en_rst_data *rst_data; 651 652 rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); 653 if (!rst_data) 654 return -ENOMEM; 655 656 rst_data->bank_ofs = en7581_rst_ofs; 657 rst_data->idx_map = en7581_rst_map; 658 rst_data->base = base; 659 660 rst_data->rcdev.nr_resets = ARRAY_SIZE(en7581_rst_map); 661 rst_data->rcdev.of_xlate = en7523_reset_xlate; 662 rst_data->rcdev.ops = &en7581_reset_ops; 663 rst_data->rcdev.of_node = dev->of_node; 664 rst_data->rcdev.of_reset_n_cells = 1; 665 rst_data->rcdev.owner = THIS_MODULE; 666 rst_data->rcdev.dev = dev; 667 668 return devm_reset_controller_register(dev, &rst_data->rcdev); 669 } 670 671 static int en7581_clk_hw_init(struct platform_device *pdev, 672 struct clk_hw_onecell_data *clk_data) 673 { 674 struct regmap *map; 675 void __iomem *base; 676 u32 val; 677 678 map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); 679 if (IS_ERR(map)) 680 return PTR_ERR(map); 681 682 base = devm_platform_ioremap_resource(pdev, 0); 683 if (IS_ERR(base)) 684 return PTR_ERR(base); 685 686 en7581_register_clocks(&pdev->dev, clk_data, map, base); 687 688 val = readl(base + REG_NP_SCU_SSTR); 689 val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); 690 writel(val, base + REG_NP_SCU_SSTR); 691 val = readl(base + REG_NP_SCU_PCIC); 692 writel(val | 3, base + REG_NP_SCU_PCIC); 693 694 return en7581_reset_register(&pdev->dev, base); 695 } 696 697 static int en7523_clk_probe(struct platform_device *pdev) 698 { 699 struct device_node *node = pdev->dev.of_node; 700 const struct en_clk_soc_data *soc_data; 701 struct clk_hw_onecell_data *clk_data; 702 int r; 703 704 clk_data = devm_kzalloc(&pdev->dev, 705 struct_size(clk_data, hws, EN7523_NUM_CLOCKS), 706 GFP_KERNEL); 707 if (!clk_data) 708 return -ENOMEM; 709 710 soc_data = device_get_match_data(&pdev->dev); 711 r = soc_data->hw_init(pdev, clk_data); 712 if (r) 713 return r; 714 715 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 716 } 717 718 static const struct en_clk_soc_data en7523_data = { 719 .pcie_ops = { 720 .is_enabled = en7523_pci_is_enabled, 721 .prepare = en7523_pci_prepare, 722 .unprepare = en7523_pci_unprepare, 723 }, 724 .hw_init = en7523_clk_hw_init, 725 }; 726 727 static const struct en_clk_soc_data en7581_data = { 728 .pcie_ops = { 729 .is_enabled = en7581_pci_is_enabled, 730 .enable = en7581_pci_enable, 731 .disable = en7581_pci_disable, 732 }, 733 .hw_init = en7581_clk_hw_init, 734 }; 735 736 static const struct of_device_id of_match_clk_en7523[] = { 737 { .compatible = "airoha,en7523-scu", .data = &en7523_data }, 738 { .compatible = "airoha,en7581-scu", .data = &en7581_data }, 739 { /* sentinel */ } 740 }; 741 742 static struct platform_driver clk_en7523_drv = { 743 .probe = en7523_clk_probe, 744 .driver = { 745 .name = "clk-en7523", 746 .of_match_table = of_match_clk_en7523, 747 .suppress_bind_attrs = true, 748 }, 749 }; 750 751 static int __init clk_en7523_init(void) 752 { 753 return platform_driver_register(&clk_en7523_drv); 754 } 755 756 arch_initcall(clk_en7523_init); 757