1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/bitfield.h> 4 #include <linux/delay.h> 5 #include <linux/clk-provider.h> 6 #include <linux/io.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/platform_device.h> 9 #include <linux/property.h> 10 #include <linux/regmap.h> 11 #include <linux/reset-controller.h> 12 #include <dt-bindings/clock/en7523-clk.h> 13 #include <dt-bindings/reset/airoha,en7523-reset.h> 14 #include <dt-bindings/reset/airoha,en7581-reset.h> 15 #include <dt-bindings/clock/econet,en751221-scu.h> 16 #include <dt-bindings/reset/econet,en751221-scu.h> 17 18 #define RST_NR_PER_BANK 32 19 20 #define REG_PCI_CONTROL 0x88 21 #define REG_PCI_CONTROL_PERSTOUT BIT(29) 22 #define REG_PCI_CONTROL_PERSTOUT1 BIT(26) 23 #define REG_PCI_CONTROL_REFCLK_EN0 BIT(23) 24 #define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) 25 #define REG_PCI_CONTROL_PERSTOUT2 BIT(16) 26 #define REG_GSW_CLK_DIV_SEL 0x1b4 27 #define REG_EMI_CLK_DIV_SEL 0x1b8 28 #define REG_BUS_CLK_DIV_SEL 0x1bc 29 #define REG_SPI_CLK_DIV_SEL 0x1c4 30 #define REG_SPI_CLK_FREQ_SEL 0x1c8 31 #define REG_NPU_CLK_DIV_SEL 0x1fc 32 #define REG_CRYPTO_CLKSRC 0x200 33 #define REG_RESET_CONTROL2 0x830 34 #define REG_RESET2_CONTROL_PCIE2 BIT(27) 35 #define REG_RESET_CONTROL1 0x834 36 #define REG_RESET_CONTROL_PCIEHB BIT(29) 37 #define REG_RESET_CONTROL_PCIE1 BIT(27) 38 #define REG_RESET_CONTROL_PCIE2 BIT(26) 39 #define REG_HIR 0x064 40 #define REG_HIR_MASK GENMASK(31, 16) 41 /* EN7581 */ 42 #define REG_NP_SCU_PCIC 0x88 43 #define REG_NP_SCU_SSTR 0x9c 44 #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) 45 #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) 46 #define REG_CRYPTO_CLKSRC2 0x20c 47 /* EN751221 */ 48 #define EN751221_REG_SPI_DIV 0x0cc 49 #define EN751221_REG_SPI_DIV_MASK GENMASK(31, 8) 50 #define EN751221_SPI_BASE 500000000 51 #define EN751221_SPI_BASE_EN7526C 400000000 52 #define EN751221_SPI_DIV_DEFAULT 40 53 #define EN751221_REG_BUS 0x284 54 #define EN751221_REG_BUS_MASK GENMASK(21, 12) 55 #define EN751221_REG_SSR3 0x094 56 #define EN751221_REG_SSR3_GSW_MASK GENMASK(9, 8) 57 58 #define REG_RST_CTRL2 0x830 59 #define REG_RST_CTRL1 0x834 60 #define EN751221_REG_RST_DMT 0x84 61 #define EN751221_REG_RST_USB 0xec 62 63 #define EN751221_MAX_CLKS 5 64 65 enum en_hir { 66 HIR_UNKNOWN = -1, 67 HIR_TC3169 = 0, 68 HIR_TC3182 = 1, 69 HIR_RT65168 = 2, 70 HIR_RT63165 = 3, 71 HIR_RT63365 = 4, 72 HIR_MT751020 = 5, 73 HIR_MT7505 = 6, 74 HIR_EN751221 = 7, 75 HIR_EN7526C = 8, 76 HIR_EN751627 = 9, 77 HIR_EN7580 = 10, 78 HIR_EN7528 = 11, 79 HIR_EN7523 = 12, 80 HIR_EN7581 = 13, 81 HIR_MAX = 14, 82 }; 83 84 struct en_clk_desc { 85 int id; 86 const char *name; 87 u32 base_reg; 88 u8 base_bits; 89 u8 base_shift; 90 union { 91 const unsigned int *base_values; 92 unsigned int base_value; 93 }; 94 size_t n_base_values; 95 96 u16 div_reg; 97 u8 div_bits; 98 u8 div_shift; 99 u16 div_val0; 100 u8 div_step; 101 u8 div_offset; 102 }; 103 104 struct en_clk_gate { 105 void __iomem *base; 106 struct clk_hw hw; 107 }; 108 109 struct en_rst_data { 110 const u16 *bank_ofs; 111 const u16 *idx_map; 112 void __iomem *base; 113 struct reset_controller_dev rcdev; 114 }; 115 116 struct en_clk_soc_data { 117 u32 num_clocks; 118 const struct clk_ops pcie_ops; 119 int (*hw_init)(struct platform_device *pdev, 120 struct clk_hw_onecell_data *clk_data); 121 }; 122 123 static const u32 gsw_base[] = { 400000000, 500000000 }; 124 static const u32 emi_base[] = { 333000000, 400000000 }; 125 static const u32 bus_base[] = { 500000000, 540000000 }; 126 static const u32 slic_base[] = { 100000000, 3125000 }; 127 static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; 128 /* EN7581 */ 129 static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 }; 130 static const u32 bus7581_base[] = { 600000000, 540000000 }; 131 static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 }; 132 static const u32 crypto_base[] = { 540000000, 480000000 }; 133 static const u32 emmc7581_base[] = { 200000000, 150000000 }; 134 /* EN751221 */ 135 static const u32 gsw751221_base[] = { 500000000, 250000000, 400000000, 200000000 }; 136 137 static const struct en_clk_desc en7523_base_clks[] = { 138 { 139 .id = EN7523_CLK_GSW, 140 .name = "gsw", 141 142 .base_reg = REG_GSW_CLK_DIV_SEL, 143 .base_bits = 1, 144 .base_shift = 8, 145 .base_values = gsw_base, 146 .n_base_values = ARRAY_SIZE(gsw_base), 147 148 .div_bits = 3, 149 .div_shift = 0, 150 .div_step = 1, 151 .div_offset = 1, 152 }, { 153 .id = EN7523_CLK_EMI, 154 .name = "emi", 155 156 .base_reg = REG_EMI_CLK_DIV_SEL, 157 .base_bits = 1, 158 .base_shift = 8, 159 .base_values = emi_base, 160 .n_base_values = ARRAY_SIZE(emi_base), 161 162 .div_bits = 3, 163 .div_shift = 0, 164 .div_step = 1, 165 .div_offset = 1, 166 }, { 167 .id = EN7523_CLK_BUS, 168 .name = "bus", 169 170 .base_reg = REG_BUS_CLK_DIV_SEL, 171 .base_bits = 1, 172 .base_shift = 8, 173 .base_values = bus_base, 174 .n_base_values = ARRAY_SIZE(bus_base), 175 176 .div_bits = 3, 177 .div_shift = 0, 178 .div_step = 1, 179 .div_offset = 1, 180 }, { 181 .id = EN7523_CLK_SLIC, 182 .name = "slic", 183 184 .base_reg = REG_SPI_CLK_FREQ_SEL, 185 .base_bits = 1, 186 .base_shift = 0, 187 .base_values = slic_base, 188 .n_base_values = ARRAY_SIZE(slic_base), 189 190 .div_reg = REG_SPI_CLK_DIV_SEL, 191 .div_bits = 5, 192 .div_shift = 24, 193 .div_val0 = 20, 194 .div_step = 2, 195 }, { 196 .id = EN7523_CLK_SPI, 197 .name = "spi", 198 199 .base_reg = REG_SPI_CLK_DIV_SEL, 200 201 .base_value = 400000000, 202 203 .div_bits = 5, 204 .div_shift = 8, 205 .div_val0 = 40, 206 .div_step = 2, 207 }, { 208 .id = EN7523_CLK_NPU, 209 .name = "npu", 210 211 .base_reg = REG_NPU_CLK_DIV_SEL, 212 .base_bits = 2, 213 .base_shift = 8, 214 .base_values = npu_base, 215 .n_base_values = ARRAY_SIZE(npu_base), 216 217 .div_bits = 3, 218 .div_shift = 0, 219 .div_step = 1, 220 .div_offset = 1, 221 }, { 222 .id = EN7523_CLK_CRYPTO, 223 .name = "crypto", 224 225 .base_reg = REG_CRYPTO_CLKSRC, 226 .base_bits = 1, 227 .base_shift = 0, 228 .base_values = emi_base, 229 .n_base_values = ARRAY_SIZE(emi_base), 230 } 231 }; 232 233 static const struct en_clk_desc en7581_base_clks[] = { 234 { 235 .id = EN7523_CLK_GSW, 236 .name = "gsw", 237 238 .base_reg = REG_GSW_CLK_DIV_SEL, 239 .base_bits = 1, 240 .base_shift = 8, 241 .base_values = gsw_base, 242 .n_base_values = ARRAY_SIZE(gsw_base), 243 244 .div_bits = 3, 245 .div_shift = 0, 246 .div_step = 1, 247 .div_offset = 1, 248 }, { 249 .id = EN7523_CLK_EMI, 250 .name = "emi", 251 252 .base_reg = REG_EMI_CLK_DIV_SEL, 253 .base_bits = 2, 254 .base_shift = 8, 255 .base_values = emi7581_base, 256 .n_base_values = ARRAY_SIZE(emi7581_base), 257 258 .div_bits = 3, 259 .div_shift = 0, 260 .div_step = 1, 261 .div_offset = 1, 262 }, { 263 .id = EN7523_CLK_BUS, 264 .name = "bus", 265 266 .base_reg = REG_BUS_CLK_DIV_SEL, 267 .base_bits = 1, 268 .base_shift = 8, 269 .base_values = bus7581_base, 270 .n_base_values = ARRAY_SIZE(bus7581_base), 271 272 .div_bits = 3, 273 .div_shift = 0, 274 .div_step = 1, 275 .div_offset = 1, 276 }, { 277 .id = EN7523_CLK_SLIC, 278 .name = "slic", 279 280 .base_reg = REG_SPI_CLK_FREQ_SEL, 281 .base_bits = 1, 282 .base_shift = 0, 283 .base_values = slic_base, 284 .n_base_values = ARRAY_SIZE(slic_base), 285 286 .div_reg = REG_SPI_CLK_DIV_SEL, 287 .div_bits = 5, 288 .div_shift = 24, 289 .div_val0 = 20, 290 .div_step = 2, 291 }, { 292 .id = EN7523_CLK_SPI, 293 .name = "spi", 294 295 .base_reg = REG_SPI_CLK_DIV_SEL, 296 297 .base_value = 400000000, 298 299 .div_bits = 5, 300 .div_shift = 8, 301 .div_val0 = 40, 302 .div_step = 2, 303 }, { 304 .id = EN7523_CLK_NPU, 305 .name = "npu", 306 307 .base_reg = REG_NPU_CLK_DIV_SEL, 308 .base_bits = 2, 309 .base_shift = 8, 310 .base_values = npu7581_base, 311 .n_base_values = ARRAY_SIZE(npu7581_base), 312 313 .div_bits = 3, 314 .div_shift = 0, 315 .div_step = 1, 316 .div_offset = 1, 317 }, { 318 .id = EN7523_CLK_CRYPTO, 319 .name = "crypto", 320 321 .base_reg = REG_CRYPTO_CLKSRC2, 322 .base_bits = 1, 323 .base_shift = 0, 324 .base_values = crypto_base, 325 .n_base_values = ARRAY_SIZE(crypto_base), 326 }, { 327 .id = EN7581_CLK_EMMC, 328 .name = "emmc", 329 330 .base_reg = REG_CRYPTO_CLKSRC2, 331 .base_bits = 1, 332 .base_shift = 12, 333 .base_values = emmc7581_base, 334 .n_base_values = ARRAY_SIZE(emmc7581_base), 335 } 336 }; 337 338 static const u16 en7581_rst_ofs[] = { 339 REG_RST_CTRL2, 340 REG_RST_CTRL1, 341 }; 342 343 static const u16 en751221_rst_ofs[] = { 344 REG_RST_CTRL2, 345 REG_RST_CTRL1, 346 EN751221_REG_RST_DMT, 347 EN751221_REG_RST_USB, 348 }; 349 350 static const u16 en7523_rst_map[] = { 351 /* RST_CTRL2 */ 352 [EN7523_XPON_PHY_RST] = 0, 353 [EN7523_XSI_MAC_RST] = 7, 354 [EN7523_XSI_PHY_RST] = 8, 355 [EN7523_NPU_RST] = 9, 356 [EN7523_I2S_RST] = 10, 357 [EN7523_TRNG_RST] = 11, 358 [EN7523_TRNG_MSTART_RST] = 12, 359 [EN7523_DUAL_HSI0_RST] = 13, 360 [EN7523_DUAL_HSI1_RST] = 14, 361 [EN7523_HSI_RST] = 15, 362 [EN7523_DUAL_HSI0_MAC_RST] = 16, 363 [EN7523_DUAL_HSI1_MAC_RST] = 17, 364 [EN7523_HSI_MAC_RST] = 18, 365 [EN7523_WDMA_RST] = 19, 366 [EN7523_WOE0_RST] = 20, 367 [EN7523_WOE1_RST] = 21, 368 [EN7523_HSDMA_RST] = 22, 369 [EN7523_I2C2RBUS_RST] = 23, 370 [EN7523_TDMA_RST] = 24, 371 /* RST_CTRL1 */ 372 [EN7523_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, 373 [EN7523_FE_PDMA_RST] = RST_NR_PER_BANK + 1, 374 [EN7523_FE_QDMA_RST] = RST_NR_PER_BANK + 2, 375 [EN7523_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, 376 [EN7523_CRYPTO_RST] = RST_NR_PER_BANK + 6, 377 [EN7523_TIMER_RST] = RST_NR_PER_BANK + 8, 378 [EN7523_PCM1_RST] = RST_NR_PER_BANK + 11, 379 [EN7523_UART_RST] = RST_NR_PER_BANK + 12, 380 [EN7523_GPIO_RST] = RST_NR_PER_BANK + 13, 381 [EN7523_GDMA_RST] = RST_NR_PER_BANK + 14, 382 [EN7523_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, 383 [EN7523_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, 384 [EN7523_SFC_RST] = RST_NR_PER_BANK + 18, 385 [EN7523_UART2_RST] = RST_NR_PER_BANK + 19, 386 [EN7523_GDMP_RST] = RST_NR_PER_BANK + 20, 387 [EN7523_FE_RST] = RST_NR_PER_BANK + 21, 388 [EN7523_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, 389 [EN7523_GSW_RST] = RST_NR_PER_BANK + 23, 390 [EN7523_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, 391 [EN7523_PCIE0_RST] = RST_NR_PER_BANK + 26, 392 [EN7523_PCIE1_RST] = RST_NR_PER_BANK + 27, 393 [EN7523_PCIE_HB_RST] = RST_NR_PER_BANK + 29, 394 [EN7523_XPON_MAC_RST] = RST_NR_PER_BANK + 31, 395 }; 396 397 static const u16 en7581_rst_map[] = { 398 /* RST_CTRL2 */ 399 [EN7581_XPON_PHY_RST] = 0, 400 [EN7581_CPU_TIMER2_RST] = 2, 401 [EN7581_HSUART_RST] = 3, 402 [EN7581_UART4_RST] = 4, 403 [EN7581_UART5_RST] = 5, 404 [EN7581_I2C2_RST] = 6, 405 [EN7581_XSI_MAC_RST] = 7, 406 [EN7581_XSI_PHY_RST] = 8, 407 [EN7581_NPU_RST] = 9, 408 [EN7581_I2S_RST] = 10, 409 [EN7581_TRNG_RST] = 11, 410 [EN7581_TRNG_MSTART_RST] = 12, 411 [EN7581_DUAL_HSI0_RST] = 13, 412 [EN7581_DUAL_HSI1_RST] = 14, 413 [EN7581_HSI_RST] = 15, 414 [EN7581_DUAL_HSI0_MAC_RST] = 16, 415 [EN7581_DUAL_HSI1_MAC_RST] = 17, 416 [EN7581_HSI_MAC_RST] = 18, 417 [EN7581_WDMA_RST] = 19, 418 [EN7581_WOE0_RST] = 20, 419 [EN7581_WOE1_RST] = 21, 420 [EN7581_HSDMA_RST] = 22, 421 [EN7581_TDMA_RST] = 24, 422 [EN7581_EMMC_RST] = 25, 423 [EN7581_SOE_RST] = 26, 424 [EN7581_PCIE2_RST] = 27, 425 [EN7581_XFP_MAC_RST] = 28, 426 [EN7581_USB_HOST_P1_RST] = 29, 427 [EN7581_USB_HOST_P1_U3_PHY_RST] = 30, 428 /* RST_CTRL1 */ 429 [EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, 430 [EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1, 431 [EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2, 432 [EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, 433 [EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6, 434 [EN7581_TIMER_RST] = RST_NR_PER_BANK + 8, 435 [EN7581_PCM1_RST] = RST_NR_PER_BANK + 11, 436 [EN7581_UART_RST] = RST_NR_PER_BANK + 12, 437 [EN7581_GPIO_RST] = RST_NR_PER_BANK + 13, 438 [EN7581_GDMA_RST] = RST_NR_PER_BANK + 14, 439 [EN7581_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, 440 [EN7581_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, 441 [EN7581_SFC_RST] = RST_NR_PER_BANK + 18, 442 [EN7581_UART2_RST] = RST_NR_PER_BANK + 19, 443 [EN7581_GDMP_RST] = RST_NR_PER_BANK + 20, 444 [EN7581_FE_RST] = RST_NR_PER_BANK + 21, 445 [EN7581_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, 446 [EN7581_GSW_RST] = RST_NR_PER_BANK + 23, 447 [EN7581_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, 448 [EN7581_PCIE0_RST] = RST_NR_PER_BANK + 26, 449 [EN7581_PCIE1_RST] = RST_NR_PER_BANK + 27, 450 [EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28, 451 [EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29, 452 [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31, 453 }; 454 455 static const u16 en751221_rst_map[] = { 456 /* RST_CTRL2 */ 457 [EN751221_XPON_PHY_RST] = 0, 458 [EN751221_GFAST_RST] = 1, 459 [EN751221_CPU_TIMER2_RST] = 2, 460 [EN751221_UART3_RST] = 3, 461 [EN751221_UART4_RST] = 4, 462 [EN751221_UART5_RST] = 5, 463 [EN751221_I2C2_RST] = 6, 464 [EN751221_XSI_MAC_RST] = 7, 465 [EN751221_XSI_PHY_RST] = 8, 466 467 /* RST_CTRL1 */ 468 [EN751221_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, 469 [EN751221_FE_QDMA1_RST] = RST_NR_PER_BANK + 1, 470 [EN751221_FE_QDMA2_RST] = RST_NR_PER_BANK + 2, 471 [EN751221_FE_UNZIP_RST] = RST_NR_PER_BANK + 3, 472 [EN751221_PCM2_RST] = RST_NR_PER_BANK + 4, 473 [EN751221_PTM_MAC_RST] = RST_NR_PER_BANK + 5, 474 [EN751221_CRYPTO_RST] = RST_NR_PER_BANK + 6, 475 [EN751221_SAR_RST] = RST_NR_PER_BANK + 7, 476 [EN751221_TIMER_RST] = RST_NR_PER_BANK + 8, 477 [EN751221_INTC_RST] = RST_NR_PER_BANK + 9, 478 [EN751221_BONDING_RST] = RST_NR_PER_BANK + 10, 479 [EN751221_PCM1_RST] = RST_NR_PER_BANK + 11, 480 [EN751221_UART_RST] = RST_NR_PER_BANK + 12, 481 [EN751221_GPIO_RST] = RST_NR_PER_BANK + 13, 482 [EN751221_GDMA_RST] = RST_NR_PER_BANK + 14, 483 [EN751221_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, 484 [EN751221_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, 485 [EN751221_SFC_RST] = RST_NR_PER_BANK + 18, 486 [EN751221_UART2_RST] = RST_NR_PER_BANK + 19, 487 [EN751221_GDMP_RST] = RST_NR_PER_BANK + 20, 488 [EN751221_FE_RST] = RST_NR_PER_BANK + 21, 489 [EN751221_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, 490 [EN751221_GSW_RST] = RST_NR_PER_BANK + 23, 491 [EN751221_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, 492 [EN751221_PCIE0_RST] = RST_NR_PER_BANK + 26, 493 [EN751221_PCIE1_RST] = RST_NR_PER_BANK + 27, 494 [EN751221_CPU_TIMER_RST] = RST_NR_PER_BANK + 28, 495 [EN751221_PCIE_HB_RST] = RST_NR_PER_BANK + 29, 496 [EN751221_SIMIF_RST] = RST_NR_PER_BANK + 30, 497 [EN751221_XPON_MAC_RST] = RST_NR_PER_BANK + 31, 498 499 /* RST_DMT */ 500 [EN751221_DMT_RST] = 2 * RST_NR_PER_BANK + 0, 501 502 /* RST_USB */ 503 [EN751221_USB_PHY_P0_RST] = 3 * RST_NR_PER_BANK + 6, 504 [EN751221_USB_PHY_P1_RST] = 3 * RST_NR_PER_BANK + 7, 505 }; 506 507 static int en7581_reset_register(struct device *dev, void __iomem *base, 508 const u16 *rst_map, int nr_resets, 509 const u16 *rst_reg_ofs); 510 511 static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val) 512 { 513 if (!desc->base_bits) 514 return desc->base_value; 515 516 val >>= desc->base_shift; 517 val &= (1 << desc->base_bits) - 1; 518 519 if (val >= desc->n_base_values) 520 return 0; 521 522 return desc->base_values[val]; 523 } 524 525 static u32 en7523_get_div(const struct en_clk_desc *desc, u32 val) 526 { 527 if (!desc->div_bits) 528 return 1; 529 530 val >>= desc->div_shift; 531 val &= (1 << desc->div_bits) - 1; 532 533 if (!val && desc->div_val0) 534 return desc->div_val0; 535 536 return (val + desc->div_offset) * desc->div_step; 537 } 538 539 static int en7523_pci_is_enabled(struct clk_hw *hw) 540 { 541 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 542 543 return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); 544 } 545 546 static int en7523_pci_prepare(struct clk_hw *hw) 547 { 548 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 549 void __iomem *np_base = cg->base; 550 u32 val, mask; 551 552 /* Need to pull device low before reset */ 553 val = readl(np_base + REG_PCI_CONTROL); 554 val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); 555 writel(val, np_base + REG_PCI_CONTROL); 556 usleep_range(1000, 2000); 557 558 /* Enable PCIe port 1 */ 559 val |= REG_PCI_CONTROL_REFCLK_EN1; 560 writel(val, np_base + REG_PCI_CONTROL); 561 usleep_range(1000, 2000); 562 563 /* Reset to default */ 564 val = readl(np_base + REG_RESET_CONTROL1); 565 mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | 566 REG_RESET_CONTROL_PCIEHB; 567 writel(val & ~mask, np_base + REG_RESET_CONTROL1); 568 usleep_range(1000, 2000); 569 writel(val | mask, np_base + REG_RESET_CONTROL1); 570 msleep(100); 571 writel(val & ~mask, np_base + REG_RESET_CONTROL1); 572 usleep_range(5000, 10000); 573 574 /* Release device */ 575 mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; 576 val = readl(np_base + REG_PCI_CONTROL); 577 writel(val & ~mask, np_base + REG_PCI_CONTROL); 578 usleep_range(1000, 2000); 579 writel(val | mask, np_base + REG_PCI_CONTROL); 580 msleep(250); 581 582 return 0; 583 } 584 585 static void en7523_pci_unprepare(struct clk_hw *hw) 586 { 587 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 588 void __iomem *np_base = cg->base; 589 u32 val; 590 591 val = readl(np_base + REG_PCI_CONTROL); 592 val &= ~REG_PCI_CONTROL_REFCLK_EN1; 593 writel(val, np_base + REG_PCI_CONTROL); 594 } 595 596 static struct clk_hw *en7523_register_pcie_clk(struct device *dev, 597 void __iomem *np_base) 598 { 599 const struct en_clk_soc_data *soc_data = device_get_match_data(dev); 600 struct clk_init_data init = { 601 .name = "pcie", 602 .ops = &soc_data->pcie_ops, 603 }; 604 struct en_clk_gate *cg; 605 606 cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); 607 if (!cg) 608 return NULL; 609 610 cg->base = np_base; 611 cg->hw.init = &init; 612 613 if (init.ops->unprepare) 614 init.ops->unprepare(&cg->hw); 615 616 if (clk_hw_register(dev, &cg->hw)) 617 return NULL; 618 619 return &cg->hw; 620 } 621 622 static int en7581_pci_is_enabled(struct clk_hw *hw) 623 { 624 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 625 u32 val, mask; 626 627 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; 628 val = readl(cg->base + REG_PCI_CONTROL); 629 return (val & mask) == mask; 630 } 631 632 static int en7581_pci_enable(struct clk_hw *hw) 633 { 634 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 635 void __iomem *np_base = cg->base; 636 u32 val, mask; 637 638 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | 639 REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | 640 REG_PCI_CONTROL_PERSTOUT; 641 val = readl(np_base + REG_PCI_CONTROL); 642 writel(val | mask, np_base + REG_PCI_CONTROL); 643 644 return 0; 645 } 646 647 static void en7581_pci_disable(struct clk_hw *hw) 648 { 649 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 650 void __iomem *np_base = cg->base; 651 u32 val, mask; 652 653 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | 654 REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | 655 REG_PCI_CONTROL_PERSTOUT; 656 val = readl(np_base + REG_PCI_CONTROL); 657 writel(val & ~mask, np_base + REG_PCI_CONTROL); 658 usleep_range(1000, 2000); 659 } 660 661 static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, 662 void __iomem *base, void __iomem *np_base) 663 { 664 struct clk_hw *hw; 665 u32 rate; 666 int i; 667 668 for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { 669 const struct en_clk_desc *desc = &en7523_base_clks[i]; 670 u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg; 671 u32 val = readl(base + desc->base_reg); 672 673 rate = en7523_get_base_rate(desc, val); 674 val = readl(base + reg); 675 rate /= en7523_get_div(desc, val); 676 677 hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); 678 if (IS_ERR(hw)) { 679 pr_err("Failed to register clk %s: %ld\n", 680 desc->name, PTR_ERR(hw)); 681 continue; 682 } 683 684 clk_data->hws[desc->id] = hw; 685 } 686 687 hw = en7523_register_pcie_clk(dev, np_base); 688 clk_data->hws[EN7523_CLK_PCIE] = hw; 689 } 690 691 static int en7523_clk_hw_init(struct platform_device *pdev, 692 struct clk_hw_onecell_data *clk_data) 693 { 694 void __iomem *base, *np_base; 695 696 base = devm_platform_ioremap_resource(pdev, 0); 697 if (IS_ERR(base)) 698 return PTR_ERR(base); 699 700 np_base = devm_platform_ioremap_resource(pdev, 1); 701 if (IS_ERR(np_base)) 702 return PTR_ERR(np_base); 703 704 en7523_register_clocks(&pdev->dev, clk_data, base, np_base); 705 706 return en7581_reset_register(&pdev->dev, np_base, en7523_rst_map, 707 ARRAY_SIZE(en7523_rst_map), 708 en7581_rst_ofs); 709 } 710 711 static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, 712 struct regmap *map, void __iomem *base) 713 { 714 struct clk_hw *hw; 715 u32 rate; 716 int i; 717 718 for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) { 719 const struct en_clk_desc *desc = &en7581_base_clks[i]; 720 u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; 721 int err; 722 723 err = regmap_read(map, desc->base_reg, &val); 724 if (err) { 725 pr_err("Failed reading fixed clk rate %s: %d\n", 726 desc->name, err); 727 continue; 728 } 729 rate = en7523_get_base_rate(desc, val); 730 731 err = regmap_read(map, reg, &val); 732 if (err) { 733 pr_err("Failed reading fixed clk div %s: %d\n", 734 desc->name, err); 735 continue; 736 } 737 rate /= en7523_get_div(desc, val); 738 739 hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); 740 if (IS_ERR(hw)) { 741 pr_err("Failed to register clk %s: %ld\n", 742 desc->name, PTR_ERR(hw)); 743 continue; 744 } 745 746 clk_data->hws[desc->id] = hw; 747 } 748 749 hw = en7523_register_pcie_clk(dev, base); 750 clk_data->hws[EN7523_CLK_PCIE] = hw; 751 } 752 753 static int en7523_reset_update(struct reset_controller_dev *rcdev, 754 unsigned long id, bool assert) 755 { 756 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 757 void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; 758 u32 val; 759 760 val = readl(addr); 761 if (assert) 762 val |= BIT(id % RST_NR_PER_BANK); 763 else 764 val &= ~BIT(id % RST_NR_PER_BANK); 765 writel(val, addr); 766 767 return 0; 768 } 769 770 static int en7523_reset_assert(struct reset_controller_dev *rcdev, 771 unsigned long id) 772 { 773 return en7523_reset_update(rcdev, id, true); 774 } 775 776 static int en7523_reset_deassert(struct reset_controller_dev *rcdev, 777 unsigned long id) 778 { 779 return en7523_reset_update(rcdev, id, false); 780 } 781 782 static int en7523_reset_status(struct reset_controller_dev *rcdev, 783 unsigned long id) 784 { 785 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 786 void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; 787 788 return !!(readl(addr) & BIT(id % RST_NR_PER_BANK)); 789 } 790 791 static int en7523_reset_xlate(struct reset_controller_dev *rcdev, 792 const struct of_phandle_args *reset_spec) 793 { 794 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 795 796 if (reset_spec->args[0] >= rcdev->nr_resets) 797 return -EINVAL; 798 799 return rst_data->idx_map[reset_spec->args[0]]; 800 } 801 802 static const struct reset_control_ops en7581_reset_ops = { 803 .assert = en7523_reset_assert, 804 .deassert = en7523_reset_deassert, 805 .status = en7523_reset_status, 806 }; 807 808 static int en7581_reset_register(struct device *dev, void __iomem *base, 809 const u16 *rst_map, int nr_resets, 810 const u16 *rst_reg_ofs) 811 { 812 struct en_rst_data *rst_data; 813 814 rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); 815 if (!rst_data) 816 return -ENOMEM; 817 818 rst_data->bank_ofs = rst_reg_ofs; 819 rst_data->idx_map = rst_map; 820 rst_data->base = base; 821 822 rst_data->rcdev.nr_resets = nr_resets; 823 rst_data->rcdev.of_xlate = en7523_reset_xlate; 824 rst_data->rcdev.ops = &en7581_reset_ops; 825 rst_data->rcdev.of_node = dev->of_node; 826 rst_data->rcdev.of_reset_n_cells = 1; 827 rst_data->rcdev.owner = THIS_MODULE; 828 rst_data->rcdev.dev = dev; 829 830 return devm_reset_controller_register(dev, &rst_data->rcdev); 831 } 832 833 static int en7581_clk_hw_init(struct platform_device *pdev, 834 struct clk_hw_onecell_data *clk_data) 835 { 836 struct regmap *map; 837 void __iomem *base; 838 u32 val; 839 840 map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); 841 if (IS_ERR(map)) 842 return PTR_ERR(map); 843 844 base = devm_platform_ioremap_resource(pdev, 0); 845 if (IS_ERR(base)) 846 return PTR_ERR(base); 847 848 en7581_register_clocks(&pdev->dev, clk_data, map, base); 849 850 val = readl(base + REG_NP_SCU_SSTR); 851 val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); 852 writel(val, base + REG_NP_SCU_SSTR); 853 val = readl(base + REG_NP_SCU_PCIC); 854 writel(val | 3, base + REG_NP_SCU_PCIC); 855 856 return en7581_reset_register(&pdev->dev, base, en7581_rst_map, 857 ARRAY_SIZE(en7581_rst_map), 858 en7581_rst_ofs); 859 } 860 861 static enum en_hir get_hw_id(void __iomem *np_base) 862 { 863 u32 val = FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR)); 864 865 if (val < HIR_MAX) 866 return (enum en_hir)val; 867 868 pr_warn("Unable to determine EcoNet SoC\n"); 869 870 return HIR_UNKNOWN; 871 } 872 873 static void en751221_try_register_clk(struct device *dev, int key, 874 struct clk_hw_onecell_data *clk_data, 875 const char *name, u32 rate) 876 { 877 struct clk_hw *hw; 878 879 if (WARN_ON_ONCE(key >= EN751221_MAX_CLKS)) 880 return; 881 882 hw = clk_hw_register_fixed_rate(dev, name, NULL, 0, rate); 883 if (IS_ERR(hw)) 884 pr_err("Failed to register clk %s: %pe\n", name, hw); 885 else 886 clk_data->hws[key] = hw; 887 } 888 889 static void en751221_register_clocks(struct device *dev, 890 struct clk_hw_onecell_data *clk_data, 891 struct regmap *map, void __iomem *np_base) 892 { 893 enum en_hir hid = get_hw_id(np_base); 894 struct clk_hw *hw; 895 u32 rate; 896 u32 div; 897 int err; 898 899 /* PCI */ 900 hw = en7523_register_pcie_clk(dev, np_base); 901 clk_data->hws[EN751221_CLK_PCIE] = hw; 902 903 /* SPI */ 904 rate = EN751221_SPI_BASE; 905 if (hid == HIR_EN7526C) 906 rate = EN751221_SPI_BASE_EN7526C; 907 908 err = regmap_read(map, EN751221_REG_SPI_DIV, &div); 909 if (err) { 910 pr_err("Failed reading fixed clk div %s: %d\n", 911 "spi", err); 912 } else { 913 div = FIELD_GET(EN751221_REG_SPI_DIV_MASK, div) * 2; 914 if (!div) 915 div = EN751221_SPI_DIV_DEFAULT; 916 917 en751221_try_register_clk(dev, EN751221_CLK_SPI, clk_data, 918 "spi", rate / div); 919 } 920 921 /* BUS */ 922 rate = FIELD_GET(EN751221_REG_BUS_MASK, 923 readl(np_base + EN751221_REG_BUS)); 924 rate *= 1000000; 925 en751221_try_register_clk(dev, EN751221_CLK_BUS, clk_data, "bus", 926 rate); 927 928 /* CPU */ 929 en751221_try_register_clk(dev, EN751221_CLK_CPU, clk_data, "cpu", 930 rate * 4); 931 932 /* GSW */ 933 rate = FIELD_GET(EN751221_REG_SSR3_GSW_MASK, 934 readl(np_base + EN751221_REG_SSR3)); 935 en751221_try_register_clk(dev, EN751221_CLK_GSW, clk_data, "gsw", 936 gsw751221_base[rate]); 937 } 938 939 static int en751221_clk_hw_init(struct platform_device *pdev, 940 struct clk_hw_onecell_data *clk_data) 941 { 942 struct regmap *map; 943 void __iomem *base; 944 945 map = syscon_regmap_lookup_by_compatible("econet,en751221-chip-scu"); 946 if (IS_ERR(map)) 947 return PTR_ERR(map); 948 949 base = devm_platform_ioremap_resource(pdev, 0); 950 if (IS_ERR(base)) 951 return PTR_ERR(base); 952 953 en751221_register_clocks(&pdev->dev, clk_data, map, base); 954 955 return en7581_reset_register(&pdev->dev, base, en751221_rst_map, 956 ARRAY_SIZE(en751221_rst_map), 957 en751221_rst_ofs); 958 } 959 960 static int en7523_clk_probe(struct platform_device *pdev) 961 { 962 struct device_node *node = pdev->dev.of_node; 963 const struct en_clk_soc_data *soc_data; 964 struct clk_hw_onecell_data *clk_data; 965 int r; 966 967 soc_data = device_get_match_data(&pdev->dev); 968 969 clk_data = devm_kzalloc(&pdev->dev, 970 struct_size(clk_data, hws, soc_data->num_clocks), 971 GFP_KERNEL); 972 if (!clk_data) 973 return -ENOMEM; 974 975 clk_data->num = soc_data->num_clocks; 976 r = soc_data->hw_init(pdev, clk_data); 977 if (r) 978 return r; 979 980 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 981 } 982 983 static const struct en_clk_soc_data en7523_data = { 984 .num_clocks = ARRAY_SIZE(en7523_base_clks) + 1, 985 .pcie_ops = { 986 .is_enabled = en7523_pci_is_enabled, 987 .prepare = en7523_pci_prepare, 988 .unprepare = en7523_pci_unprepare, 989 }, 990 .hw_init = en7523_clk_hw_init, 991 }; 992 993 static const struct en_clk_soc_data en7581_data = { 994 /* We increment num_clocks by 1 to account for additional PCIe clock */ 995 .num_clocks = ARRAY_SIZE(en7581_base_clks) + 1, 996 .pcie_ops = { 997 .is_enabled = en7581_pci_is_enabled, 998 .enable = en7581_pci_enable, 999 .disable = en7581_pci_disable, 1000 }, 1001 .hw_init = en7581_clk_hw_init, 1002 }; 1003 1004 static const struct en_clk_soc_data en751221_data = { 1005 .num_clocks = EN751221_MAX_CLKS, 1006 .pcie_ops = { 1007 .is_enabled = en7523_pci_is_enabled, 1008 .prepare = en7523_pci_prepare, 1009 .unprepare = en7523_pci_unprepare, 1010 }, 1011 .hw_init = en751221_clk_hw_init, 1012 }; 1013 1014 static const struct of_device_id of_match_clk_en7523[] = { 1015 { .compatible = "airoha,en7523-scu", .data = &en7523_data }, 1016 { .compatible = "airoha,en7581-scu", .data = &en7581_data }, 1017 { .compatible = "econet,en751221-scu", .data = &en751221_data }, 1018 { /* sentinel */ } 1019 }; 1020 1021 static struct platform_driver clk_en7523_drv = { 1022 .probe = en7523_clk_probe, 1023 .driver = { 1024 .name = "clk-en7523", 1025 .of_match_table = of_match_clk_en7523, 1026 .suppress_bind_attrs = true, 1027 }, 1028 }; 1029 1030 static int __init clk_en7523_init(void) 1031 { 1032 return platform_driver_register(&clk_en7523_drv); 1033 } 1034 1035 arch_initcall(clk_en7523_init); 1036