1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/bitfield.h> 4 #include <linux/delay.h> 5 #include <linux/clk-provider.h> 6 #include <linux/io.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/platform_device.h> 9 #include <linux/property.h> 10 #include <linux/regmap.h> 11 #include <linux/reset-controller.h> 12 #include <dt-bindings/clock/en7523-clk.h> 13 #include <dt-bindings/reset/airoha,en7523-reset.h> 14 #include <dt-bindings/reset/airoha,en7581-reset.h> 15 #include <dt-bindings/clock/econet,en751221-scu.h> 16 #include <dt-bindings/reset/econet,en751221-scu.h> 17 18 #define RST_NR_PER_BANK 32 19 20 #define REG_PCI_CONTROL 0x88 21 #define REG_PCI_CONTROL_PERSTOUT BIT(29) 22 #define REG_PCI_CONTROL_PERSTOUT1 BIT(26) 23 #define REG_PCI_CONTROL_REFCLK_EN0 BIT(23) 24 #define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) 25 #define REG_PCI_CONTROL_PERSTOUT2 BIT(16) 26 #define REG_GSW_CLK_DIV_SEL 0x1b4 27 #define REG_EMI_CLK_DIV_SEL 0x1b8 28 #define REG_BUS_CLK_DIV_SEL 0x1bc 29 #define REG_SPI_CLK_DIV_SEL 0x1c4 30 #define REG_SPI_CLK_FREQ_SEL 0x1c8 31 #define REG_NPU_CLK_DIV_SEL 0x1fc 32 #define REG_CRYPTO_CLKSRC 0x200 33 #define REG_RESET_CONTROL2 0x830 34 #define REG_RESET2_CONTROL_PCIE2 BIT(27) 35 #define REG_RESET_CONTROL1 0x834 36 #define REG_RESET_CONTROL_PCIEHB BIT(29) 37 #define REG_RESET_CONTROL_PCIE1 BIT(27) 38 #define REG_RESET_CONTROL_PCIE2 BIT(26) 39 #define REG_HIR 0x064 40 #define REG_HIR_MASK GENMASK(31, 16) 41 /* EN7581 */ 42 #define REG_NP_SCU_PCIC 0x88 43 #define REG_NP_SCU_SSTR 0x9c 44 #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) 45 #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) 46 #define REG_CRYPTO_CLKSRC2 0x20c 47 /* EN751221 */ 48 #define EN751221_REG_SPI_DIV 0x0cc 49 #define EN751221_REG_SPI_DIV_MASK GENMASK(31, 8) 50 #define EN751221_SPI_BASE 500000000 51 #define EN751221_SPI_BASE_EN7526C 400000000 52 #define EN751221_SPI_DIV_DEFAULT 40 53 #define EN751221_REG_BUS 0x284 54 #define EN751221_REG_BUS_MASK GENMASK(21, 12) 55 #define EN751221_REG_SSR3 0x094 56 #define EN751221_REG_SSR3_GSW_MASK GENMASK(9, 8) 57 58 #define REG_RST_CTRL2 0x830 59 #define REG_RST_CTRL1 0x834 60 #define REG_PCIE_HB_RST BIT(29) 61 #define EN751221_REG_RST_DMT 0x84 62 #define EN751221_REG_RST_USB 0xec 63 64 #define EN751221_MAX_CLKS 5 65 66 enum en_hir { 67 HIR_UNKNOWN = -1, 68 HIR_TC3169 = 0, 69 HIR_TC3182 = 1, 70 HIR_RT65168 = 2, 71 HIR_RT63165 = 3, 72 HIR_RT63365 = 4, 73 HIR_MT751020 = 5, 74 HIR_MT7505 = 6, 75 HIR_EN751221 = 7, 76 HIR_EN7526C = 8, 77 HIR_EN751627 = 9, 78 HIR_EN7580 = 10, 79 HIR_EN7528 = 11, 80 HIR_EN7523 = 12, 81 HIR_EN7581 = 13, 82 HIR_MAX = 14, 83 }; 84 85 struct en_clk_desc { 86 int id; 87 const char *name; 88 u32 base_reg; 89 u8 base_bits; 90 u8 base_shift; 91 union { 92 const unsigned int *base_values; 93 unsigned int base_value; 94 }; 95 size_t n_base_values; 96 97 u16 div_reg; 98 u8 div_bits; 99 u8 div_shift; 100 u16 div_val0; 101 u8 div_step; 102 u8 div_offset; 103 }; 104 105 struct en_clk_gate { 106 void __iomem *base; 107 struct clk_hw hw; 108 }; 109 110 struct en_rst_data { 111 const u16 *bank_ofs; 112 const u16 *idx_map; 113 void __iomem *base; 114 struct reset_controller_dev rcdev; 115 }; 116 117 struct en_clk_soc_data { 118 u32 num_clocks; 119 const struct clk_ops pcie_ops; 120 int (*hw_init)(struct platform_device *pdev, 121 struct clk_hw_onecell_data *clk_data); 122 }; 123 124 static const u32 gsw_base[] = { 400000000, 500000000 }; 125 static const u32 emi_base[] = { 333000000, 400000000 }; 126 static const u32 bus_base[] = { 500000000, 540000000 }; 127 static const u32 slic_base[] = { 100000000, 3125000 }; 128 static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; 129 /* EN7581 */ 130 static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 }; 131 static const u32 bus7581_base[] = { 600000000, 540000000 }; 132 static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 }; 133 static const u32 crypto_base[] = { 540000000, 480000000 }; 134 static const u32 emmc7581_base[] = { 200000000, 150000000 }; 135 /* EN751221 */ 136 static const u32 gsw751221_base[] = { 500000000, 250000000, 400000000, 200000000 }; 137 138 static const struct en_clk_desc en7523_base_clks[] = { 139 { 140 .id = EN7523_CLK_GSW, 141 .name = "gsw", 142 143 .base_reg = REG_GSW_CLK_DIV_SEL, 144 .base_bits = 1, 145 .base_shift = 8, 146 .base_values = gsw_base, 147 .n_base_values = ARRAY_SIZE(gsw_base), 148 149 .div_bits = 3, 150 .div_shift = 0, 151 .div_step = 1, 152 .div_offset = 1, 153 }, { 154 .id = EN7523_CLK_EMI, 155 .name = "emi", 156 157 .base_reg = REG_EMI_CLK_DIV_SEL, 158 .base_bits = 1, 159 .base_shift = 8, 160 .base_values = emi_base, 161 .n_base_values = ARRAY_SIZE(emi_base), 162 163 .div_bits = 3, 164 .div_shift = 0, 165 .div_step = 1, 166 .div_offset = 1, 167 }, { 168 .id = EN7523_CLK_BUS, 169 .name = "bus", 170 171 .base_reg = REG_BUS_CLK_DIV_SEL, 172 .base_bits = 1, 173 .base_shift = 8, 174 .base_values = bus_base, 175 .n_base_values = ARRAY_SIZE(bus_base), 176 177 .div_bits = 3, 178 .div_shift = 0, 179 .div_step = 1, 180 .div_offset = 1, 181 }, { 182 .id = EN7523_CLK_SLIC, 183 .name = "slic", 184 185 .base_reg = REG_SPI_CLK_FREQ_SEL, 186 .base_bits = 1, 187 .base_shift = 0, 188 .base_values = slic_base, 189 .n_base_values = ARRAY_SIZE(slic_base), 190 191 .div_reg = REG_SPI_CLK_DIV_SEL, 192 .div_bits = 5, 193 .div_shift = 24, 194 .div_val0 = 20, 195 .div_step = 2, 196 }, { 197 .id = EN7523_CLK_SPI, 198 .name = "spi", 199 200 .base_reg = REG_SPI_CLK_DIV_SEL, 201 202 .base_value = 400000000, 203 204 .div_bits = 5, 205 .div_shift = 8, 206 .div_val0 = 40, 207 .div_step = 2, 208 }, { 209 .id = EN7523_CLK_NPU, 210 .name = "npu", 211 212 .base_reg = REG_NPU_CLK_DIV_SEL, 213 .base_bits = 2, 214 .base_shift = 8, 215 .base_values = npu_base, 216 .n_base_values = ARRAY_SIZE(npu_base), 217 218 .div_bits = 3, 219 .div_shift = 0, 220 .div_step = 1, 221 .div_offset = 1, 222 }, { 223 .id = EN7523_CLK_CRYPTO, 224 .name = "crypto", 225 226 .base_reg = REG_CRYPTO_CLKSRC, 227 .base_bits = 1, 228 .base_shift = 0, 229 .base_values = emi_base, 230 .n_base_values = ARRAY_SIZE(emi_base), 231 } 232 }; 233 234 static const struct en_clk_desc en7581_base_clks[] = { 235 { 236 .id = EN7523_CLK_GSW, 237 .name = "gsw", 238 239 .base_reg = REG_GSW_CLK_DIV_SEL, 240 .base_bits = 1, 241 .base_shift = 8, 242 .base_values = gsw_base, 243 .n_base_values = ARRAY_SIZE(gsw_base), 244 245 .div_bits = 3, 246 .div_shift = 0, 247 .div_step = 1, 248 .div_offset = 1, 249 }, { 250 .id = EN7523_CLK_EMI, 251 .name = "emi", 252 253 .base_reg = REG_EMI_CLK_DIV_SEL, 254 .base_bits = 2, 255 .base_shift = 8, 256 .base_values = emi7581_base, 257 .n_base_values = ARRAY_SIZE(emi7581_base), 258 259 .div_bits = 3, 260 .div_shift = 0, 261 .div_step = 1, 262 .div_offset = 1, 263 }, { 264 .id = EN7523_CLK_BUS, 265 .name = "bus", 266 267 .base_reg = REG_BUS_CLK_DIV_SEL, 268 .base_bits = 1, 269 .base_shift = 8, 270 .base_values = bus7581_base, 271 .n_base_values = ARRAY_SIZE(bus7581_base), 272 273 .div_bits = 3, 274 .div_shift = 0, 275 .div_step = 1, 276 .div_offset = 1, 277 }, { 278 .id = EN7523_CLK_SLIC, 279 .name = "slic", 280 281 .base_reg = REG_SPI_CLK_FREQ_SEL, 282 .base_bits = 1, 283 .base_shift = 0, 284 .base_values = slic_base, 285 .n_base_values = ARRAY_SIZE(slic_base), 286 287 .div_reg = REG_SPI_CLK_DIV_SEL, 288 .div_bits = 5, 289 .div_shift = 24, 290 .div_val0 = 20, 291 .div_step = 2, 292 }, { 293 .id = EN7523_CLK_SPI, 294 .name = "spi", 295 296 .base_reg = REG_SPI_CLK_DIV_SEL, 297 298 .base_value = 400000000, 299 300 .div_bits = 5, 301 .div_shift = 8, 302 .div_val0 = 40, 303 .div_step = 2, 304 }, { 305 .id = EN7523_CLK_NPU, 306 .name = "npu", 307 308 .base_reg = REG_NPU_CLK_DIV_SEL, 309 .base_bits = 2, 310 .base_shift = 8, 311 .base_values = npu7581_base, 312 .n_base_values = ARRAY_SIZE(npu7581_base), 313 314 .div_bits = 3, 315 .div_shift = 0, 316 .div_step = 1, 317 .div_offset = 1, 318 }, { 319 .id = EN7523_CLK_CRYPTO, 320 .name = "crypto", 321 322 .base_reg = REG_CRYPTO_CLKSRC2, 323 .base_bits = 1, 324 .base_shift = 0, 325 .base_values = crypto_base, 326 .n_base_values = ARRAY_SIZE(crypto_base), 327 }, { 328 .id = EN7581_CLK_EMMC, 329 .name = "emmc", 330 331 .base_reg = REG_CRYPTO_CLKSRC2, 332 .base_bits = 1, 333 .base_shift = 12, 334 .base_values = emmc7581_base, 335 .n_base_values = ARRAY_SIZE(emmc7581_base), 336 } 337 }; 338 339 static const u16 en7581_rst_ofs[] = { 340 REG_RST_CTRL2, 341 REG_RST_CTRL1, 342 REG_NP_SCU_PCIC, 343 }; 344 345 static const u16 en751221_rst_ofs[] = { 346 REG_RST_CTRL2, 347 REG_RST_CTRL1, 348 EN751221_REG_RST_DMT, 349 EN751221_REG_RST_USB, 350 }; 351 352 static const u16 en7523_rst_map[] = { 353 /* RST_CTRL2 */ 354 [EN7523_XPON_PHY_RST] = 0, 355 [EN7523_XSI_MAC_RST] = 7, 356 [EN7523_XSI_PHY_RST] = 8, 357 [EN7523_NPU_RST] = 9, 358 [EN7523_I2S_RST] = 10, 359 [EN7523_TRNG_RST] = 11, 360 [EN7523_TRNG_MSTART_RST] = 12, 361 [EN7523_DUAL_HSI0_RST] = 13, 362 [EN7523_DUAL_HSI1_RST] = 14, 363 [EN7523_HSI_RST] = 15, 364 [EN7523_DUAL_HSI0_MAC_RST] = 16, 365 [EN7523_DUAL_HSI1_MAC_RST] = 17, 366 [EN7523_HSI_MAC_RST] = 18, 367 [EN7523_WDMA_RST] = 19, 368 [EN7523_WOE0_RST] = 20, 369 [EN7523_WOE1_RST] = 21, 370 [EN7523_HSDMA_RST] = 22, 371 [EN7523_I2C2RBUS_RST] = 23, 372 [EN7523_TDMA_RST] = 24, 373 /* RST_CTRL1 */ 374 [EN7523_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, 375 [EN7523_FE_PDMA_RST] = RST_NR_PER_BANK + 1, 376 [EN7523_FE_QDMA_RST] = RST_NR_PER_BANK + 2, 377 [EN7523_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, 378 [EN7523_CRYPTO_RST] = RST_NR_PER_BANK + 6, 379 [EN7523_TIMER_RST] = RST_NR_PER_BANK + 8, 380 [EN7523_PCM1_RST] = RST_NR_PER_BANK + 11, 381 [EN7523_UART_RST] = RST_NR_PER_BANK + 12, 382 [EN7523_GPIO_RST] = RST_NR_PER_BANK + 13, 383 [EN7523_GDMA_RST] = RST_NR_PER_BANK + 14, 384 [EN7523_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, 385 [EN7523_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, 386 [EN7523_SFC_RST] = RST_NR_PER_BANK + 18, 387 [EN7523_UART2_RST] = RST_NR_PER_BANK + 19, 388 [EN7523_GDMP_RST] = RST_NR_PER_BANK + 20, 389 [EN7523_FE_RST] = RST_NR_PER_BANK + 21, 390 [EN7523_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, 391 [EN7523_GSW_RST] = RST_NR_PER_BANK + 23, 392 [EN7523_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, 393 [EN7523_PCIE0_RST] = RST_NR_PER_BANK + 26, 394 [EN7523_PCIE1_RST] = RST_NR_PER_BANK + 27, 395 [EN7523_PCIE_HB_RST] = RST_NR_PER_BANK + 29, 396 [EN7523_XPON_MAC_RST] = RST_NR_PER_BANK + 31, 397 }; 398 399 static const u16 en7581_rst_map[] = { 400 /* RST_CTRL2 */ 401 [EN7581_XPON_PHY_RST] = 0, 402 [EN7581_CPU_TIMER2_RST] = 2, 403 [EN7581_HSUART_RST] = 3, 404 [EN7581_UART4_RST] = 4, 405 [EN7581_UART5_RST] = 5, 406 [EN7581_I2C2_RST] = 6, 407 [EN7581_XSI_MAC_RST] = 7, 408 [EN7581_XSI_PHY_RST] = 8, 409 [EN7581_NPU_RST] = 9, 410 [EN7581_I2S_RST] = 10, 411 [EN7581_TRNG_RST] = 11, 412 [EN7581_TRNG_MSTART_RST] = 12, 413 [EN7581_DUAL_HSI0_RST] = 13, 414 [EN7581_DUAL_HSI1_RST] = 14, 415 [EN7581_HSI_RST] = 15, 416 [EN7581_DUAL_HSI0_MAC_RST] = 16, 417 [EN7581_DUAL_HSI1_MAC_RST] = 17, 418 [EN7581_HSI_MAC_RST] = 18, 419 [EN7581_WDMA_RST] = 19, 420 [EN7581_WOE0_RST] = 20, 421 [EN7581_WOE1_RST] = 21, 422 [EN7581_HSDMA_RST] = 22, 423 [EN7581_TDMA_RST] = 24, 424 [EN7581_EMMC_RST] = 25, 425 [EN7581_SOE_RST] = 26, 426 [EN7581_PCIE2_RST] = 27, 427 [EN7581_XFP_MAC_RST] = 28, 428 [EN7581_USB_HOST_P1_RST] = 29, 429 [EN7581_USB_HOST_P1_U3_PHY_RST] = 30, 430 /* RST_CTRL1 */ 431 [EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, 432 [EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1, 433 [EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2, 434 [EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, 435 [EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6, 436 [EN7581_TIMER_RST] = RST_NR_PER_BANK + 8, 437 [EN7581_PCM1_RST] = RST_NR_PER_BANK + 11, 438 [EN7581_UART_RST] = RST_NR_PER_BANK + 12, 439 [EN7581_GPIO_RST] = RST_NR_PER_BANK + 13, 440 [EN7581_GDMA_RST] = RST_NR_PER_BANK + 14, 441 [EN7581_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, 442 [EN7581_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, 443 [EN7581_SFC_RST] = RST_NR_PER_BANK + 18, 444 [EN7581_UART2_RST] = RST_NR_PER_BANK + 19, 445 [EN7581_GDMP_RST] = RST_NR_PER_BANK + 20, 446 [EN7581_FE_RST] = RST_NR_PER_BANK + 21, 447 [EN7581_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, 448 [EN7581_GSW_RST] = RST_NR_PER_BANK + 23, 449 [EN7581_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, 450 [EN7581_PCIE0_RST] = RST_NR_PER_BANK + 26, 451 [EN7581_PCIE1_RST] = RST_NR_PER_BANK + 27, 452 [EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28, 453 [EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29, 454 [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31, 455 456 /* RST_PCIC */ 457 [EN7581_PCIC_PERSTOUT0_RST] = 2 * RST_NR_PER_BANK + 29, 458 [EN7581_PCIC_PERSTOUT1_RST] = 2 * RST_NR_PER_BANK + 26, 459 [EN7581_PCIC_PERSTOUT2_RST] = 2 * RST_NR_PER_BANK + 16, 460 }; 461 462 static const u16 en751221_rst_map[] = { 463 /* RST_CTRL2 */ 464 [EN751221_XPON_PHY_RST] = 0, 465 [EN751221_GFAST_RST] = 1, 466 [EN751221_CPU_TIMER2_RST] = 2, 467 [EN751221_UART3_RST] = 3, 468 [EN751221_UART4_RST] = 4, 469 [EN751221_UART5_RST] = 5, 470 [EN751221_I2C2_RST] = 6, 471 [EN751221_XSI_MAC_RST] = 7, 472 [EN751221_XSI_PHY_RST] = 8, 473 474 /* RST_CTRL1 */ 475 [EN751221_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, 476 [EN751221_FE_QDMA1_RST] = RST_NR_PER_BANK + 1, 477 [EN751221_FE_QDMA2_RST] = RST_NR_PER_BANK + 2, 478 [EN751221_FE_UNZIP_RST] = RST_NR_PER_BANK + 3, 479 [EN751221_PCM2_RST] = RST_NR_PER_BANK + 4, 480 [EN751221_PTM_MAC_RST] = RST_NR_PER_BANK + 5, 481 [EN751221_CRYPTO_RST] = RST_NR_PER_BANK + 6, 482 [EN751221_SAR_RST] = RST_NR_PER_BANK + 7, 483 [EN751221_TIMER_RST] = RST_NR_PER_BANK + 8, 484 [EN751221_INTC_RST] = RST_NR_PER_BANK + 9, 485 [EN751221_BONDING_RST] = RST_NR_PER_BANK + 10, 486 [EN751221_PCM1_RST] = RST_NR_PER_BANK + 11, 487 [EN751221_UART_RST] = RST_NR_PER_BANK + 12, 488 [EN751221_GPIO_RST] = RST_NR_PER_BANK + 13, 489 [EN751221_GDMA_RST] = RST_NR_PER_BANK + 14, 490 [EN751221_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, 491 [EN751221_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, 492 [EN751221_SFC_RST] = RST_NR_PER_BANK + 18, 493 [EN751221_UART2_RST] = RST_NR_PER_BANK + 19, 494 [EN751221_GDMP_RST] = RST_NR_PER_BANK + 20, 495 [EN751221_FE_RST] = RST_NR_PER_BANK + 21, 496 [EN751221_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, 497 [EN751221_GSW_RST] = RST_NR_PER_BANK + 23, 498 [EN751221_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, 499 [EN751221_PCIE0_RST] = RST_NR_PER_BANK + 26, 500 [EN751221_PCIE1_RST] = RST_NR_PER_BANK + 27, 501 [EN751221_CPU_TIMER_RST] = RST_NR_PER_BANK + 28, 502 [EN751221_PCIE_HB_RST] = RST_NR_PER_BANK + 29, 503 [EN751221_SIMIF_RST] = RST_NR_PER_BANK + 30, 504 [EN751221_XPON_MAC_RST] = RST_NR_PER_BANK + 31, 505 506 /* RST_DMT */ 507 [EN751221_DMT_RST] = 2 * RST_NR_PER_BANK + 0, 508 509 /* RST_USB */ 510 [EN751221_USB_PHY_P0_RST] = 3 * RST_NR_PER_BANK + 6, 511 [EN751221_USB_PHY_P1_RST] = 3 * RST_NR_PER_BANK + 7, 512 }; 513 514 static int en7581_reset_register(struct device *dev, void __iomem *base, 515 const u16 *rst_map, int nr_resets, 516 const u16 *rst_reg_ofs); 517 518 static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val) 519 { 520 if (!desc->base_bits) 521 return desc->base_value; 522 523 val >>= desc->base_shift; 524 val &= (1 << desc->base_bits) - 1; 525 526 if (val >= desc->n_base_values) 527 return 0; 528 529 return desc->base_values[val]; 530 } 531 532 static u32 en7523_get_div(const struct en_clk_desc *desc, u32 val) 533 { 534 if (!desc->div_bits) 535 return 1; 536 537 val >>= desc->div_shift; 538 val &= (1 << desc->div_bits) - 1; 539 540 if (!val && desc->div_val0) 541 return desc->div_val0; 542 543 return (val + desc->div_offset) * desc->div_step; 544 } 545 546 static int en7523_pci_is_enabled(struct clk_hw *hw) 547 { 548 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 549 550 return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); 551 } 552 553 static int en7523_pci_prepare(struct clk_hw *hw) 554 { 555 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 556 void __iomem *np_base = cg->base; 557 u32 val, mask; 558 559 /* Need to pull device low before reset */ 560 val = readl(np_base + REG_PCI_CONTROL); 561 val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); 562 writel(val, np_base + REG_PCI_CONTROL); 563 usleep_range(1000, 2000); 564 565 /* Enable PCIe port 1 */ 566 val |= REG_PCI_CONTROL_REFCLK_EN1; 567 writel(val, np_base + REG_PCI_CONTROL); 568 usleep_range(1000, 2000); 569 570 /* Reset to default */ 571 val = readl(np_base + REG_RESET_CONTROL1); 572 mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | 573 REG_RESET_CONTROL_PCIEHB; 574 writel(val & ~mask, np_base + REG_RESET_CONTROL1); 575 usleep_range(1000, 2000); 576 writel(val | mask, np_base + REG_RESET_CONTROL1); 577 msleep(100); 578 writel(val & ~mask, np_base + REG_RESET_CONTROL1); 579 usleep_range(5000, 10000); 580 581 /* Release device */ 582 mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; 583 val = readl(np_base + REG_PCI_CONTROL); 584 writel(val & ~mask, np_base + REG_PCI_CONTROL); 585 usleep_range(1000, 2000); 586 writel(val | mask, np_base + REG_PCI_CONTROL); 587 msleep(250); 588 589 return 0; 590 } 591 592 static void en7523_pci_unprepare(struct clk_hw *hw) 593 { 594 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 595 void __iomem *np_base = cg->base; 596 u32 val; 597 598 val = readl(np_base + REG_PCI_CONTROL); 599 val &= ~REG_PCI_CONTROL_REFCLK_EN1; 600 writel(val, np_base + REG_PCI_CONTROL); 601 } 602 603 static struct clk_hw *en7523_register_pcie_clk(struct device *dev, 604 void __iomem *np_base) 605 { 606 const struct en_clk_soc_data *soc_data = device_get_match_data(dev); 607 struct clk_init_data init = { 608 .name = "pcie", 609 .ops = &soc_data->pcie_ops, 610 }; 611 struct en_clk_gate *cg; 612 613 cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); 614 if (!cg) 615 return NULL; 616 617 cg->base = np_base; 618 cg->hw.init = &init; 619 620 if (init.ops->unprepare) 621 init.ops->unprepare(&cg->hw); 622 623 if (clk_hw_register(dev, &cg->hw)) 624 return NULL; 625 626 return &cg->hw; 627 } 628 629 static int en7581_pci_is_enabled(struct clk_hw *hw) 630 { 631 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 632 u32 val, mask; 633 634 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; 635 val = readl(cg->base + REG_PCI_CONTROL); 636 return (val & mask) == mask; 637 } 638 639 static int en7581_pci_enable(struct clk_hw *hw) 640 { 641 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 642 void __iomem *np_base = cg->base; 643 u32 val, mask; 644 645 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; 646 val = readl(np_base + REG_PCI_CONTROL); 647 writel(val | mask, np_base + REG_PCI_CONTROL); 648 649 return 0; 650 } 651 652 static void en7581_pci_disable(struct clk_hw *hw) 653 { 654 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); 655 void __iomem *np_base = cg->base; 656 u32 val, mask; 657 658 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; 659 val = readl(np_base + REG_PCI_CONTROL); 660 writel(val & ~mask, np_base + REG_PCI_CONTROL); 661 usleep_range(1000, 2000); 662 } 663 664 static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, 665 void __iomem *base, void __iomem *np_base) 666 { 667 struct clk_hw *hw; 668 u32 rate; 669 int i; 670 671 for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { 672 const struct en_clk_desc *desc = &en7523_base_clks[i]; 673 u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg; 674 u32 val = readl(base + desc->base_reg); 675 676 rate = en7523_get_base_rate(desc, val); 677 val = readl(base + reg); 678 rate /= en7523_get_div(desc, val); 679 680 hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); 681 if (IS_ERR(hw)) { 682 pr_err("Failed to register clk %s: %ld\n", 683 desc->name, PTR_ERR(hw)); 684 continue; 685 } 686 687 clk_data->hws[desc->id] = hw; 688 } 689 690 hw = en7523_register_pcie_clk(dev, np_base); 691 clk_data->hws[EN7523_CLK_PCIE] = hw; 692 } 693 694 static int en7523_clk_hw_init(struct platform_device *pdev, 695 struct clk_hw_onecell_data *clk_data) 696 { 697 void __iomem *base, *np_base; 698 699 base = devm_platform_ioremap_resource(pdev, 0); 700 if (IS_ERR(base)) 701 return PTR_ERR(base); 702 703 np_base = devm_platform_ioremap_resource(pdev, 1); 704 if (IS_ERR(np_base)) 705 return PTR_ERR(np_base); 706 707 en7523_register_clocks(&pdev->dev, clk_data, base, np_base); 708 709 return en7581_reset_register(&pdev->dev, np_base, en7523_rst_map, 710 ARRAY_SIZE(en7523_rst_map), 711 en7581_rst_ofs); 712 } 713 714 static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, 715 struct regmap *map, void __iomem *base) 716 { 717 struct clk_hw *hw; 718 u32 rate; 719 int i; 720 721 for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) { 722 const struct en_clk_desc *desc = &en7581_base_clks[i]; 723 u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; 724 int err; 725 726 err = regmap_read(map, desc->base_reg, &val); 727 if (err) { 728 pr_err("Failed reading fixed clk rate %s: %d\n", 729 desc->name, err); 730 continue; 731 } 732 rate = en7523_get_base_rate(desc, val); 733 734 err = regmap_read(map, reg, &val); 735 if (err) { 736 pr_err("Failed reading fixed clk div %s: %d\n", 737 desc->name, err); 738 continue; 739 } 740 rate /= en7523_get_div(desc, val); 741 742 hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); 743 if (IS_ERR(hw)) { 744 pr_err("Failed to register clk %s: %ld\n", 745 desc->name, PTR_ERR(hw)); 746 continue; 747 } 748 749 clk_data->hws[desc->id] = hw; 750 } 751 752 hw = en7523_register_pcie_clk(dev, base); 753 clk_data->hws[EN7523_CLK_PCIE] = hw; 754 } 755 756 static int en7523_reset_update(struct reset_controller_dev *rcdev, 757 unsigned long id, bool assert) 758 { 759 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 760 u32 offset = rst_data->bank_ofs[id / RST_NR_PER_BANK]; 761 void __iomem *addr = rst_data->base + offset; 762 bool inverted = false; 763 u32 val; 764 765 /* For PCIC reset logic is inverted, 0:assert 1:deassert */ 766 if (offset == REG_NP_SCU_PCIC) 767 inverted = true; 768 769 val = readl(addr); 770 if (assert ^ inverted) 771 val |= BIT(id % RST_NR_PER_BANK); 772 else 773 val &= ~BIT(id % RST_NR_PER_BANK); 774 writel(val, addr); 775 776 return 0; 777 } 778 779 static int en7523_reset_assert(struct reset_controller_dev *rcdev, 780 unsigned long id) 781 { 782 return en7523_reset_update(rcdev, id, true); 783 } 784 785 static int en7523_reset_deassert(struct reset_controller_dev *rcdev, 786 unsigned long id) 787 { 788 return en7523_reset_update(rcdev, id, false); 789 } 790 791 static int en7523_reset_status(struct reset_controller_dev *rcdev, 792 unsigned long id) 793 { 794 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 795 u32 offset = rst_data->bank_ofs[id / RST_NR_PER_BANK]; 796 void __iomem *addr = rst_data->base + offset; 797 bool inverted = false; 798 u32 val; 799 800 /* For PCIC reset logic is inverted, 0:assert 1:deassert */ 801 if (offset == REG_NP_SCU_PCIC) 802 inverted = true; 803 804 val = readl(addr) & BIT(id % RST_NR_PER_BANK); 805 return inverted ? !val : !!val; 806 } 807 808 static int en7523_reset_xlate(struct reset_controller_dev *rcdev, 809 const struct of_phandle_args *reset_spec) 810 { 811 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); 812 813 if (reset_spec->args[0] >= rcdev->nr_resets) 814 return -EINVAL; 815 816 return rst_data->idx_map[reset_spec->args[0]]; 817 } 818 819 static const struct reset_control_ops en7581_reset_ops = { 820 .assert = en7523_reset_assert, 821 .deassert = en7523_reset_deassert, 822 .status = en7523_reset_status, 823 }; 824 825 static int en7581_reset_register(struct device *dev, void __iomem *base, 826 const u16 *rst_map, int nr_resets, 827 const u16 *rst_reg_ofs) 828 { 829 struct en_rst_data *rst_data; 830 831 rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); 832 if (!rst_data) 833 return -ENOMEM; 834 835 rst_data->bank_ofs = rst_reg_ofs; 836 rst_data->idx_map = rst_map; 837 rst_data->base = base; 838 839 rst_data->rcdev.nr_resets = nr_resets; 840 rst_data->rcdev.of_xlate = en7523_reset_xlate; 841 rst_data->rcdev.ops = &en7581_reset_ops; 842 rst_data->rcdev.of_node = dev->of_node; 843 rst_data->rcdev.of_reset_n_cells = 1; 844 rst_data->rcdev.owner = THIS_MODULE; 845 rst_data->rcdev.dev = dev; 846 847 return devm_reset_controller_register(dev, &rst_data->rcdev); 848 } 849 850 static int en7581_clk_hw_init(struct platform_device *pdev, 851 struct clk_hw_onecell_data *clk_data) 852 { 853 struct regmap *map; 854 void __iomem *base; 855 u32 val; 856 857 map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); 858 if (IS_ERR(map)) 859 return PTR_ERR(map); 860 861 base = devm_platform_ioremap_resource(pdev, 0); 862 if (IS_ERR(base)) 863 return PTR_ERR(base); 864 865 en7581_register_clocks(&pdev->dev, clk_data, map, base); 866 867 val = readl(base + REG_NP_SCU_SSTR); 868 val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); 869 writel(val, base + REG_NP_SCU_SSTR); 870 val = readl(base + REG_NP_SCU_PCIC); 871 writel(val | 3, base + REG_NP_SCU_PCIC); 872 873 val = readl(base + REG_RST_CTRL1); 874 val |= REG_PCIE_HB_RST; 875 writel(val, base + REG_RST_CTRL1); 876 val &= ~REG_PCIE_HB_RST; 877 writel(val, base + REG_RST_CTRL1); 878 879 return en7581_reset_register(&pdev->dev, base, en7581_rst_map, 880 ARRAY_SIZE(en7581_rst_map), 881 en7581_rst_ofs); 882 } 883 884 static enum en_hir get_hw_id(void __iomem *np_base) 885 { 886 u32 val = FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR)); 887 888 if (val < HIR_MAX) 889 return (enum en_hir)val; 890 891 pr_warn("Unable to determine EcoNet SoC\n"); 892 893 return HIR_UNKNOWN; 894 } 895 896 static void en751221_try_register_clk(struct device *dev, int key, 897 struct clk_hw_onecell_data *clk_data, 898 const char *name, u32 rate) 899 { 900 struct clk_hw *hw; 901 902 if (WARN_ON_ONCE(key >= EN751221_MAX_CLKS)) 903 return; 904 905 hw = clk_hw_register_fixed_rate(dev, name, NULL, 0, rate); 906 if (IS_ERR(hw)) 907 pr_err("Failed to register clk %s: %pe\n", name, hw); 908 else 909 clk_data->hws[key] = hw; 910 } 911 912 static void en751221_register_clocks(struct device *dev, 913 struct clk_hw_onecell_data *clk_data, 914 struct regmap *map, void __iomem *np_base) 915 { 916 enum en_hir hid = get_hw_id(np_base); 917 struct clk_hw *hw; 918 u32 rate; 919 u32 div; 920 int err; 921 922 /* PCI */ 923 hw = en7523_register_pcie_clk(dev, np_base); 924 clk_data->hws[EN751221_CLK_PCIE] = hw; 925 926 /* SPI */ 927 rate = EN751221_SPI_BASE; 928 if (hid == HIR_EN7526C) 929 rate = EN751221_SPI_BASE_EN7526C; 930 931 err = regmap_read(map, EN751221_REG_SPI_DIV, &div); 932 if (err) { 933 pr_err("Failed reading fixed clk div %s: %d\n", 934 "spi", err); 935 } else { 936 div = FIELD_GET(EN751221_REG_SPI_DIV_MASK, div) * 2; 937 if (!div) 938 div = EN751221_SPI_DIV_DEFAULT; 939 940 en751221_try_register_clk(dev, EN751221_CLK_SPI, clk_data, 941 "spi", rate / div); 942 } 943 944 /* BUS */ 945 rate = FIELD_GET(EN751221_REG_BUS_MASK, 946 readl(np_base + EN751221_REG_BUS)); 947 rate *= 1000000; 948 en751221_try_register_clk(dev, EN751221_CLK_BUS, clk_data, "bus", 949 rate); 950 951 /* CPU */ 952 en751221_try_register_clk(dev, EN751221_CLK_CPU, clk_data, "cpu", 953 rate * 4); 954 955 /* GSW */ 956 rate = FIELD_GET(EN751221_REG_SSR3_GSW_MASK, 957 readl(np_base + EN751221_REG_SSR3)); 958 en751221_try_register_clk(dev, EN751221_CLK_GSW, clk_data, "gsw", 959 gsw751221_base[rate]); 960 } 961 962 static int en751221_clk_hw_init(struct platform_device *pdev, 963 struct clk_hw_onecell_data *clk_data) 964 { 965 struct regmap *map; 966 void __iomem *base; 967 968 map = syscon_regmap_lookup_by_compatible("econet,en751221-chip-scu"); 969 if (IS_ERR(map)) 970 return PTR_ERR(map); 971 972 base = devm_platform_ioremap_resource(pdev, 0); 973 if (IS_ERR(base)) 974 return PTR_ERR(base); 975 976 en751221_register_clocks(&pdev->dev, clk_data, map, base); 977 978 return en7581_reset_register(&pdev->dev, base, en751221_rst_map, 979 ARRAY_SIZE(en751221_rst_map), 980 en751221_rst_ofs); 981 } 982 983 static int en7523_clk_probe(struct platform_device *pdev) 984 { 985 struct device_node *node = pdev->dev.of_node; 986 const struct en_clk_soc_data *soc_data; 987 struct clk_hw_onecell_data *clk_data; 988 int r; 989 990 soc_data = device_get_match_data(&pdev->dev); 991 992 clk_data = devm_kzalloc(&pdev->dev, 993 struct_size(clk_data, hws, soc_data->num_clocks), 994 GFP_KERNEL); 995 if (!clk_data) 996 return -ENOMEM; 997 998 clk_data->num = soc_data->num_clocks; 999 r = soc_data->hw_init(pdev, clk_data); 1000 if (r) 1001 return r; 1002 1003 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1004 } 1005 1006 static const struct en_clk_soc_data en7523_data = { 1007 .num_clocks = ARRAY_SIZE(en7523_base_clks) + 1, 1008 .pcie_ops = { 1009 .is_enabled = en7523_pci_is_enabled, 1010 .prepare = en7523_pci_prepare, 1011 .unprepare = en7523_pci_unprepare, 1012 }, 1013 .hw_init = en7523_clk_hw_init, 1014 }; 1015 1016 static const struct en_clk_soc_data en7581_data = { 1017 /* We increment num_clocks by 1 to account for additional PCIe clock */ 1018 .num_clocks = ARRAY_SIZE(en7581_base_clks) + 1, 1019 .pcie_ops = { 1020 .is_enabled = en7581_pci_is_enabled, 1021 .enable = en7581_pci_enable, 1022 .disable = en7581_pci_disable, 1023 }, 1024 .hw_init = en7581_clk_hw_init, 1025 }; 1026 1027 static const struct en_clk_soc_data en751221_data = { 1028 .num_clocks = EN751221_MAX_CLKS, 1029 .pcie_ops = { 1030 .is_enabled = en7523_pci_is_enabled, 1031 .prepare = en7523_pci_prepare, 1032 .unprepare = en7523_pci_unprepare, 1033 }, 1034 .hw_init = en751221_clk_hw_init, 1035 }; 1036 1037 static const struct of_device_id of_match_clk_en7523[] = { 1038 { .compatible = "airoha,en7523-scu", .data = &en7523_data }, 1039 { .compatible = "airoha,en7581-scu", .data = &en7581_data }, 1040 { .compatible = "econet,en751221-scu", .data = &en751221_data }, 1041 { /* sentinel */ } 1042 }; 1043 1044 static struct platform_driver clk_en7523_drv = { 1045 .probe = en7523_clk_probe, 1046 .driver = { 1047 .name = "clk-en7523", 1048 .of_match_table = of_match_clk_en7523, 1049 .suppress_bind_attrs = true, 1050 }, 1051 }; 1052 1053 static int __init clk_en7523_init(void) 1054 { 1055 return platform_driver_register(&clk_en7523_drv); 1056 } 1057 1058 arch_initcall(clk_en7523_init); 1059