1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Cirrus Logic CLPS711X CLK driver 4 * 5 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/clkdev.h> 10 #include <linux/io.h> 11 #include <linux/ioport.h> 12 #include <linux/of_address.h> 13 #include <linux/slab.h> 14 #include <linux/mfd/syscon/clps711x.h> 15 16 #include <dt-bindings/clock/clps711x-clock.h> 17 18 #define CLPS711X_SYSCON1 (0x0100) 19 #define CLPS711X_SYSCON2 (0x1100) 20 #define CLPS711X_SYSFLG2 (CLPS711X_SYSCON2 + SYSFLG_OFFSET) 21 #define CLPS711X_PLLR (0xa5a8) 22 23 #define CLPS711X_EXT_FREQ (13000000) 24 #define CLPS711X_OSC_FREQ (3686400) 25 26 static const struct clk_div_table spi_div_table[] = { 27 { .val = 0, .div = 32, }, 28 { .val = 1, .div = 8, }, 29 { .val = 2, .div = 2, }, 30 { .val = 3, .div = 1, }, 31 { /* sentinel */ } 32 }; 33 34 static const struct clk_div_table timer_div_table[] = { 35 { .val = 0, .div = 256, }, 36 { .val = 1, .div = 1, }, 37 { /* sentinel */ } 38 }; 39 40 struct clps711x_clk { 41 spinlock_t lock; 42 struct clk_hw_onecell_data clk_data; 43 }; 44 45 static void __init clps711x_clk_init_dt(struct device_node *np) 46 { 47 u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi, fref = 0; 48 struct clps711x_clk *clps711x_clk; 49 void __iomem *base; 50 51 WARN_ON(of_property_read_u32(np, "startup-frequency", &fref)); 52 53 base = of_iomap(np, 0); 54 BUG_ON(!base); 55 56 clps711x_clk = kzalloc_flex(*clps711x_clk, clk_data.hws, 57 CLPS711X_CLK_MAX); 58 BUG_ON(!clps711x_clk); 59 60 spin_lock_init(&clps711x_clk->lock); 61 62 /* Read PLL multiplier value and sanity check */ 63 tmp = readl(base + CLPS711X_PLLR) >> 24; 64 if (((tmp >= 10) && (tmp <= 50)) || !fref) 65 f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2); 66 else 67 f_pll = fref; 68 69 tmp = readl(base + CLPS711X_SYSFLG2); 70 if (tmp & SYSFLG2_CKMODE) { 71 f_cpu = CLPS711X_EXT_FREQ; 72 f_bus = CLPS711X_EXT_FREQ; 73 f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96); 74 f_pll = 0; 75 f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128); 76 } else { 77 f_cpu = f_pll; 78 if (f_cpu > 36864000) 79 f_bus = DIV_ROUND_UP(f_cpu, 2); 80 else 81 f_bus = 36864000 / 2; 82 f_spi = DIV_ROUND_CLOSEST(f_cpu, 576); 83 f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768); 84 } 85 86 if (tmp & SYSFLG2_CKMODE) { 87 if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB) 88 f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26); 89 else 90 f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24); 91 } else 92 f_tim = DIV_ROUND_CLOSEST(f_cpu, 144); 93 94 tmp = readl(base + CLPS711X_SYSCON1); 95 /* Timer1 in free running mode. 96 * Counter will wrap around to 0xffff when it underflows 97 * and will continue to count down. 98 */ 99 tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S); 100 /* Timer2 in prescale mode. 101 * Value written is automatically re-loaded when 102 * the counter underflows. 103 */ 104 tmp |= SYSCON1_TC2M | SYSCON1_TC2S; 105 writel(tmp, base + CLPS711X_SYSCON1); 106 107 clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] = 108 clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0); 109 clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] = 110 clk_hw_register_fixed_rate(NULL, "cpu", NULL, 0, f_cpu); 111 clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] = 112 clk_hw_register_fixed_rate(NULL, "bus", NULL, 0, f_bus); 113 clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] = 114 clk_hw_register_fixed_rate(NULL, "pll", NULL, 0, f_pll); 115 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] = 116 clk_hw_register_fixed_rate(NULL, "timer_ref", NULL, 0, f_tim); 117 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] = 118 clk_hw_register_divider_table(NULL, "timer1", "timer_ref", 0, 119 base + CLPS711X_SYSCON1, 5, 1, 0, 120 timer_div_table, &clps711x_clk->lock); 121 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] = 122 clk_hw_register_divider_table(NULL, "timer2", "timer_ref", 0, 123 base + CLPS711X_SYSCON1, 7, 1, 0, 124 timer_div_table, &clps711x_clk->lock); 125 clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] = 126 clk_hw_register_fixed_rate(NULL, "pwm", NULL, 0, f_pwm); 127 clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] = 128 clk_hw_register_fixed_rate(NULL, "spi_ref", NULL, 0, f_spi); 129 clps711x_clk->clk_data.hws[CLPS711X_CLK_SPI] = 130 clk_hw_register_divider_table(NULL, "spi", "spi_ref", 0, 131 base + CLPS711X_SYSCON1, 16, 2, 0, 132 spi_div_table, &clps711x_clk->lock); 133 clps711x_clk->clk_data.hws[CLPS711X_CLK_UART] = 134 clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10); 135 clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] = 136 clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64); 137 for (tmp = 0; tmp < CLPS711X_CLK_MAX; tmp++) 138 if (IS_ERR(clps711x_clk->clk_data.hws[tmp])) 139 pr_err("clk %i: register failed with %ld\n", 140 tmp, PTR_ERR(clps711x_clk->clk_data.hws[tmp])); 141 142 clps711x_clk->clk_data.num = CLPS711X_CLK_MAX; 143 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, 144 &clps711x_clk->clk_data); 145 } 146 CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt); 147