1 /* 2 * Driver for TI Dual PLL CDCE925 clock synthesizer 3 * 4 * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1 5 * and Y4/Y5 to PLL2. PLL frequency is set on a first-come-first-serve 6 * basis. Clients can directly request any frequency that the chip can 7 * deliver using the standard clk framework. In addition, the device can 8 * be configured and activated via the devicetree. 9 * 10 * Copyright (C) 2014, Topic Embedded Products 11 * Licenced under GPL 12 */ 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/delay.h> 16 #include <linux/module.h> 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 #include <linux/gcd.h> 21 22 /* The chip has 2 PLLs which can be routed through dividers to 5 outputs. 23 * Model this as 2 PLL clocks which are parents to the outputs. 24 */ 25 #define NUMBER_OF_PLLS 2 26 #define NUMBER_OF_OUTPUTS 5 27 28 #define CDCE925_REG_GLOBAL1 0x01 29 #define CDCE925_REG_Y1SPIPDIVH 0x02 30 #define CDCE925_REG_PDIVL 0x03 31 #define CDCE925_REG_XCSEL 0x05 32 /* PLL parameters start at 0x10, steps of 0x10 */ 33 #define CDCE925_OFFSET_PLL 0x10 34 /* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */ 35 #define CDCE925_PLL_MUX_OUTPUTS 0x14 36 #define CDCE925_PLL_MULDIV 0x18 37 38 #define CDCE925_PLL_FREQUENCY_MIN 80000000ul 39 #define CDCE925_PLL_FREQUENCY_MAX 230000000ul 40 struct clk_cdce925_chip; 41 42 struct clk_cdce925_output { 43 struct clk_hw hw; 44 struct clk_cdce925_chip *chip; 45 u8 index; 46 u16 pdiv; /* 1..127 for Y2-Y5; 1..1023 for Y1 */ 47 }; 48 #define to_clk_cdce925_output(_hw) \ 49 container_of(_hw, struct clk_cdce925_output, hw) 50 51 struct clk_cdce925_pll { 52 struct clk_hw hw; 53 struct clk_cdce925_chip *chip; 54 u8 index; 55 u16 m; /* 1..511 */ 56 u16 n; /* 1..4095 */ 57 }; 58 #define to_clk_cdce925_pll(_hw) container_of(_hw, struct clk_cdce925_pll, hw) 59 60 struct clk_cdce925_chip { 61 struct regmap *regmap; 62 struct i2c_client *i2c_client; 63 struct clk_cdce925_pll pll[NUMBER_OF_PLLS]; 64 struct clk_cdce925_output clk[NUMBER_OF_OUTPUTS]; 65 struct clk *dt_clk[NUMBER_OF_OUTPUTS]; 66 struct clk_onecell_data onecell; 67 }; 68 69 /* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */ 70 71 static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate, 72 u16 n, u16 m) 73 { 74 if ((!m || !n) || (m == n)) 75 return parent_rate; /* In bypass mode runs at same frequency */ 76 return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m); 77 } 78 79 static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw, 80 unsigned long parent_rate) 81 { 82 /* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */ 83 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 84 85 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); 86 } 87 88 static void cdce925_pll_find_rate(unsigned long rate, 89 unsigned long parent_rate, u16 *n, u16 *m) 90 { 91 unsigned long un; 92 unsigned long um; 93 unsigned long g; 94 95 if (rate <= parent_rate) { 96 /* Can always deliver parent_rate in bypass mode */ 97 rate = parent_rate; 98 *n = 0; 99 *m = 0; 100 } else { 101 /* In PLL mode, need to apply min/max range */ 102 if (rate < CDCE925_PLL_FREQUENCY_MIN) 103 rate = CDCE925_PLL_FREQUENCY_MIN; 104 else if (rate > CDCE925_PLL_FREQUENCY_MAX) 105 rate = CDCE925_PLL_FREQUENCY_MAX; 106 107 g = gcd(rate, parent_rate); 108 um = parent_rate / g; 109 un = rate / g; 110 /* When outside hw range, reduce to fit (rounding errors) */ 111 while ((un > 4095) || (um > 511)) { 112 un >>= 1; 113 um >>= 1; 114 } 115 if (un == 0) 116 un = 1; 117 if (um == 0) 118 um = 1; 119 120 *n = un; 121 *m = um; 122 } 123 } 124 125 static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate, 126 unsigned long *parent_rate) 127 { 128 u16 n, m; 129 130 cdce925_pll_find_rate(rate, *parent_rate, &n, &m); 131 return (long)cdce925_pll_calculate_rate(*parent_rate, n, m); 132 } 133 134 static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate, 135 unsigned long parent_rate) 136 { 137 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 138 139 if (!rate || (rate == parent_rate)) { 140 data->m = 0; /* Bypass mode */ 141 data->n = 0; 142 return 0; 143 } 144 145 if ((rate < CDCE925_PLL_FREQUENCY_MIN) || 146 (rate > CDCE925_PLL_FREQUENCY_MAX)) { 147 pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate); 148 return -EINVAL; 149 } 150 151 if (rate < parent_rate) { 152 pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__, 153 rate, parent_rate); 154 return -EINVAL; 155 } 156 157 cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); 158 return 0; 159 } 160 161 162 /* calculate p = max(0, 4 - int(log2 (n/m))) */ 163 static u8 cdce925_pll_calc_p(u16 n, u16 m) 164 { 165 u8 p; 166 u16 r = n / m; 167 168 if (r >= 16) 169 return 0; 170 p = 4; 171 while (r > 1) { 172 r >>= 1; 173 --p; 174 } 175 return p; 176 } 177 178 /* Returns VCO range bits for VCO1_0_RANGE */ 179 static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m) 180 { 181 struct clk *parent = clk_get_parent(hw->clk); 182 unsigned long rate = clk_get_rate(parent); 183 184 rate = mult_frac(rate, (unsigned long)n, (unsigned long)m); 185 if (rate >= 175000000) 186 return 0x3; 187 if (rate >= 150000000) 188 return 0x02; 189 if (rate >= 125000000) 190 return 0x01; 191 return 0x00; 192 } 193 194 /* I2C clock, hence everything must happen in (un)prepare because this 195 * may sleep */ 196 static int cdce925_pll_prepare(struct clk_hw *hw) 197 { 198 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 199 u16 n = data->n; 200 u16 m = data->m; 201 u16 r; 202 u8 q; 203 u8 p; 204 u16 nn; 205 u8 pll[4]; /* Bits are spread out over 4 byte registers */ 206 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; 207 unsigned i; 208 209 if ((!m || !n) || (m == n)) { 210 /* Set PLL mux to bypass mode, leave the rest as is */ 211 regmap_update_bits(data->chip->regmap, 212 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); 213 } else { 214 /* According to data sheet: */ 215 /* p = max(0, 4 - int(log2 (n/m))) */ 216 p = cdce925_pll_calc_p(n, m); 217 /* nn = n * 2^p */ 218 nn = n * BIT(p); 219 /* q = int(nn/m) */ 220 q = nn / m; 221 if ((q < 16) || (1 > 64)) { 222 pr_debug("%s invalid q=%d\n", __func__, q); 223 return -EINVAL; 224 } 225 r = nn - (m*q); 226 if (r > 511) { 227 pr_debug("%s invalid r=%d\n", __func__, r); 228 return -EINVAL; 229 } 230 pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__, 231 n, m, p, q, r); 232 /* encode into register bits */ 233 pll[0] = n >> 4; 234 pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F); 235 pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07); 236 pll[3] = ((q & 0x07) << 5) | (p << 2) | 237 cdce925_pll_calc_range_bits(hw, n, m); 238 /* Write to registers */ 239 for (i = 0; i < ARRAY_SIZE(pll); ++i) 240 regmap_write(data->chip->regmap, 241 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); 242 /* Enable PLL */ 243 regmap_update_bits(data->chip->regmap, 244 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00); 245 } 246 247 return 0; 248 } 249 250 static void cdce925_pll_unprepare(struct clk_hw *hw) 251 { 252 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 253 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; 254 255 regmap_update_bits(data->chip->regmap, 256 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); 257 } 258 259 static const struct clk_ops cdce925_pll_ops = { 260 .prepare = cdce925_pll_prepare, 261 .unprepare = cdce925_pll_unprepare, 262 .recalc_rate = cdce925_pll_recalc_rate, 263 .round_rate = cdce925_pll_round_rate, 264 .set_rate = cdce925_pll_set_rate, 265 }; 266 267 268 static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) 269 { 270 switch (data->index) { 271 case 0: 272 regmap_update_bits(data->chip->regmap, 273 CDCE925_REG_Y1SPIPDIVH, 274 0x03, (pdiv >> 8) & 0x03); 275 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); 276 break; 277 case 1: 278 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); 279 break; 280 case 2: 281 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); 282 break; 283 case 3: 284 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); 285 break; 286 case 4: 287 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); 288 break; 289 } 290 } 291 292 static void cdce925_clk_activate(struct clk_cdce925_output *data) 293 { 294 switch (data->index) { 295 case 0: 296 regmap_update_bits(data->chip->regmap, 297 CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c); 298 break; 299 case 1: 300 case 2: 301 regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03); 302 break; 303 case 3: 304 case 4: 305 regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03); 306 break; 307 } 308 } 309 310 static int cdce925_clk_prepare(struct clk_hw *hw) 311 { 312 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 313 314 cdce925_clk_set_pdiv(data, data->pdiv); 315 cdce925_clk_activate(data); 316 return 0; 317 } 318 319 static void cdce925_clk_unprepare(struct clk_hw *hw) 320 { 321 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 322 323 /* Disable clock by setting divider to "0" */ 324 cdce925_clk_set_pdiv(data, 0); 325 } 326 327 static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw, 328 unsigned long parent_rate) 329 { 330 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 331 332 if (data->pdiv) 333 return parent_rate / data->pdiv; 334 return 0; 335 } 336 337 static u16 cdce925_calc_divider(unsigned long rate, 338 unsigned long parent_rate) 339 { 340 unsigned long divider; 341 342 if (!rate) 343 return 0; 344 if (rate >= parent_rate) 345 return 1; 346 347 divider = DIV_ROUND_CLOSEST(parent_rate, rate); 348 if (divider > 0x7F) 349 divider = 0x7F; 350 351 return (u16)divider; 352 } 353 354 static unsigned long cdce925_clk_best_parent_rate( 355 struct clk_hw *hw, unsigned long rate) 356 { 357 struct clk *pll = clk_get_parent(hw->clk); 358 struct clk *root = clk_get_parent(pll); 359 unsigned long root_rate = clk_get_rate(root); 360 unsigned long best_rate_error = rate; 361 u16 pdiv_min; 362 u16 pdiv_max; 363 u16 pdiv_best; 364 u16 pdiv_now; 365 366 if (root_rate % rate == 0) 367 return root_rate; /* Don't need the PLL, use bypass */ 368 369 pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate)); 370 pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate); 371 372 if (pdiv_min > pdiv_max) 373 return 0; /* No can do? */ 374 375 pdiv_best = pdiv_min; 376 for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) { 377 unsigned long target_rate = rate * pdiv_now; 378 long pll_rate = clk_round_rate(pll, target_rate); 379 unsigned long actual_rate; 380 unsigned long rate_error; 381 382 if (pll_rate <= 0) 383 continue; 384 actual_rate = pll_rate / pdiv_now; 385 rate_error = abs((long)actual_rate - (long)rate); 386 if (rate_error < best_rate_error) { 387 pdiv_best = pdiv_now; 388 best_rate_error = rate_error; 389 } 390 /* TODO: Consider PLL frequency based on smaller n/m values 391 * and pick the better one if the error is equal */ 392 } 393 394 return rate * pdiv_best; 395 } 396 397 static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate, 398 unsigned long *parent_rate) 399 { 400 unsigned long l_parent_rate = *parent_rate; 401 u16 divider = cdce925_calc_divider(rate, l_parent_rate); 402 403 if (l_parent_rate / divider != rate) { 404 l_parent_rate = cdce925_clk_best_parent_rate(hw, rate); 405 divider = cdce925_calc_divider(rate, l_parent_rate); 406 *parent_rate = l_parent_rate; 407 } 408 409 if (divider) 410 return (long)(l_parent_rate / divider); 411 return 0; 412 } 413 414 static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate, 415 unsigned long parent_rate) 416 { 417 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 418 419 data->pdiv = cdce925_calc_divider(rate, parent_rate); 420 421 return 0; 422 } 423 424 static const struct clk_ops cdce925_clk_ops = { 425 .prepare = cdce925_clk_prepare, 426 .unprepare = cdce925_clk_unprepare, 427 .recalc_rate = cdce925_clk_recalc_rate, 428 .round_rate = cdce925_clk_round_rate, 429 .set_rate = cdce925_clk_set_rate, 430 }; 431 432 433 static u16 cdce925_y1_calc_divider(unsigned long rate, 434 unsigned long parent_rate) 435 { 436 unsigned long divider; 437 438 if (!rate) 439 return 0; 440 if (rate >= parent_rate) 441 return 1; 442 443 divider = DIV_ROUND_CLOSEST(parent_rate, rate); 444 if (divider > 0x3FF) /* Y1 has 10-bit divider */ 445 divider = 0x3FF; 446 447 return (u16)divider; 448 } 449 450 static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate, 451 unsigned long *parent_rate) 452 { 453 unsigned long l_parent_rate = *parent_rate; 454 u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate); 455 456 if (divider) 457 return (long)(l_parent_rate / divider); 458 return 0; 459 } 460 461 static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate, 462 unsigned long parent_rate) 463 { 464 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 465 466 data->pdiv = cdce925_y1_calc_divider(rate, parent_rate); 467 468 return 0; 469 } 470 471 static const struct clk_ops cdce925_clk_y1_ops = { 472 .prepare = cdce925_clk_prepare, 473 .unprepare = cdce925_clk_unprepare, 474 .recalc_rate = cdce925_clk_recalc_rate, 475 .round_rate = cdce925_clk_y1_round_rate, 476 .set_rate = cdce925_clk_y1_set_rate, 477 }; 478 479 480 static struct regmap_config cdce925_regmap_config = { 481 .name = "configuration0", 482 .reg_bits = 8, 483 .val_bits = 8, 484 .cache_type = REGCACHE_RBTREE, 485 .max_register = 0x2F, 486 }; 487 488 #define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00 489 #define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80 490 491 static int cdce925_regmap_i2c_write( 492 void *context, const void *data, size_t count) 493 { 494 struct device *dev = context; 495 struct i2c_client *i2c = to_i2c_client(dev); 496 int ret; 497 u8 reg_data[2]; 498 499 if (count != 2) 500 return -ENOTSUPP; 501 502 /* First byte is command code */ 503 reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0]; 504 reg_data[1] = ((u8 *)data)[1]; 505 506 dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count, 507 reg_data[0], reg_data[1]); 508 509 ret = i2c_master_send(i2c, reg_data, count); 510 if (likely(ret == count)) 511 return 0; 512 else if (ret < 0) 513 return ret; 514 else 515 return -EIO; 516 } 517 518 static int cdce925_regmap_i2c_read(void *context, 519 const void *reg, size_t reg_size, void *val, size_t val_size) 520 { 521 struct device *dev = context; 522 struct i2c_client *i2c = to_i2c_client(dev); 523 struct i2c_msg xfer[2]; 524 int ret; 525 u8 reg_data[2]; 526 527 if (reg_size != 1) 528 return -ENOTSUPP; 529 530 xfer[0].addr = i2c->addr; 531 xfer[0].flags = 0; 532 xfer[0].buf = reg_data; 533 if (val_size == 1) { 534 reg_data[0] = 535 CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0]; 536 xfer[0].len = 1; 537 } else { 538 reg_data[0] = 539 CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0]; 540 reg_data[1] = val_size; 541 xfer[0].len = 2; 542 } 543 544 xfer[1].addr = i2c->addr; 545 xfer[1].flags = I2C_M_RD; 546 xfer[1].len = val_size; 547 xfer[1].buf = val; 548 549 ret = i2c_transfer(i2c->adapter, xfer, 2); 550 if (likely(ret == 2)) { 551 dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__, 552 reg_size, val_size, reg_data[0], *((u8 *)val)); 553 return 0; 554 } else if (ret < 0) 555 return ret; 556 else 557 return -EIO; 558 } 559 560 /* The CDCE925 uses a funky way to read/write registers. Bulk mode is 561 * just weird, so just use the single byte mode exclusively. */ 562 static struct regmap_bus regmap_cdce925_bus = { 563 .write = cdce925_regmap_i2c_write, 564 .read = cdce925_regmap_i2c_read, 565 }; 566 567 static int cdce925_probe(struct i2c_client *client, 568 const struct i2c_device_id *id) 569 { 570 struct clk_cdce925_chip *data; 571 struct device_node *node = client->dev.of_node; 572 const char *parent_name; 573 const char *pll_clk_name[NUMBER_OF_PLLS] = {NULL,}; 574 struct clk_init_data init; 575 struct clk *clk; 576 u32 value; 577 int i; 578 int err; 579 struct device_node *np_output; 580 char child_name[6]; 581 582 dev_dbg(&client->dev, "%s\n", __func__); 583 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); 584 if (!data) 585 return -ENOMEM; 586 587 data->i2c_client = client; 588 data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus, 589 &client->dev, &cdce925_regmap_config); 590 if (IS_ERR(data->regmap)) { 591 dev_err(&client->dev, "failed to allocate register map\n"); 592 return PTR_ERR(data->regmap); 593 } 594 i2c_set_clientdata(client, data); 595 596 parent_name = of_clk_get_parent_name(node, 0); 597 if (!parent_name) { 598 dev_err(&client->dev, "missing parent clock\n"); 599 return -ENODEV; 600 } 601 dev_dbg(&client->dev, "parent is: %s\n", parent_name); 602 603 if (of_property_read_u32(node, "xtal-load-pf", &value) == 0) 604 regmap_write(data->regmap, 605 CDCE925_REG_XCSEL, (value << 3) & 0xF8); 606 /* PWDN bit */ 607 regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0); 608 609 /* Set input source for Y1 to be the XTAL */ 610 regmap_update_bits(data->regmap, 0x02, BIT(7), 0); 611 612 init.ops = &cdce925_pll_ops; 613 init.flags = 0; 614 init.parent_names = &parent_name; 615 init.num_parents = parent_name ? 1 : 0; 616 617 /* Register PLL clocks */ 618 for (i = 0; i < NUMBER_OF_PLLS; ++i) { 619 pll_clk_name[i] = kasprintf(GFP_KERNEL, "%s.pll%d", 620 client->dev.of_node->name, i); 621 init.name = pll_clk_name[i]; 622 data->pll[i].chip = data; 623 data->pll[i].hw.init = &init; 624 data->pll[i].index = i; 625 clk = devm_clk_register(&client->dev, &data->pll[i].hw); 626 if (IS_ERR(clk)) { 627 dev_err(&client->dev, "Failed register PLL %d\n", i); 628 err = PTR_ERR(clk); 629 goto error; 630 } 631 sprintf(child_name, "PLL%d", i+1); 632 np_output = of_get_child_by_name(node, child_name); 633 if (!np_output) 634 continue; 635 if (!of_property_read_u32(np_output, 636 "clock-frequency", &value)) { 637 err = clk_set_rate(clk, value); 638 if (err) 639 dev_err(&client->dev, 640 "unable to set PLL frequency %ud\n", 641 value); 642 } 643 if (!of_property_read_u32(np_output, 644 "spread-spectrum", &value)) { 645 u8 flag = of_property_read_bool(np_output, 646 "spread-spectrum-center") ? 0x80 : 0x00; 647 regmap_update_bits(data->regmap, 648 0x16 + (i*CDCE925_OFFSET_PLL), 649 0x80, flag); 650 regmap_update_bits(data->regmap, 651 0x12 + (i*CDCE925_OFFSET_PLL), 652 0x07, value & 0x07); 653 } 654 } 655 656 /* Register output clock Y1 */ 657 init.ops = &cdce925_clk_y1_ops; 658 init.flags = 0; 659 init.num_parents = 1; 660 init.parent_names = &parent_name; /* Mux Y1 to input */ 661 init.name = kasprintf(GFP_KERNEL, "%s.Y1", client->dev.of_node->name); 662 data->clk[0].chip = data; 663 data->clk[0].hw.init = &init; 664 data->clk[0].index = 0; 665 data->clk[0].pdiv = 1; 666 clk = devm_clk_register(&client->dev, &data->clk[0].hw); 667 kfree(init.name); /* clock framework made a copy of the name */ 668 if (IS_ERR(clk)) { 669 dev_err(&client->dev, "clock registration Y1 failed\n"); 670 err = PTR_ERR(clk); 671 goto error; 672 } 673 data->dt_clk[0] = clk; 674 675 /* Register output clocks Y2 .. Y5*/ 676 init.ops = &cdce925_clk_ops; 677 init.flags = CLK_SET_RATE_PARENT; 678 init.num_parents = 1; 679 for (i = 1; i < NUMBER_OF_OUTPUTS; ++i) { 680 init.name = kasprintf(GFP_KERNEL, "%s.Y%d", 681 client->dev.of_node->name, i+1); 682 data->clk[i].chip = data; 683 data->clk[i].hw.init = &init; 684 data->clk[i].index = i; 685 data->clk[i].pdiv = 1; 686 switch (i) { 687 case 1: 688 case 2: 689 /* Mux Y2/3 to PLL1 */ 690 init.parent_names = &pll_clk_name[0]; 691 break; 692 case 3: 693 case 4: 694 /* Mux Y4/5 to PLL2 */ 695 init.parent_names = &pll_clk_name[1]; 696 break; 697 } 698 clk = devm_clk_register(&client->dev, &data->clk[i].hw); 699 kfree(init.name); /* clock framework made a copy of the name */ 700 if (IS_ERR(clk)) { 701 dev_err(&client->dev, "clock registration failed\n"); 702 err = PTR_ERR(clk); 703 goto error; 704 } 705 data->dt_clk[i] = clk; 706 } 707 708 /* Register the output clocks */ 709 data->onecell.clk_num = NUMBER_OF_OUTPUTS; 710 data->onecell.clks = data->dt_clk; 711 err = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get, 712 &data->onecell); 713 if (err) 714 dev_err(&client->dev, "unable to add OF clock provider\n"); 715 716 err = 0; 717 718 error: 719 for (i = 0; i < NUMBER_OF_PLLS; ++i) 720 /* clock framework made a copy of the name */ 721 kfree(pll_clk_name[i]); 722 723 return err; 724 } 725 726 static const struct i2c_device_id cdce925_id[] = { 727 { "cdce925", 0 }, 728 { } 729 }; 730 MODULE_DEVICE_TABLE(i2c, cdce925_id); 731 732 static const struct of_device_id clk_cdce925_of_match[] = { 733 { .compatible = "ti,cdce925" }, 734 { }, 735 }; 736 MODULE_DEVICE_TABLE(of, clk_cdce925_of_match); 737 738 static struct i2c_driver cdce925_driver = { 739 .driver = { 740 .name = "cdce925", 741 .of_match_table = of_match_ptr(clk_cdce925_of_match), 742 }, 743 .probe = cdce925_probe, 744 .id_table = cdce925_id, 745 }; 746 module_i2c_driver(cdce925_driver); 747 748 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); 749 MODULE_DESCRIPTION("cdce925 driver"); 750 MODULE_LICENSE("GPL"); 751