1 /* 2 * Driver for TI Dual PLL CDCE925 clock synthesizer 3 * 4 * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1 5 * and Y4/Y5 to PLL2. PLL frequency is set on a first-come-first-serve 6 * basis. Clients can directly request any frequency that the chip can 7 * deliver using the standard clk framework. In addition, the device can 8 * be configured and activated via the devicetree. 9 * 10 * Copyright (C) 2014, Topic Embedded Products 11 * Licenced under GPL 12 */ 13 #include <linux/clk-provider.h> 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/i2c.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 #include <linux/gcd.h> 20 21 /* The chip has 2 PLLs which can be routed through dividers to 5 outputs. 22 * Model this as 2 PLL clocks which are parents to the outputs. 23 */ 24 #define NUMBER_OF_PLLS 2 25 #define NUMBER_OF_OUTPUTS 5 26 27 #define CDCE925_REG_GLOBAL1 0x01 28 #define CDCE925_REG_Y1SPIPDIVH 0x02 29 #define CDCE925_REG_PDIVL 0x03 30 #define CDCE925_REG_XCSEL 0x05 31 /* PLL parameters start at 0x10, steps of 0x10 */ 32 #define CDCE925_OFFSET_PLL 0x10 33 /* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */ 34 #define CDCE925_PLL_MUX_OUTPUTS 0x14 35 #define CDCE925_PLL_MULDIV 0x18 36 37 #define CDCE925_PLL_FREQUENCY_MIN 80000000ul 38 #define CDCE925_PLL_FREQUENCY_MAX 230000000ul 39 struct clk_cdce925_chip; 40 41 struct clk_cdce925_output { 42 struct clk_hw hw; 43 struct clk_cdce925_chip *chip; 44 u8 index; 45 u16 pdiv; /* 1..127 for Y2-Y5; 1..1023 for Y1 */ 46 }; 47 #define to_clk_cdce925_output(_hw) \ 48 container_of(_hw, struct clk_cdce925_output, hw) 49 50 struct clk_cdce925_pll { 51 struct clk_hw hw; 52 struct clk_cdce925_chip *chip; 53 u8 index; 54 u16 m; /* 1..511 */ 55 u16 n; /* 1..4095 */ 56 }; 57 #define to_clk_cdce925_pll(_hw) container_of(_hw, struct clk_cdce925_pll, hw) 58 59 struct clk_cdce925_chip { 60 struct regmap *regmap; 61 struct i2c_client *i2c_client; 62 struct clk_cdce925_pll pll[NUMBER_OF_PLLS]; 63 struct clk_cdce925_output clk[NUMBER_OF_OUTPUTS]; 64 struct clk *dt_clk[NUMBER_OF_OUTPUTS]; 65 struct clk_onecell_data onecell; 66 }; 67 68 /* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */ 69 70 static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate, 71 u16 n, u16 m) 72 { 73 if ((!m || !n) || (m == n)) 74 return parent_rate; /* In bypass mode runs at same frequency */ 75 return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m); 76 } 77 78 static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw, 79 unsigned long parent_rate) 80 { 81 /* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */ 82 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 83 84 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); 85 } 86 87 static void cdce925_pll_find_rate(unsigned long rate, 88 unsigned long parent_rate, u16 *n, u16 *m) 89 { 90 unsigned long un; 91 unsigned long um; 92 unsigned long g; 93 94 if (rate <= parent_rate) { 95 /* Can always deliver parent_rate in bypass mode */ 96 rate = parent_rate; 97 *n = 0; 98 *m = 0; 99 } else { 100 /* In PLL mode, need to apply min/max range */ 101 if (rate < CDCE925_PLL_FREQUENCY_MIN) 102 rate = CDCE925_PLL_FREQUENCY_MIN; 103 else if (rate > CDCE925_PLL_FREQUENCY_MAX) 104 rate = CDCE925_PLL_FREQUENCY_MAX; 105 106 g = gcd(rate, parent_rate); 107 um = parent_rate / g; 108 un = rate / g; 109 /* When outside hw range, reduce to fit (rounding errors) */ 110 while ((un > 4095) || (um > 511)) { 111 un >>= 1; 112 um >>= 1; 113 } 114 if (un == 0) 115 un = 1; 116 if (um == 0) 117 um = 1; 118 119 *n = un; 120 *m = um; 121 } 122 } 123 124 static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate, 125 unsigned long *parent_rate) 126 { 127 u16 n, m; 128 129 cdce925_pll_find_rate(rate, *parent_rate, &n, &m); 130 return (long)cdce925_pll_calculate_rate(*parent_rate, n, m); 131 } 132 133 static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate, 134 unsigned long parent_rate) 135 { 136 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 137 138 if (!rate || (rate == parent_rate)) { 139 data->m = 0; /* Bypass mode */ 140 data->n = 0; 141 return 0; 142 } 143 144 if ((rate < CDCE925_PLL_FREQUENCY_MIN) || 145 (rate > CDCE925_PLL_FREQUENCY_MAX)) { 146 pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate); 147 return -EINVAL; 148 } 149 150 if (rate < parent_rate) { 151 pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__, 152 rate, parent_rate); 153 return -EINVAL; 154 } 155 156 cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); 157 return 0; 158 } 159 160 161 /* calculate p = max(0, 4 - int(log2 (n/m))) */ 162 static u8 cdce925_pll_calc_p(u16 n, u16 m) 163 { 164 u8 p; 165 u16 r = n / m; 166 167 if (r >= 16) 168 return 0; 169 p = 4; 170 while (r > 1) { 171 r >>= 1; 172 --p; 173 } 174 return p; 175 } 176 177 /* Returns VCO range bits for VCO1_0_RANGE */ 178 static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m) 179 { 180 struct clk *parent = clk_get_parent(hw->clk); 181 unsigned long rate = clk_get_rate(parent); 182 183 rate = mult_frac(rate, (unsigned long)n, (unsigned long)m); 184 if (rate >= 175000000) 185 return 0x3; 186 if (rate >= 150000000) 187 return 0x02; 188 if (rate >= 125000000) 189 return 0x01; 190 return 0x00; 191 } 192 193 /* I2C clock, hence everything must happen in (un)prepare because this 194 * may sleep */ 195 static int cdce925_pll_prepare(struct clk_hw *hw) 196 { 197 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 198 u16 n = data->n; 199 u16 m = data->m; 200 u16 r; 201 u8 q; 202 u8 p; 203 u16 nn; 204 u8 pll[4]; /* Bits are spread out over 4 byte registers */ 205 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; 206 unsigned i; 207 208 if ((!m || !n) || (m == n)) { 209 /* Set PLL mux to bypass mode, leave the rest as is */ 210 regmap_update_bits(data->chip->regmap, 211 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); 212 } else { 213 /* According to data sheet: */ 214 /* p = max(0, 4 - int(log2 (n/m))) */ 215 p = cdce925_pll_calc_p(n, m); 216 /* nn = n * 2^p */ 217 nn = n * BIT(p); 218 /* q = int(nn/m) */ 219 q = nn / m; 220 if ((q < 16) || (1 > 64)) { 221 pr_debug("%s invalid q=%d\n", __func__, q); 222 return -EINVAL; 223 } 224 r = nn - (m*q); 225 if (r > 511) { 226 pr_debug("%s invalid r=%d\n", __func__, r); 227 return -EINVAL; 228 } 229 pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__, 230 n, m, p, q, r); 231 /* encode into register bits */ 232 pll[0] = n >> 4; 233 pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F); 234 pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07); 235 pll[3] = ((q & 0x07) << 5) | (p << 2) | 236 cdce925_pll_calc_range_bits(hw, n, m); 237 /* Write to registers */ 238 for (i = 0; i < ARRAY_SIZE(pll); ++i) 239 regmap_write(data->chip->regmap, 240 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); 241 /* Enable PLL */ 242 regmap_update_bits(data->chip->regmap, 243 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00); 244 } 245 246 return 0; 247 } 248 249 static void cdce925_pll_unprepare(struct clk_hw *hw) 250 { 251 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 252 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; 253 254 regmap_update_bits(data->chip->regmap, 255 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); 256 } 257 258 static const struct clk_ops cdce925_pll_ops = { 259 .prepare = cdce925_pll_prepare, 260 .unprepare = cdce925_pll_unprepare, 261 .recalc_rate = cdce925_pll_recalc_rate, 262 .round_rate = cdce925_pll_round_rate, 263 .set_rate = cdce925_pll_set_rate, 264 }; 265 266 267 static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) 268 { 269 switch (data->index) { 270 case 0: 271 regmap_update_bits(data->chip->regmap, 272 CDCE925_REG_Y1SPIPDIVH, 273 0x03, (pdiv >> 8) & 0x03); 274 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); 275 break; 276 case 1: 277 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); 278 break; 279 case 2: 280 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); 281 break; 282 case 3: 283 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); 284 break; 285 case 4: 286 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); 287 break; 288 } 289 } 290 291 static void cdce925_clk_activate(struct clk_cdce925_output *data) 292 { 293 switch (data->index) { 294 case 0: 295 regmap_update_bits(data->chip->regmap, 296 CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c); 297 break; 298 case 1: 299 case 2: 300 regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03); 301 break; 302 case 3: 303 case 4: 304 regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03); 305 break; 306 } 307 } 308 309 static int cdce925_clk_prepare(struct clk_hw *hw) 310 { 311 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 312 313 cdce925_clk_set_pdiv(data, data->pdiv); 314 cdce925_clk_activate(data); 315 return 0; 316 } 317 318 static void cdce925_clk_unprepare(struct clk_hw *hw) 319 { 320 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 321 322 /* Disable clock by setting divider to "0" */ 323 cdce925_clk_set_pdiv(data, 0); 324 } 325 326 static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw, 327 unsigned long parent_rate) 328 { 329 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 330 331 if (data->pdiv) 332 return parent_rate / data->pdiv; 333 return 0; 334 } 335 336 static u16 cdce925_calc_divider(unsigned long rate, 337 unsigned long parent_rate) 338 { 339 unsigned long divider; 340 341 if (!rate) 342 return 0; 343 if (rate >= parent_rate) 344 return 1; 345 346 divider = DIV_ROUND_CLOSEST(parent_rate, rate); 347 if (divider > 0x7F) 348 divider = 0x7F; 349 350 return (u16)divider; 351 } 352 353 static unsigned long cdce925_clk_best_parent_rate( 354 struct clk_hw *hw, unsigned long rate) 355 { 356 struct clk *pll = clk_get_parent(hw->clk); 357 struct clk *root = clk_get_parent(pll); 358 unsigned long root_rate = clk_get_rate(root); 359 unsigned long best_rate_error = rate; 360 u16 pdiv_min; 361 u16 pdiv_max; 362 u16 pdiv_best; 363 u16 pdiv_now; 364 365 if (root_rate % rate == 0) 366 return root_rate; /* Don't need the PLL, use bypass */ 367 368 pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate)); 369 pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate); 370 371 if (pdiv_min > pdiv_max) 372 return 0; /* No can do? */ 373 374 pdiv_best = pdiv_min; 375 for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) { 376 unsigned long target_rate = rate * pdiv_now; 377 long pll_rate = clk_round_rate(pll, target_rate); 378 unsigned long actual_rate; 379 unsigned long rate_error; 380 381 if (pll_rate <= 0) 382 continue; 383 actual_rate = pll_rate / pdiv_now; 384 rate_error = abs((long)actual_rate - (long)rate); 385 if (rate_error < best_rate_error) { 386 pdiv_best = pdiv_now; 387 best_rate_error = rate_error; 388 } 389 /* TODO: Consider PLL frequency based on smaller n/m values 390 * and pick the better one if the error is equal */ 391 } 392 393 return rate * pdiv_best; 394 } 395 396 static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate, 397 unsigned long *parent_rate) 398 { 399 unsigned long l_parent_rate = *parent_rate; 400 u16 divider = cdce925_calc_divider(rate, l_parent_rate); 401 402 if (l_parent_rate / divider != rate) { 403 l_parent_rate = cdce925_clk_best_parent_rate(hw, rate); 404 divider = cdce925_calc_divider(rate, l_parent_rate); 405 *parent_rate = l_parent_rate; 406 } 407 408 if (divider) 409 return (long)(l_parent_rate / divider); 410 return 0; 411 } 412 413 static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate, 414 unsigned long parent_rate) 415 { 416 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 417 418 data->pdiv = cdce925_calc_divider(rate, parent_rate); 419 420 return 0; 421 } 422 423 static const struct clk_ops cdce925_clk_ops = { 424 .prepare = cdce925_clk_prepare, 425 .unprepare = cdce925_clk_unprepare, 426 .recalc_rate = cdce925_clk_recalc_rate, 427 .round_rate = cdce925_clk_round_rate, 428 .set_rate = cdce925_clk_set_rate, 429 }; 430 431 432 static u16 cdce925_y1_calc_divider(unsigned long rate, 433 unsigned long parent_rate) 434 { 435 unsigned long divider; 436 437 if (!rate) 438 return 0; 439 if (rate >= parent_rate) 440 return 1; 441 442 divider = DIV_ROUND_CLOSEST(parent_rate, rate); 443 if (divider > 0x3FF) /* Y1 has 10-bit divider */ 444 divider = 0x3FF; 445 446 return (u16)divider; 447 } 448 449 static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate, 450 unsigned long *parent_rate) 451 { 452 unsigned long l_parent_rate = *parent_rate; 453 u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate); 454 455 if (divider) 456 return (long)(l_parent_rate / divider); 457 return 0; 458 } 459 460 static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate, 461 unsigned long parent_rate) 462 { 463 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 464 465 data->pdiv = cdce925_y1_calc_divider(rate, parent_rate); 466 467 return 0; 468 } 469 470 static const struct clk_ops cdce925_clk_y1_ops = { 471 .prepare = cdce925_clk_prepare, 472 .unprepare = cdce925_clk_unprepare, 473 .recalc_rate = cdce925_clk_recalc_rate, 474 .round_rate = cdce925_clk_y1_round_rate, 475 .set_rate = cdce925_clk_y1_set_rate, 476 }; 477 478 479 static struct regmap_config cdce925_regmap_config = { 480 .name = "configuration0", 481 .reg_bits = 8, 482 .val_bits = 8, 483 .cache_type = REGCACHE_RBTREE, 484 .max_register = 0x2F, 485 }; 486 487 #define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00 488 #define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80 489 490 static int cdce925_regmap_i2c_write( 491 void *context, const void *data, size_t count) 492 { 493 struct device *dev = context; 494 struct i2c_client *i2c = to_i2c_client(dev); 495 int ret; 496 u8 reg_data[2]; 497 498 if (count != 2) 499 return -ENOTSUPP; 500 501 /* First byte is command code */ 502 reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0]; 503 reg_data[1] = ((u8 *)data)[1]; 504 505 dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count, 506 reg_data[0], reg_data[1]); 507 508 ret = i2c_master_send(i2c, reg_data, count); 509 if (likely(ret == count)) 510 return 0; 511 else if (ret < 0) 512 return ret; 513 else 514 return -EIO; 515 } 516 517 static int cdce925_regmap_i2c_read(void *context, 518 const void *reg, size_t reg_size, void *val, size_t val_size) 519 { 520 struct device *dev = context; 521 struct i2c_client *i2c = to_i2c_client(dev); 522 struct i2c_msg xfer[2]; 523 int ret; 524 u8 reg_data[2]; 525 526 if (reg_size != 1) 527 return -ENOTSUPP; 528 529 xfer[0].addr = i2c->addr; 530 xfer[0].flags = 0; 531 xfer[0].buf = reg_data; 532 if (val_size == 1) { 533 reg_data[0] = 534 CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0]; 535 xfer[0].len = 1; 536 } else { 537 reg_data[0] = 538 CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0]; 539 reg_data[1] = val_size; 540 xfer[0].len = 2; 541 } 542 543 xfer[1].addr = i2c->addr; 544 xfer[1].flags = I2C_M_RD; 545 xfer[1].len = val_size; 546 xfer[1].buf = val; 547 548 ret = i2c_transfer(i2c->adapter, xfer, 2); 549 if (likely(ret == 2)) { 550 dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__, 551 reg_size, val_size, reg_data[0], *((u8 *)val)); 552 return 0; 553 } else if (ret < 0) 554 return ret; 555 else 556 return -EIO; 557 } 558 559 /* The CDCE925 uses a funky way to read/write registers. Bulk mode is 560 * just weird, so just use the single byte mode exclusively. */ 561 static struct regmap_bus regmap_cdce925_bus = { 562 .write = cdce925_regmap_i2c_write, 563 .read = cdce925_regmap_i2c_read, 564 }; 565 566 static int cdce925_probe(struct i2c_client *client, 567 const struct i2c_device_id *id) 568 { 569 struct clk_cdce925_chip *data; 570 struct device_node *node = client->dev.of_node; 571 const char *parent_name; 572 const char *pll_clk_name[NUMBER_OF_PLLS] = {NULL,}; 573 struct clk_init_data init; 574 struct clk *clk; 575 u32 value; 576 int i; 577 int err; 578 struct device_node *np_output; 579 char child_name[6]; 580 581 dev_dbg(&client->dev, "%s\n", __func__); 582 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); 583 if (!data) 584 return -ENOMEM; 585 586 data->i2c_client = client; 587 data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus, 588 &client->dev, &cdce925_regmap_config); 589 if (IS_ERR(data->regmap)) { 590 dev_err(&client->dev, "failed to allocate register map\n"); 591 return PTR_ERR(data->regmap); 592 } 593 i2c_set_clientdata(client, data); 594 595 parent_name = of_clk_get_parent_name(node, 0); 596 if (!parent_name) { 597 dev_err(&client->dev, "missing parent clock\n"); 598 return -ENODEV; 599 } 600 dev_dbg(&client->dev, "parent is: %s\n", parent_name); 601 602 if (of_property_read_u32(node, "xtal-load-pf", &value) == 0) 603 regmap_write(data->regmap, 604 CDCE925_REG_XCSEL, (value << 3) & 0xF8); 605 /* PWDN bit */ 606 regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0); 607 608 /* Set input source for Y1 to be the XTAL */ 609 regmap_update_bits(data->regmap, 0x02, BIT(7), 0); 610 611 init.ops = &cdce925_pll_ops; 612 init.flags = 0; 613 init.parent_names = &parent_name; 614 init.num_parents = parent_name ? 1 : 0; 615 616 /* Register PLL clocks */ 617 for (i = 0; i < NUMBER_OF_PLLS; ++i) { 618 pll_clk_name[i] = kasprintf(GFP_KERNEL, "%s.pll%d", 619 client->dev.of_node->name, i); 620 init.name = pll_clk_name[i]; 621 data->pll[i].chip = data; 622 data->pll[i].hw.init = &init; 623 data->pll[i].index = i; 624 clk = devm_clk_register(&client->dev, &data->pll[i].hw); 625 if (IS_ERR(clk)) { 626 dev_err(&client->dev, "Failed register PLL %d\n", i); 627 err = PTR_ERR(clk); 628 goto error; 629 } 630 sprintf(child_name, "PLL%d", i+1); 631 np_output = of_get_child_by_name(node, child_name); 632 if (!np_output) 633 continue; 634 if (!of_property_read_u32(np_output, 635 "clock-frequency", &value)) { 636 err = clk_set_rate(clk, value); 637 if (err) 638 dev_err(&client->dev, 639 "unable to set PLL frequency %ud\n", 640 value); 641 } 642 if (!of_property_read_u32(np_output, 643 "spread-spectrum", &value)) { 644 u8 flag = of_property_read_bool(np_output, 645 "spread-spectrum-center") ? 0x80 : 0x00; 646 regmap_update_bits(data->regmap, 647 0x16 + (i*CDCE925_OFFSET_PLL), 648 0x80, flag); 649 regmap_update_bits(data->regmap, 650 0x12 + (i*CDCE925_OFFSET_PLL), 651 0x07, value & 0x07); 652 } 653 } 654 655 /* Register output clock Y1 */ 656 init.ops = &cdce925_clk_y1_ops; 657 init.flags = 0; 658 init.num_parents = 1; 659 init.parent_names = &parent_name; /* Mux Y1 to input */ 660 init.name = kasprintf(GFP_KERNEL, "%s.Y1", client->dev.of_node->name); 661 data->clk[0].chip = data; 662 data->clk[0].hw.init = &init; 663 data->clk[0].index = 0; 664 data->clk[0].pdiv = 1; 665 clk = devm_clk_register(&client->dev, &data->clk[0].hw); 666 kfree(init.name); /* clock framework made a copy of the name */ 667 if (IS_ERR(clk)) { 668 dev_err(&client->dev, "clock registration Y1 failed\n"); 669 err = PTR_ERR(clk); 670 goto error; 671 } 672 data->dt_clk[0] = clk; 673 674 /* Register output clocks Y2 .. Y5*/ 675 init.ops = &cdce925_clk_ops; 676 init.flags = CLK_SET_RATE_PARENT; 677 init.num_parents = 1; 678 for (i = 1; i < NUMBER_OF_OUTPUTS; ++i) { 679 init.name = kasprintf(GFP_KERNEL, "%s.Y%d", 680 client->dev.of_node->name, i+1); 681 data->clk[i].chip = data; 682 data->clk[i].hw.init = &init; 683 data->clk[i].index = i; 684 data->clk[i].pdiv = 1; 685 switch (i) { 686 case 1: 687 case 2: 688 /* Mux Y2/3 to PLL1 */ 689 init.parent_names = &pll_clk_name[0]; 690 break; 691 case 3: 692 case 4: 693 /* Mux Y4/5 to PLL2 */ 694 init.parent_names = &pll_clk_name[1]; 695 break; 696 } 697 clk = devm_clk_register(&client->dev, &data->clk[i].hw); 698 kfree(init.name); /* clock framework made a copy of the name */ 699 if (IS_ERR(clk)) { 700 dev_err(&client->dev, "clock registration failed\n"); 701 err = PTR_ERR(clk); 702 goto error; 703 } 704 data->dt_clk[i] = clk; 705 } 706 707 /* Register the output clocks */ 708 data->onecell.clk_num = NUMBER_OF_OUTPUTS; 709 data->onecell.clks = data->dt_clk; 710 err = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get, 711 &data->onecell); 712 if (err) 713 dev_err(&client->dev, "unable to add OF clock provider\n"); 714 715 err = 0; 716 717 error: 718 for (i = 0; i < NUMBER_OF_PLLS; ++i) 719 /* clock framework made a copy of the name */ 720 kfree(pll_clk_name[i]); 721 722 return err; 723 } 724 725 static const struct i2c_device_id cdce925_id[] = { 726 { "cdce925", 0 }, 727 { } 728 }; 729 MODULE_DEVICE_TABLE(i2c, cdce925_id); 730 731 static const struct of_device_id clk_cdce925_of_match[] = { 732 { .compatible = "ti,cdce925" }, 733 { }, 734 }; 735 MODULE_DEVICE_TABLE(of, clk_cdce925_of_match); 736 737 static struct i2c_driver cdce925_driver = { 738 .driver = { 739 .name = "cdce925", 740 .of_match_table = of_match_ptr(clk_cdce925_of_match), 741 }, 742 .probe = cdce925_probe, 743 .id_table = cdce925_id, 744 }; 745 module_i2c_driver(cdce925_driver); 746 747 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); 748 MODULE_DESCRIPTION("cdce925 driver"); 749 MODULE_LICENSE("GPL"); 750