1 /* 2 * Driver for TI Multi PLL CDCE913/925/937/949 clock synthesizer 3 * 4 * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1, 5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve 6 * basis. Clients can directly request any frequency that the chip can 7 * deliver using the standard clk framework. In addition, the device can 8 * be configured and activated via the devicetree. 9 * 10 * Copyright (C) 2014, Topic Embedded Products 11 * Licenced under GPL 12 */ 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/delay.h> 16 #include <linux/module.h> 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/slab.h> 21 #include <linux/gcd.h> 22 23 /* Each chip has different number of PLLs and outputs, for example: 24 * The CECE925 has 2 PLLs which can be routed through dividers to 5 outputs. 25 * Model this as 2 PLL clocks which are parents to the outputs. 26 */ 27 28 struct clk_cdce925_chip_info { 29 int num_plls; 30 int num_outputs; 31 }; 32 33 #define MAX_NUMBER_OF_PLLS 4 34 #define MAX_NUMBER_OF_OUTPUTS 9 35 36 #define CDCE925_REG_GLOBAL1 0x01 37 #define CDCE925_REG_Y1SPIPDIVH 0x02 38 #define CDCE925_REG_PDIVL 0x03 39 #define CDCE925_REG_XCSEL 0x05 40 /* PLL parameters start at 0x10, steps of 0x10 */ 41 #define CDCE925_OFFSET_PLL 0x10 42 /* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */ 43 #define CDCE925_PLL_MUX_OUTPUTS 0x14 44 #define CDCE925_PLL_MULDIV 0x18 45 46 #define CDCE925_PLL_FREQUENCY_MIN 80000000ul 47 #define CDCE925_PLL_FREQUENCY_MAX 230000000ul 48 struct clk_cdce925_chip; 49 50 struct clk_cdce925_output { 51 struct clk_hw hw; 52 struct clk_cdce925_chip *chip; 53 u8 index; 54 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */ 55 }; 56 #define to_clk_cdce925_output(_hw) \ 57 container_of(_hw, struct clk_cdce925_output, hw) 58 59 struct clk_cdce925_pll { 60 struct clk_hw hw; 61 struct clk_cdce925_chip *chip; 62 u8 index; 63 u16 m; /* 1..511 */ 64 u16 n; /* 1..4095 */ 65 }; 66 #define to_clk_cdce925_pll(_hw) container_of(_hw, struct clk_cdce925_pll, hw) 67 68 struct clk_cdce925_chip { 69 struct regmap *regmap; 70 struct i2c_client *i2c_client; 71 const struct clk_cdce925_chip_info *chip_info; 72 struct clk_cdce925_pll pll[MAX_NUMBER_OF_PLLS]; 73 struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS]; 74 }; 75 76 /* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */ 77 78 static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate, 79 u16 n, u16 m) 80 { 81 if ((!m || !n) || (m == n)) 82 return parent_rate; /* In bypass mode runs at same frequency */ 83 return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m); 84 } 85 86 static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw, 87 unsigned long parent_rate) 88 { 89 /* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */ 90 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 91 92 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); 93 } 94 95 static void cdce925_pll_find_rate(unsigned long rate, 96 unsigned long parent_rate, u16 *n, u16 *m) 97 { 98 unsigned long un; 99 unsigned long um; 100 unsigned long g; 101 102 if (rate <= parent_rate) { 103 /* Can always deliver parent_rate in bypass mode */ 104 rate = parent_rate; 105 *n = 0; 106 *m = 0; 107 } else { 108 /* In PLL mode, need to apply min/max range */ 109 if (rate < CDCE925_PLL_FREQUENCY_MIN) 110 rate = CDCE925_PLL_FREQUENCY_MIN; 111 else if (rate > CDCE925_PLL_FREQUENCY_MAX) 112 rate = CDCE925_PLL_FREQUENCY_MAX; 113 114 g = gcd(rate, parent_rate); 115 um = parent_rate / g; 116 un = rate / g; 117 /* When outside hw range, reduce to fit (rounding errors) */ 118 while ((un > 4095) || (um > 511)) { 119 un >>= 1; 120 um >>= 1; 121 } 122 if (un == 0) 123 un = 1; 124 if (um == 0) 125 um = 1; 126 127 *n = un; 128 *m = um; 129 } 130 } 131 132 static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate, 133 unsigned long *parent_rate) 134 { 135 u16 n, m; 136 137 cdce925_pll_find_rate(rate, *parent_rate, &n, &m); 138 return (long)cdce925_pll_calculate_rate(*parent_rate, n, m); 139 } 140 141 static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate, 142 unsigned long parent_rate) 143 { 144 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 145 146 if (!rate || (rate == parent_rate)) { 147 data->m = 0; /* Bypass mode */ 148 data->n = 0; 149 return 0; 150 } 151 152 if ((rate < CDCE925_PLL_FREQUENCY_MIN) || 153 (rate > CDCE925_PLL_FREQUENCY_MAX)) { 154 pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate); 155 return -EINVAL; 156 } 157 158 if (rate < parent_rate) { 159 pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__, 160 rate, parent_rate); 161 return -EINVAL; 162 } 163 164 cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); 165 return 0; 166 } 167 168 169 /* calculate p = max(0, 4 - int(log2 (n/m))) */ 170 static u8 cdce925_pll_calc_p(u16 n, u16 m) 171 { 172 u8 p; 173 u16 r = n / m; 174 175 if (r >= 16) 176 return 0; 177 p = 4; 178 while (r > 1) { 179 r >>= 1; 180 --p; 181 } 182 return p; 183 } 184 185 /* Returns VCO range bits for VCO1_0_RANGE */ 186 static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m) 187 { 188 struct clk *parent = clk_get_parent(hw->clk); 189 unsigned long rate = clk_get_rate(parent); 190 191 rate = mult_frac(rate, (unsigned long)n, (unsigned long)m); 192 if (rate >= 175000000) 193 return 0x3; 194 if (rate >= 150000000) 195 return 0x02; 196 if (rate >= 125000000) 197 return 0x01; 198 return 0x00; 199 } 200 201 /* I2C clock, hence everything must happen in (un)prepare because this 202 * may sleep */ 203 static int cdce925_pll_prepare(struct clk_hw *hw) 204 { 205 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 206 u16 n = data->n; 207 u16 m = data->m; 208 u16 r; 209 u8 q; 210 u8 p; 211 u16 nn; 212 u8 pll[4]; /* Bits are spread out over 4 byte registers */ 213 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; 214 unsigned i; 215 216 if ((!m || !n) || (m == n)) { 217 /* Set PLL mux to bypass mode, leave the rest as is */ 218 regmap_update_bits(data->chip->regmap, 219 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); 220 } else { 221 /* According to data sheet: */ 222 /* p = max(0, 4 - int(log2 (n/m))) */ 223 p = cdce925_pll_calc_p(n, m); 224 /* nn = n * 2^p */ 225 nn = n * BIT(p); 226 /* q = int(nn/m) */ 227 q = nn / m; 228 if ((q < 16) || (q > 63)) { 229 pr_debug("%s invalid q=%d\n", __func__, q); 230 return -EINVAL; 231 } 232 r = nn - (m*q); 233 if (r > 511) { 234 pr_debug("%s invalid r=%d\n", __func__, r); 235 return -EINVAL; 236 } 237 pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__, 238 n, m, p, q, r); 239 /* encode into register bits */ 240 pll[0] = n >> 4; 241 pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F); 242 pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07); 243 pll[3] = ((q & 0x07) << 5) | (p << 2) | 244 cdce925_pll_calc_range_bits(hw, n, m); 245 /* Write to registers */ 246 for (i = 0; i < ARRAY_SIZE(pll); ++i) 247 regmap_write(data->chip->regmap, 248 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); 249 /* Enable PLL */ 250 regmap_update_bits(data->chip->regmap, 251 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00); 252 } 253 254 return 0; 255 } 256 257 static void cdce925_pll_unprepare(struct clk_hw *hw) 258 { 259 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 260 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; 261 262 regmap_update_bits(data->chip->regmap, 263 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); 264 } 265 266 static const struct clk_ops cdce925_pll_ops = { 267 .prepare = cdce925_pll_prepare, 268 .unprepare = cdce925_pll_unprepare, 269 .recalc_rate = cdce925_pll_recalc_rate, 270 .round_rate = cdce925_pll_round_rate, 271 .set_rate = cdce925_pll_set_rate, 272 }; 273 274 275 static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) 276 { 277 switch (data->index) { 278 case 0: 279 regmap_update_bits(data->chip->regmap, 280 CDCE925_REG_Y1SPIPDIVH, 281 0x03, (pdiv >> 8) & 0x03); 282 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); 283 break; 284 case 1: 285 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); 286 break; 287 case 2: 288 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); 289 break; 290 case 3: 291 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); 292 break; 293 case 4: 294 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); 295 break; 296 case 5: 297 regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv); 298 break; 299 case 6: 300 regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv); 301 break; 302 case 7: 303 regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv); 304 break; 305 case 8: 306 regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv); 307 break; 308 } 309 } 310 311 static void cdce925_clk_activate(struct clk_cdce925_output *data) 312 { 313 switch (data->index) { 314 case 0: 315 regmap_update_bits(data->chip->regmap, 316 CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c); 317 break; 318 case 1: 319 case 2: 320 regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03); 321 break; 322 case 3: 323 case 4: 324 regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03); 325 break; 326 case 5: 327 case 6: 328 regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03); 329 break; 330 case 7: 331 case 8: 332 regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03); 333 break; 334 } 335 } 336 337 static int cdce925_clk_prepare(struct clk_hw *hw) 338 { 339 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 340 341 cdce925_clk_set_pdiv(data, data->pdiv); 342 cdce925_clk_activate(data); 343 return 0; 344 } 345 346 static void cdce925_clk_unprepare(struct clk_hw *hw) 347 { 348 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 349 350 /* Disable clock by setting divider to "0" */ 351 cdce925_clk_set_pdiv(data, 0); 352 } 353 354 static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw, 355 unsigned long parent_rate) 356 { 357 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 358 359 if (data->pdiv) 360 return parent_rate / data->pdiv; 361 return 0; 362 } 363 364 static u16 cdce925_calc_divider(unsigned long rate, 365 unsigned long parent_rate) 366 { 367 unsigned long divider; 368 369 if (!rate) 370 return 0; 371 if (rate >= parent_rate) 372 return 1; 373 374 divider = DIV_ROUND_CLOSEST(parent_rate, rate); 375 if (divider > 0x7F) 376 divider = 0x7F; 377 378 return (u16)divider; 379 } 380 381 static unsigned long cdce925_clk_best_parent_rate( 382 struct clk_hw *hw, unsigned long rate) 383 { 384 struct clk *pll = clk_get_parent(hw->clk); 385 struct clk *root = clk_get_parent(pll); 386 unsigned long root_rate = clk_get_rate(root); 387 unsigned long best_rate_error = rate; 388 u16 pdiv_min; 389 u16 pdiv_max; 390 u16 pdiv_best; 391 u16 pdiv_now; 392 393 if (root_rate % rate == 0) 394 return root_rate; /* Don't need the PLL, use bypass */ 395 396 pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate)); 397 pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate); 398 399 if (pdiv_min > pdiv_max) 400 return 0; /* No can do? */ 401 402 pdiv_best = pdiv_min; 403 for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) { 404 unsigned long target_rate = rate * pdiv_now; 405 long pll_rate = clk_round_rate(pll, target_rate); 406 unsigned long actual_rate; 407 unsigned long rate_error; 408 409 if (pll_rate <= 0) 410 continue; 411 actual_rate = pll_rate / pdiv_now; 412 rate_error = abs((long)actual_rate - (long)rate); 413 if (rate_error < best_rate_error) { 414 pdiv_best = pdiv_now; 415 best_rate_error = rate_error; 416 } 417 /* TODO: Consider PLL frequency based on smaller n/m values 418 * and pick the better one if the error is equal */ 419 } 420 421 return rate * pdiv_best; 422 } 423 424 static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate, 425 unsigned long *parent_rate) 426 { 427 unsigned long l_parent_rate = *parent_rate; 428 u16 divider = cdce925_calc_divider(rate, l_parent_rate); 429 430 if (l_parent_rate / divider != rate) { 431 l_parent_rate = cdce925_clk_best_parent_rate(hw, rate); 432 divider = cdce925_calc_divider(rate, l_parent_rate); 433 *parent_rate = l_parent_rate; 434 } 435 436 if (divider) 437 return (long)(l_parent_rate / divider); 438 return 0; 439 } 440 441 static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate, 442 unsigned long parent_rate) 443 { 444 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 445 446 data->pdiv = cdce925_calc_divider(rate, parent_rate); 447 448 return 0; 449 } 450 451 static const struct clk_ops cdce925_clk_ops = { 452 .prepare = cdce925_clk_prepare, 453 .unprepare = cdce925_clk_unprepare, 454 .recalc_rate = cdce925_clk_recalc_rate, 455 .round_rate = cdce925_clk_round_rate, 456 .set_rate = cdce925_clk_set_rate, 457 }; 458 459 460 static u16 cdce925_y1_calc_divider(unsigned long rate, 461 unsigned long parent_rate) 462 { 463 unsigned long divider; 464 465 if (!rate) 466 return 0; 467 if (rate >= parent_rate) 468 return 1; 469 470 divider = DIV_ROUND_CLOSEST(parent_rate, rate); 471 if (divider > 0x3FF) /* Y1 has 10-bit divider */ 472 divider = 0x3FF; 473 474 return (u16)divider; 475 } 476 477 static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate, 478 unsigned long *parent_rate) 479 { 480 unsigned long l_parent_rate = *parent_rate; 481 u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate); 482 483 if (divider) 484 return (long)(l_parent_rate / divider); 485 return 0; 486 } 487 488 static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate, 489 unsigned long parent_rate) 490 { 491 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 492 493 data->pdiv = cdce925_y1_calc_divider(rate, parent_rate); 494 495 return 0; 496 } 497 498 static const struct clk_ops cdce925_clk_y1_ops = { 499 .prepare = cdce925_clk_prepare, 500 .unprepare = cdce925_clk_unprepare, 501 .recalc_rate = cdce925_clk_recalc_rate, 502 .round_rate = cdce925_clk_y1_round_rate, 503 .set_rate = cdce925_clk_y1_set_rate, 504 }; 505 506 #define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00 507 #define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80 508 509 static int cdce925_regmap_i2c_write( 510 void *context, const void *data, size_t count) 511 { 512 struct device *dev = context; 513 struct i2c_client *i2c = to_i2c_client(dev); 514 int ret; 515 u8 reg_data[2]; 516 517 if (count != 2) 518 return -ENOTSUPP; 519 520 /* First byte is command code */ 521 reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0]; 522 reg_data[1] = ((u8 *)data)[1]; 523 524 dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count, 525 reg_data[0], reg_data[1]); 526 527 ret = i2c_master_send(i2c, reg_data, count); 528 if (likely(ret == count)) 529 return 0; 530 else if (ret < 0) 531 return ret; 532 else 533 return -EIO; 534 } 535 536 static int cdce925_regmap_i2c_read(void *context, 537 const void *reg, size_t reg_size, void *val, size_t val_size) 538 { 539 struct device *dev = context; 540 struct i2c_client *i2c = to_i2c_client(dev); 541 struct i2c_msg xfer[2]; 542 int ret; 543 u8 reg_data[2]; 544 545 if (reg_size != 1) 546 return -ENOTSUPP; 547 548 xfer[0].addr = i2c->addr; 549 xfer[0].flags = 0; 550 xfer[0].buf = reg_data; 551 if (val_size == 1) { 552 reg_data[0] = 553 CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0]; 554 xfer[0].len = 1; 555 } else { 556 reg_data[0] = 557 CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0]; 558 reg_data[1] = val_size; 559 xfer[0].len = 2; 560 } 561 562 xfer[1].addr = i2c->addr; 563 xfer[1].flags = I2C_M_RD; 564 xfer[1].len = val_size; 565 xfer[1].buf = val; 566 567 ret = i2c_transfer(i2c->adapter, xfer, 2); 568 if (likely(ret == 2)) { 569 dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__, 570 reg_size, val_size, reg_data[0], *((u8 *)val)); 571 return 0; 572 } else if (ret < 0) 573 return ret; 574 else 575 return -EIO; 576 } 577 578 static struct clk_hw * 579 of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data) 580 { 581 struct clk_cdce925_chip *data = _data; 582 unsigned int idx = clkspec->args[0]; 583 584 if (idx >= ARRAY_SIZE(data->clk)) { 585 pr_err("%s: invalid index %u\n", __func__, idx); 586 return ERR_PTR(-EINVAL); 587 } 588 589 return &data->clk[idx].hw; 590 } 591 592 static int cdce925_regulator_enable(struct device *dev, const char *name) 593 { 594 int err; 595 596 err = devm_regulator_get_enable(dev, name); 597 if (err) 598 dev_err_probe(dev, err, "Failed to enable %s:\n", name); 599 600 return err; 601 } 602 603 /* The CDCE925 uses a funky way to read/write registers. Bulk mode is 604 * just weird, so just use the single byte mode exclusively. */ 605 static struct regmap_bus regmap_cdce925_bus = { 606 .write = cdce925_regmap_i2c_write, 607 .read = cdce925_regmap_i2c_read, 608 }; 609 610 static int cdce925_probe(struct i2c_client *client) 611 { 612 struct clk_cdce925_chip *data; 613 struct device_node *node = client->dev.of_node; 614 const char *parent_name; 615 const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,}; 616 struct clk_init_data init; 617 u32 value; 618 int i; 619 int err; 620 struct device_node *np_output; 621 char child_name[6]; 622 struct regmap_config config = { 623 .name = "configuration0", 624 .reg_bits = 8, 625 .val_bits = 8, 626 .cache_type = REGCACHE_MAPLE, 627 }; 628 629 dev_dbg(&client->dev, "%s\n", __func__); 630 631 err = cdce925_regulator_enable(&client->dev, "vdd"); 632 if (err) 633 return err; 634 635 err = cdce925_regulator_enable(&client->dev, "vddout"); 636 if (err) 637 return err; 638 639 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); 640 if (!data) 641 return -ENOMEM; 642 643 data->i2c_client = client; 644 data->chip_info = i2c_get_match_data(client); 645 config.max_register = CDCE925_OFFSET_PLL + 646 data->chip_info->num_plls * 0x10 - 1; 647 data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus, 648 &client->dev, &config); 649 if (IS_ERR(data->regmap)) { 650 dev_err(&client->dev, "failed to allocate register map\n"); 651 return PTR_ERR(data->regmap); 652 } 653 i2c_set_clientdata(client, data); 654 655 parent_name = of_clk_get_parent_name(node, 0); 656 if (!parent_name) { 657 dev_err(&client->dev, "missing parent clock\n"); 658 return -ENODEV; 659 } 660 dev_dbg(&client->dev, "parent is: %s\n", parent_name); 661 662 if (of_property_read_u32(node, "xtal-load-pf", &value) == 0) 663 regmap_write(data->regmap, 664 CDCE925_REG_XCSEL, (value << 3) & 0xF8); 665 /* PWDN bit */ 666 regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0); 667 668 /* Set input source for Y1 to be the XTAL */ 669 regmap_update_bits(data->regmap, 0x02, BIT(7), 0); 670 671 init.ops = &cdce925_pll_ops; 672 init.flags = 0; 673 init.parent_names = &parent_name; 674 init.num_parents = 1; 675 676 /* Register PLL clocks */ 677 for (i = 0; i < data->chip_info->num_plls; ++i) { 678 pll_clk_name[i] = kasprintf(GFP_KERNEL, "%pOFn.pll%d", 679 client->dev.of_node, i); 680 if (!pll_clk_name[i]) { 681 err = -ENOMEM; 682 goto error; 683 } 684 init.name = pll_clk_name[i]; 685 data->pll[i].chip = data; 686 data->pll[i].hw.init = &init; 687 data->pll[i].index = i; 688 err = devm_clk_hw_register(&client->dev, &data->pll[i].hw); 689 if (err) { 690 dev_err(&client->dev, "Failed register PLL %d\n", i); 691 goto error; 692 } 693 sprintf(child_name, "PLL%d", i+1); 694 np_output = of_get_child_by_name(node, child_name); 695 if (!np_output) 696 continue; 697 if (!of_property_read_u32(np_output, 698 "clock-frequency", &value)) { 699 err = clk_set_rate(data->pll[i].hw.clk, value); 700 if (err) 701 dev_err(&client->dev, 702 "unable to set PLL frequency %ud\n", 703 value); 704 } 705 if (!of_property_read_u32(np_output, 706 "spread-spectrum", &value)) { 707 u8 flag = of_property_read_bool(np_output, 708 "spread-spectrum-center") ? 0x80 : 0x00; 709 regmap_update_bits(data->regmap, 710 0x16 + (i*CDCE925_OFFSET_PLL), 711 0x80, flag); 712 regmap_update_bits(data->regmap, 713 0x12 + (i*CDCE925_OFFSET_PLL), 714 0x07, value & 0x07); 715 } 716 of_node_put(np_output); 717 } 718 719 /* Register output clock Y1 */ 720 init.ops = &cdce925_clk_y1_ops; 721 init.flags = 0; 722 init.num_parents = 1; 723 init.parent_names = &parent_name; /* Mux Y1 to input */ 724 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node); 725 if (!init.name) { 726 err = -ENOMEM; 727 goto error; 728 } 729 data->clk[0].chip = data; 730 data->clk[0].hw.init = &init; 731 data->clk[0].index = 0; 732 data->clk[0].pdiv = 1; 733 err = devm_clk_hw_register(&client->dev, &data->clk[0].hw); 734 kfree(init.name); /* clock framework made a copy of the name */ 735 if (err) { 736 dev_err(&client->dev, "clock registration Y1 failed\n"); 737 goto error; 738 } 739 740 /* Register output clocks Y2 .. Y5*/ 741 init.ops = &cdce925_clk_ops; 742 init.flags = CLK_SET_RATE_PARENT; 743 init.num_parents = 1; 744 for (i = 1; i < data->chip_info->num_outputs; ++i) { 745 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y%d", 746 client->dev.of_node, i+1); 747 if (!init.name) { 748 err = -ENOMEM; 749 goto error; 750 } 751 data->clk[i].chip = data; 752 data->clk[i].hw.init = &init; 753 data->clk[i].index = i; 754 data->clk[i].pdiv = 1; 755 switch (i) { 756 case 1: 757 case 2: 758 /* Mux Y2/3 to PLL1 */ 759 init.parent_names = &pll_clk_name[0]; 760 break; 761 case 3: 762 case 4: 763 /* Mux Y4/5 to PLL2 */ 764 init.parent_names = &pll_clk_name[1]; 765 break; 766 case 5: 767 case 6: 768 /* Mux Y6/7 to PLL3 */ 769 init.parent_names = &pll_clk_name[2]; 770 break; 771 case 7: 772 case 8: 773 /* Mux Y8/9 to PLL4 */ 774 init.parent_names = &pll_clk_name[3]; 775 break; 776 } 777 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); 778 kfree(init.name); /* clock framework made a copy of the name */ 779 if (err) { 780 dev_err(&client->dev, "clock registration failed\n"); 781 goto error; 782 } 783 } 784 785 /* Register the output clocks */ 786 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get, 787 data); 788 if (err) 789 dev_err(&client->dev, "unable to add OF clock provider\n"); 790 791 err = 0; 792 793 error: 794 for (i = 0; i < data->chip_info->num_plls; ++i) 795 /* clock framework made a copy of the name */ 796 kfree(pll_clk_name[i]); 797 798 return err; 799 } 800 801 static const struct clk_cdce925_chip_info clk_cdce913_info = { 802 .num_plls = 1, 803 .num_outputs = 3, 804 }; 805 806 static const struct clk_cdce925_chip_info clk_cdce925_info = { 807 .num_plls = 2, 808 .num_outputs = 5, 809 }; 810 811 static const struct clk_cdce925_chip_info clk_cdce937_info = { 812 .num_plls = 3, 813 .num_outputs = 7, 814 }; 815 816 static const struct clk_cdce925_chip_info clk_cdce949_info = { 817 .num_plls = 4, 818 .num_outputs = 9, 819 }; 820 821 static const struct i2c_device_id cdce925_id[] = { 822 { "cdce913", (kernel_ulong_t)&clk_cdce913_info }, 823 { "cdce925", (kernel_ulong_t)&clk_cdce925_info }, 824 { "cdce937", (kernel_ulong_t)&clk_cdce937_info }, 825 { "cdce949", (kernel_ulong_t)&clk_cdce949_info }, 826 { } 827 }; 828 MODULE_DEVICE_TABLE(i2c, cdce925_id); 829 830 static const struct of_device_id clk_cdce925_of_match[] = { 831 { .compatible = "ti,cdce913", .data = &clk_cdce913_info }, 832 { .compatible = "ti,cdce925", .data = &clk_cdce925_info }, 833 { .compatible = "ti,cdce937", .data = &clk_cdce937_info }, 834 { .compatible = "ti,cdce949", .data = &clk_cdce949_info }, 835 { } 836 }; 837 MODULE_DEVICE_TABLE(of, clk_cdce925_of_match); 838 839 static struct i2c_driver cdce925_driver = { 840 .driver = { 841 .name = "cdce925", 842 .of_match_table = clk_cdce925_of_match, 843 }, 844 .probe = cdce925_probe, 845 .id_table = cdce925_id, 846 }; 847 module_i2c_driver(cdce925_driver); 848 849 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); 850 MODULE_DESCRIPTION("TI CDCE913/925/937/949 driver"); 851 MODULE_LICENSE("GPL"); 852