1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * TI CDCE706 programmable 3-PLL clock synthesizer driver 4 * 5 * Copyright (c) 2014 Cadence Design Systems Inc. 6 * 7 * Reference: https://www.ti.com/lit/ds/symlink/cdce706.pdf 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/i2c.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/rational.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 21 #define CDCE706_CLKIN_CLOCK 10 22 #define CDCE706_CLKIN_SOURCE 11 23 #define CDCE706_PLL_M_LOW(pll) (1 + 3 * (pll)) 24 #define CDCE706_PLL_N_LOW(pll) (2 + 3 * (pll)) 25 #define CDCE706_PLL_HI(pll) (3 + 3 * (pll)) 26 #define CDCE706_PLL_MUX 3 27 #define CDCE706_PLL_FVCO 6 28 #define CDCE706_DIVIDER(div) (13 + (div)) 29 #define CDCE706_CLKOUT(out) (19 + (out)) 30 31 #define CDCE706_CLKIN_CLOCK_MASK 0x10 32 #define CDCE706_CLKIN_SOURCE_SHIFT 6 33 #define CDCE706_CLKIN_SOURCE_MASK 0xc0 34 #define CDCE706_CLKIN_SOURCE_LVCMOS 0x40 35 36 #define CDCE706_PLL_MUX_MASK(pll) (0x80 >> (pll)) 37 #define CDCE706_PLL_LOW_M_MASK 0xff 38 #define CDCE706_PLL_LOW_N_MASK 0xff 39 #define CDCE706_PLL_HI_M_MASK 0x1 40 #define CDCE706_PLL_HI_N_MASK 0x1e 41 #define CDCE706_PLL_HI_N_SHIFT 1 42 #define CDCE706_PLL_M_MAX 0x1ff 43 #define CDCE706_PLL_N_MAX 0xfff 44 #define CDCE706_PLL_FVCO_MASK(pll) (0x80 >> (pll)) 45 #define CDCE706_PLL_FREQ_MIN 80000000 46 #define CDCE706_PLL_FREQ_MAX 300000000 47 #define CDCE706_PLL_FREQ_HI 180000000 48 49 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) 50 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) 51 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div)) 52 #define CDCE706_DIVIDER_DIVIDER_MASK 0x7f 53 #define CDCE706_DIVIDER_DIVIDER_MAX 0x7f 54 55 #define CDCE706_CLKOUT_DIVIDER_MASK 0x7 56 #define CDCE706_CLKOUT_ENABLE_MASK 0x8 57 58 static const struct regmap_config cdce706_regmap_config = { 59 .reg_bits = 8, 60 .val_bits = 8, 61 .val_format_endian = REGMAP_ENDIAN_NATIVE, 62 }; 63 64 #define to_hw_data(phw) (container_of((phw), struct cdce706_hw_data, hw)) 65 66 struct cdce706_hw_data { 67 struct cdce706_dev_data *dev_data; 68 unsigned idx; 69 unsigned parent; 70 struct clk_hw hw; 71 unsigned div; 72 unsigned mul; 73 unsigned mux; 74 }; 75 76 struct cdce706_dev_data { 77 struct i2c_client *client; 78 struct regmap *regmap; 79 struct clk *clkin_clk[2]; 80 const char *clkin_name[2]; 81 struct cdce706_hw_data clkin[1]; 82 struct cdce706_hw_data pll[3]; 83 struct cdce706_hw_data divider[6]; 84 struct cdce706_hw_data clkout[6]; 85 }; 86 87 static const char * const cdce706_source_name[] = { 88 "clk_in0", "clk_in1", 89 }; 90 91 static const char * const cdce706_clkin_name[] = { 92 "clk_in", 93 }; 94 95 static const char * const cdce706_pll_name[] = { 96 "pll1", "pll2", "pll3", 97 }; 98 99 static const char * const cdce706_divider_parent_name[] = { 100 "clk_in", "pll1", "pll2", "pll2", "pll3", 101 }; 102 103 static const char *cdce706_divider_name[] = { 104 "p0", "p1", "p2", "p3", "p4", "p5", 105 }; 106 107 static const char * const cdce706_clkout_name[] = { 108 "clk_out0", "clk_out1", "clk_out2", "clk_out3", "clk_out4", "clk_out5", 109 }; 110 111 static int cdce706_reg_read(struct cdce706_dev_data *dev_data, unsigned reg, 112 unsigned *val) 113 { 114 int rc = regmap_read(dev_data->regmap, reg | 0x80, val); 115 116 if (rc < 0) 117 dev_err(&dev_data->client->dev, "error reading reg %u", reg); 118 return rc; 119 } 120 121 static int cdce706_reg_write(struct cdce706_dev_data *dev_data, unsigned reg, 122 unsigned val) 123 { 124 int rc = regmap_write(dev_data->regmap, reg | 0x80, val); 125 126 if (rc < 0) 127 dev_err(&dev_data->client->dev, "error writing reg %u", reg); 128 return rc; 129 } 130 131 static int cdce706_reg_update(struct cdce706_dev_data *dev_data, unsigned reg, 132 unsigned mask, unsigned val) 133 { 134 int rc = regmap_update_bits(dev_data->regmap, reg | 0x80, mask, val); 135 136 if (rc < 0) 137 dev_err(&dev_data->client->dev, "error updating reg %u", reg); 138 return rc; 139 } 140 141 static int cdce706_clkin_set_parent(struct clk_hw *hw, u8 index) 142 { 143 struct cdce706_hw_data *hwd = to_hw_data(hw); 144 145 hwd->parent = index; 146 return 0; 147 } 148 149 static u8 cdce706_clkin_get_parent(struct clk_hw *hw) 150 { 151 struct cdce706_hw_data *hwd = to_hw_data(hw); 152 153 return hwd->parent; 154 } 155 156 static const struct clk_ops cdce706_clkin_ops = { 157 .determine_rate = clk_hw_determine_rate_no_reparent, 158 .set_parent = cdce706_clkin_set_parent, 159 .get_parent = cdce706_clkin_get_parent, 160 }; 161 162 static unsigned long cdce706_pll_recalc_rate(struct clk_hw *hw, 163 unsigned long parent_rate) 164 { 165 struct cdce706_hw_data *hwd = to_hw_data(hw); 166 167 dev_dbg(&hwd->dev_data->client->dev, 168 "%s, pll: %d, mux: %d, mul: %u, div: %u\n", 169 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); 170 171 if (!hwd->mux) { 172 if (hwd->div && hwd->mul) { 173 u64 res = (u64)parent_rate * hwd->mul; 174 175 do_div(res, hwd->div); 176 return res; 177 } 178 } else { 179 if (hwd->div) 180 return parent_rate / hwd->div; 181 } 182 return 0; 183 } 184 185 static int cdce706_pll_determine_rate(struct clk_hw *hw, 186 struct clk_rate_request *req) 187 { 188 struct cdce706_hw_data *hwd = to_hw_data(hw); 189 unsigned long mul, div; 190 u64 res; 191 192 dev_dbg(&hwd->dev_data->client->dev, 193 "%s, rate: %lu, parent_rate: %lu\n", 194 __func__, req->rate, req->best_parent_rate); 195 196 rational_best_approximation(req->rate, req->best_parent_rate, 197 CDCE706_PLL_N_MAX, CDCE706_PLL_M_MAX, 198 &mul, &div); 199 hwd->mul = mul; 200 hwd->div = div; 201 202 dev_dbg(&hwd->dev_data->client->dev, 203 "%s, pll: %d, mul: %lu, div: %lu\n", 204 __func__, hwd->idx, mul, div); 205 206 res = (u64)req->best_parent_rate * hwd->mul; 207 do_div(res, hwd->div); 208 req->rate = res; 209 210 return 0; 211 } 212 213 static int cdce706_pll_set_rate(struct clk_hw *hw, unsigned long rate, 214 unsigned long parent_rate) 215 { 216 struct cdce706_hw_data *hwd = to_hw_data(hw); 217 unsigned long mul = hwd->mul, div = hwd->div; 218 int err; 219 220 dev_dbg(&hwd->dev_data->client->dev, 221 "%s, pll: %d, mul: %lu, div: %lu\n", 222 __func__, hwd->idx, mul, div); 223 224 err = cdce706_reg_update(hwd->dev_data, 225 CDCE706_PLL_HI(hwd->idx), 226 CDCE706_PLL_HI_M_MASK | CDCE706_PLL_HI_N_MASK, 227 ((div >> 8) & CDCE706_PLL_HI_M_MASK) | 228 ((mul >> (8 - CDCE706_PLL_HI_N_SHIFT)) & 229 CDCE706_PLL_HI_N_MASK)); 230 if (err < 0) 231 return err; 232 233 err = cdce706_reg_write(hwd->dev_data, 234 CDCE706_PLL_M_LOW(hwd->idx), 235 div & CDCE706_PLL_LOW_M_MASK); 236 if (err < 0) 237 return err; 238 239 err = cdce706_reg_write(hwd->dev_data, 240 CDCE706_PLL_N_LOW(hwd->idx), 241 mul & CDCE706_PLL_LOW_N_MASK); 242 if (err < 0) 243 return err; 244 245 err = cdce706_reg_update(hwd->dev_data, 246 CDCE706_PLL_FVCO, 247 CDCE706_PLL_FVCO_MASK(hwd->idx), 248 rate > CDCE706_PLL_FREQ_HI ? 249 CDCE706_PLL_FVCO_MASK(hwd->idx) : 0); 250 return err; 251 } 252 253 static const struct clk_ops cdce706_pll_ops = { 254 .recalc_rate = cdce706_pll_recalc_rate, 255 .determine_rate = cdce706_pll_determine_rate, 256 .set_rate = cdce706_pll_set_rate, 257 }; 258 259 static int cdce706_divider_set_parent(struct clk_hw *hw, u8 index) 260 { 261 struct cdce706_hw_data *hwd = to_hw_data(hw); 262 263 if (hwd->parent == index) 264 return 0; 265 hwd->parent = index; 266 return cdce706_reg_update(hwd->dev_data, 267 CDCE706_DIVIDER_PLL(hwd->idx), 268 CDCE706_DIVIDER_PLL_MASK(hwd->idx), 269 index << CDCE706_DIVIDER_PLL_SHIFT(hwd->idx)); 270 } 271 272 static u8 cdce706_divider_get_parent(struct clk_hw *hw) 273 { 274 struct cdce706_hw_data *hwd = to_hw_data(hw); 275 276 return hwd->parent; 277 } 278 279 static unsigned long cdce706_divider_recalc_rate(struct clk_hw *hw, 280 unsigned long parent_rate) 281 { 282 struct cdce706_hw_data *hwd = to_hw_data(hw); 283 284 dev_dbg(&hwd->dev_data->client->dev, 285 "%s, divider: %d, div: %u\n", 286 __func__, hwd->idx, hwd->div); 287 if (hwd->div) 288 return parent_rate / hwd->div; 289 return 0; 290 } 291 292 static int cdce706_divider_determine_rate(struct clk_hw *hw, 293 struct clk_rate_request *req) 294 { 295 struct cdce706_hw_data *hwd = to_hw_data(hw); 296 struct cdce706_dev_data *cdce = hwd->dev_data; 297 unsigned long rate = req->rate; 298 unsigned long mul, div; 299 300 dev_dbg(&hwd->dev_data->client->dev, 301 "%s, rate: %lu, parent_rate: %lu\n", 302 __func__, rate, req->best_parent_rate); 303 304 rational_best_approximation(rate, req->best_parent_rate, 305 1, CDCE706_DIVIDER_DIVIDER_MAX, 306 &mul, &div); 307 if (!mul) 308 div = CDCE706_DIVIDER_DIVIDER_MAX; 309 310 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { 311 unsigned long best_diff = rate; 312 unsigned long best_div = 0; 313 struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0].parent]; 314 unsigned long gp_rate = gp_clk ? clk_get_rate(gp_clk) : 0; 315 316 for (div = CDCE706_PLL_FREQ_MIN / rate; best_diff && 317 div <= CDCE706_PLL_FREQ_MAX / rate; ++div) { 318 unsigned long n, m; 319 unsigned long diff; 320 unsigned long div_rate; 321 u64 div_rate64; 322 323 if (rate * div < CDCE706_PLL_FREQ_MIN) 324 continue; 325 326 rational_best_approximation(rate * div, gp_rate, 327 CDCE706_PLL_N_MAX, 328 CDCE706_PLL_M_MAX, 329 &n, &m); 330 div_rate64 = (u64)gp_rate * n; 331 do_div(div_rate64, m); 332 do_div(div_rate64, div); 333 div_rate = div_rate64; 334 diff = max(div_rate, rate) - min(div_rate, rate); 335 336 if (diff < best_diff) { 337 best_diff = diff; 338 best_div = div; 339 dev_dbg(&hwd->dev_data->client->dev, 340 "%s, %lu * %lu / %lu / %lu = %lu\n", 341 __func__, gp_rate, n, m, div, div_rate); 342 } 343 } 344 345 div = best_div; 346 347 dev_dbg(&hwd->dev_data->client->dev, 348 "%s, altering parent rate: %lu -> %lu\n", 349 __func__, req->best_parent_rate, rate * div); 350 req->best_parent_rate = rate * div; 351 } 352 hwd->div = div; 353 354 dev_dbg(&hwd->dev_data->client->dev, 355 "%s, divider: %d, div: %lu\n", 356 __func__, hwd->idx, div); 357 358 req->rate = req->best_parent_rate / div; 359 return 0; 360 } 361 362 static int cdce706_divider_set_rate(struct clk_hw *hw, unsigned long rate, 363 unsigned long parent_rate) 364 { 365 struct cdce706_hw_data *hwd = to_hw_data(hw); 366 367 dev_dbg(&hwd->dev_data->client->dev, 368 "%s, divider: %d, div: %u\n", 369 __func__, hwd->idx, hwd->div); 370 371 return cdce706_reg_update(hwd->dev_data, 372 CDCE706_DIVIDER(hwd->idx), 373 CDCE706_DIVIDER_DIVIDER_MASK, 374 hwd->div); 375 } 376 377 static const struct clk_ops cdce706_divider_ops = { 378 .set_parent = cdce706_divider_set_parent, 379 .get_parent = cdce706_divider_get_parent, 380 .recalc_rate = cdce706_divider_recalc_rate, 381 .determine_rate = cdce706_divider_determine_rate, 382 .set_rate = cdce706_divider_set_rate, 383 }; 384 385 static int cdce706_clkout_prepare(struct clk_hw *hw) 386 { 387 struct cdce706_hw_data *hwd = to_hw_data(hw); 388 389 return cdce706_reg_update(hwd->dev_data, CDCE706_CLKOUT(hwd->idx), 390 CDCE706_CLKOUT_ENABLE_MASK, 391 CDCE706_CLKOUT_ENABLE_MASK); 392 } 393 394 static void cdce706_clkout_unprepare(struct clk_hw *hw) 395 { 396 struct cdce706_hw_data *hwd = to_hw_data(hw); 397 398 cdce706_reg_update(hwd->dev_data, CDCE706_CLKOUT(hwd->idx), 399 CDCE706_CLKOUT_ENABLE_MASK, 0); 400 } 401 402 static int cdce706_clkout_set_parent(struct clk_hw *hw, u8 index) 403 { 404 struct cdce706_hw_data *hwd = to_hw_data(hw); 405 406 if (hwd->parent == index) 407 return 0; 408 hwd->parent = index; 409 return cdce706_reg_update(hwd->dev_data, 410 CDCE706_CLKOUT(hwd->idx), 411 CDCE706_CLKOUT_ENABLE_MASK, index); 412 } 413 414 static u8 cdce706_clkout_get_parent(struct clk_hw *hw) 415 { 416 struct cdce706_hw_data *hwd = to_hw_data(hw); 417 418 return hwd->parent; 419 } 420 421 static unsigned long cdce706_clkout_recalc_rate(struct clk_hw *hw, 422 unsigned long parent_rate) 423 { 424 return parent_rate; 425 } 426 427 static int cdce706_clkout_determine_rate(struct clk_hw *hw, 428 struct clk_rate_request *req) 429 { 430 req->best_parent_rate = req->rate; 431 432 return 0; 433 } 434 435 static int cdce706_clkout_set_rate(struct clk_hw *hw, unsigned long rate, 436 unsigned long parent_rate) 437 { 438 return 0; 439 } 440 441 static const struct clk_ops cdce706_clkout_ops = { 442 .prepare = cdce706_clkout_prepare, 443 .unprepare = cdce706_clkout_unprepare, 444 .set_parent = cdce706_clkout_set_parent, 445 .get_parent = cdce706_clkout_get_parent, 446 .recalc_rate = cdce706_clkout_recalc_rate, 447 .determine_rate = cdce706_clkout_determine_rate, 448 .set_rate = cdce706_clkout_set_rate, 449 }; 450 451 static int cdce706_register_hw(struct cdce706_dev_data *cdce, 452 struct cdce706_hw_data *hw, unsigned num_hw, 453 const char * const *clk_names, 454 struct clk_init_data *init) 455 { 456 unsigned i; 457 int ret; 458 459 for (i = 0; i < num_hw; ++i, ++hw) { 460 init->name = clk_names[i]; 461 hw->dev_data = cdce; 462 hw->idx = i; 463 hw->hw.init = init; 464 ret = devm_clk_hw_register(&cdce->client->dev, 465 &hw->hw); 466 if (ret) { 467 dev_err(&cdce->client->dev, "Failed to register %s\n", 468 clk_names[i]); 469 return ret; 470 } 471 } 472 return 0; 473 } 474 475 static int cdce706_register_clkin(struct cdce706_dev_data *cdce) 476 { 477 struct clk_init_data init = { 478 .ops = &cdce706_clkin_ops, 479 .parent_names = cdce->clkin_name, 480 .num_parents = ARRAY_SIZE(cdce->clkin_name), 481 }; 482 unsigned i; 483 int ret; 484 unsigned clock, source; 485 486 for (i = 0; i < ARRAY_SIZE(cdce->clkin_name); ++i) { 487 struct clk *parent = devm_clk_get(&cdce->client->dev, 488 cdce706_source_name[i]); 489 490 if (IS_ERR(parent)) { 491 cdce->clkin_name[i] = cdce706_source_name[i]; 492 } else { 493 cdce->clkin_name[i] = __clk_get_name(parent); 494 cdce->clkin_clk[i] = parent; 495 } 496 } 497 498 ret = cdce706_reg_read(cdce, CDCE706_CLKIN_SOURCE, &source); 499 if (ret < 0) 500 return ret; 501 if ((source & CDCE706_CLKIN_SOURCE_MASK) == 502 CDCE706_CLKIN_SOURCE_LVCMOS) { 503 ret = cdce706_reg_read(cdce, CDCE706_CLKIN_CLOCK, &clock); 504 if (ret < 0) 505 return ret; 506 cdce->clkin[0].parent = !!(clock & CDCE706_CLKIN_CLOCK_MASK); 507 } 508 509 ret = cdce706_register_hw(cdce, cdce->clkin, 510 ARRAY_SIZE(cdce->clkin), 511 cdce706_clkin_name, &init); 512 return ret; 513 } 514 515 static int cdce706_register_plls(struct cdce706_dev_data *cdce) 516 { 517 struct clk_init_data init = { 518 .ops = &cdce706_pll_ops, 519 .parent_names = cdce706_clkin_name, 520 .num_parents = ARRAY_SIZE(cdce706_clkin_name), 521 }; 522 unsigned i; 523 int ret; 524 unsigned mux; 525 526 ret = cdce706_reg_read(cdce, CDCE706_PLL_MUX, &mux); 527 if (ret < 0) 528 return ret; 529 530 for (i = 0; i < ARRAY_SIZE(cdce->pll); ++i) { 531 unsigned m, n, v; 532 533 ret = cdce706_reg_read(cdce, CDCE706_PLL_M_LOW(i), &m); 534 if (ret < 0) 535 return ret; 536 ret = cdce706_reg_read(cdce, CDCE706_PLL_N_LOW(i), &n); 537 if (ret < 0) 538 return ret; 539 ret = cdce706_reg_read(cdce, CDCE706_PLL_HI(i), &v); 540 if (ret < 0) 541 return ret; 542 cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8); 543 cdce->pll[i].mul = n | ((v & CDCE706_PLL_HI_N_MASK) << 544 (8 - CDCE706_PLL_HI_N_SHIFT)); 545 cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i); 546 dev_dbg(&cdce->client->dev, 547 "%s: i: %u, div: %u, mul: %u, mux: %d\n", __func__, i, 548 cdce->pll[i].div, cdce->pll[i].mul, cdce->pll[i].mux); 549 } 550 551 ret = cdce706_register_hw(cdce, cdce->pll, 552 ARRAY_SIZE(cdce->pll), 553 cdce706_pll_name, &init); 554 return ret; 555 } 556 557 static int cdce706_register_dividers(struct cdce706_dev_data *cdce) 558 { 559 struct clk_init_data init = { 560 .ops = &cdce706_divider_ops, 561 .parent_names = cdce706_divider_parent_name, 562 .num_parents = ARRAY_SIZE(cdce706_divider_parent_name), 563 .flags = CLK_SET_RATE_PARENT, 564 }; 565 unsigned i; 566 int ret; 567 568 for (i = 0; i < ARRAY_SIZE(cdce->divider); ++i) { 569 unsigned val; 570 571 ret = cdce706_reg_read(cdce, CDCE706_DIVIDER_PLL(i), &val); 572 if (ret < 0) 573 return ret; 574 cdce->divider[i].parent = 575 (val & CDCE706_DIVIDER_PLL_MASK(i)) >> 576 CDCE706_DIVIDER_PLL_SHIFT(i); 577 578 ret = cdce706_reg_read(cdce, CDCE706_DIVIDER(i), &val); 579 if (ret < 0) 580 return ret; 581 cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK; 582 dev_dbg(&cdce->client->dev, 583 "%s: i: %u, parent: %u, div: %u\n", __func__, i, 584 cdce->divider[i].parent, cdce->divider[i].div); 585 } 586 587 ret = cdce706_register_hw(cdce, cdce->divider, 588 ARRAY_SIZE(cdce->divider), 589 cdce706_divider_name, &init); 590 return ret; 591 } 592 593 static int cdce706_register_clkouts(struct cdce706_dev_data *cdce) 594 { 595 struct clk_init_data init = { 596 .ops = &cdce706_clkout_ops, 597 .parent_names = cdce706_divider_name, 598 .num_parents = ARRAY_SIZE(cdce706_divider_name), 599 .flags = CLK_SET_RATE_PARENT, 600 }; 601 unsigned i; 602 int ret; 603 604 for (i = 0; i < ARRAY_SIZE(cdce->clkout); ++i) { 605 unsigned val; 606 607 ret = cdce706_reg_read(cdce, CDCE706_CLKOUT(i), &val); 608 if (ret < 0) 609 return ret; 610 cdce->clkout[i].parent = val & CDCE706_CLKOUT_DIVIDER_MASK; 611 dev_dbg(&cdce->client->dev, 612 "%s: i: %u, parent: %u\n", __func__, i, 613 cdce->clkout[i].parent); 614 } 615 616 return cdce706_register_hw(cdce, cdce->clkout, 617 ARRAY_SIZE(cdce->clkout), 618 cdce706_clkout_name, &init); 619 } 620 621 static struct clk_hw * 622 of_clk_cdce_get(struct of_phandle_args *clkspec, void *data) 623 { 624 struct cdce706_dev_data *cdce = data; 625 unsigned int idx = clkspec->args[0]; 626 627 if (idx >= ARRAY_SIZE(cdce->clkout)) { 628 pr_err("%s: invalid index %u\n", __func__, idx); 629 return ERR_PTR(-EINVAL); 630 } 631 632 return &cdce->clkout[idx].hw; 633 } 634 635 static int cdce706_probe(struct i2c_client *client) 636 { 637 struct i2c_adapter *adapter = client->adapter; 638 struct cdce706_dev_data *cdce; 639 int ret; 640 641 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 642 return -EIO; 643 644 cdce = devm_kzalloc(&client->dev, sizeof(*cdce), GFP_KERNEL); 645 if (!cdce) 646 return -ENOMEM; 647 648 cdce->client = client; 649 cdce->regmap = devm_regmap_init_i2c(client, &cdce706_regmap_config); 650 if (IS_ERR(cdce->regmap)) { 651 dev_err(&client->dev, "Failed to initialize regmap\n"); 652 return -EINVAL; 653 } 654 655 i2c_set_clientdata(client, cdce); 656 657 ret = cdce706_register_clkin(cdce); 658 if (ret < 0) 659 return ret; 660 ret = cdce706_register_plls(cdce); 661 if (ret < 0) 662 return ret; 663 ret = cdce706_register_dividers(cdce); 664 if (ret < 0) 665 return ret; 666 ret = cdce706_register_clkouts(cdce); 667 if (ret < 0) 668 return ret; 669 return devm_of_clk_add_hw_provider(&client->dev, of_clk_cdce_get, 670 cdce); 671 } 672 673 #ifdef CONFIG_OF 674 static const struct of_device_id cdce706_dt_match[] = { 675 { .compatible = "ti,cdce706" }, 676 { }, 677 }; 678 MODULE_DEVICE_TABLE(of, cdce706_dt_match); 679 #endif 680 681 static const struct i2c_device_id cdce706_id[] = { 682 { "cdce706" }, 683 { } 684 }; 685 MODULE_DEVICE_TABLE(i2c, cdce706_id); 686 687 static struct i2c_driver cdce706_i2c_driver = { 688 .driver = { 689 .name = "cdce706", 690 .of_match_table = of_match_ptr(cdce706_dt_match), 691 }, 692 .probe = cdce706_probe, 693 .id_table = cdce706_id, 694 }; 695 module_i2c_driver(cdce706_i2c_driver); 696 697 MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>"); 698 MODULE_DESCRIPTION("TI CDCE 706 clock synthesizer driver"); 699 MODULE_LICENSE("GPL"); 700