1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * TI CDCE706 programmable 3-PLL clock synthesizer driver 4 * 5 * Copyright (c) 2014 Cadence Design Systems Inc. 6 * 7 * Reference: https://www.ti.com/lit/ds/symlink/cdce706.pdf 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/i2c.h> 14 #include <linux/interrupt.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/rational.h> 19 #include <linux/regmap.h> 20 #include <linux/slab.h> 21 22 #define CDCE706_CLKIN_CLOCK 10 23 #define CDCE706_CLKIN_SOURCE 11 24 #define CDCE706_PLL_M_LOW(pll) (1 + 3 * (pll)) 25 #define CDCE706_PLL_N_LOW(pll) (2 + 3 * (pll)) 26 #define CDCE706_PLL_HI(pll) (3 + 3 * (pll)) 27 #define CDCE706_PLL_MUX 3 28 #define CDCE706_PLL_FVCO 6 29 #define CDCE706_DIVIDER(div) (13 + (div)) 30 #define CDCE706_CLKOUT(out) (19 + (out)) 31 32 #define CDCE706_CLKIN_CLOCK_MASK 0x10 33 #define CDCE706_CLKIN_SOURCE_SHIFT 6 34 #define CDCE706_CLKIN_SOURCE_MASK 0xc0 35 #define CDCE706_CLKIN_SOURCE_LVCMOS 0x40 36 37 #define CDCE706_PLL_MUX_MASK(pll) (0x80 >> (pll)) 38 #define CDCE706_PLL_LOW_M_MASK 0xff 39 #define CDCE706_PLL_LOW_N_MASK 0xff 40 #define CDCE706_PLL_HI_M_MASK 0x1 41 #define CDCE706_PLL_HI_N_MASK 0x1e 42 #define CDCE706_PLL_HI_N_SHIFT 1 43 #define CDCE706_PLL_M_MAX 0x1ff 44 #define CDCE706_PLL_N_MAX 0xfff 45 #define CDCE706_PLL_FVCO_MASK(pll) (0x80 >> (pll)) 46 #define CDCE706_PLL_FREQ_MIN 80000000 47 #define CDCE706_PLL_FREQ_MAX 300000000 48 #define CDCE706_PLL_FREQ_HI 180000000 49 50 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) 51 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) 52 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div)) 53 #define CDCE706_DIVIDER_DIVIDER_MASK 0x7f 54 #define CDCE706_DIVIDER_DIVIDER_MAX 0x7f 55 56 #define CDCE706_CLKOUT_DIVIDER_MASK 0x7 57 #define CDCE706_CLKOUT_ENABLE_MASK 0x8 58 59 static const struct regmap_config cdce706_regmap_config = { 60 .reg_bits = 8, 61 .val_bits = 8, 62 .val_format_endian = REGMAP_ENDIAN_NATIVE, 63 }; 64 65 #define to_hw_data(phw) (container_of((phw), struct cdce706_hw_data, hw)) 66 67 struct cdce706_hw_data { 68 struct cdce706_dev_data *dev_data; 69 unsigned idx; 70 unsigned parent; 71 struct clk_hw hw; 72 unsigned div; 73 unsigned mul; 74 unsigned mux; 75 }; 76 77 struct cdce706_dev_data { 78 struct i2c_client *client; 79 struct regmap *regmap; 80 struct clk *clkin_clk[2]; 81 const char *clkin_name[2]; 82 struct cdce706_hw_data clkin[1]; 83 struct cdce706_hw_data pll[3]; 84 struct cdce706_hw_data divider[6]; 85 struct cdce706_hw_data clkout[6]; 86 }; 87 88 static const char * const cdce706_source_name[] = { 89 "clk_in0", "clk_in1", 90 }; 91 92 static const char * const cdce706_clkin_name[] = { 93 "clk_in", 94 }; 95 96 static const char * const cdce706_pll_name[] = { 97 "pll1", "pll2", "pll3", 98 }; 99 100 static const char * const cdce706_divider_parent_name[] = { 101 "clk_in", "pll1", "pll2", "pll2", "pll3", 102 }; 103 104 static const char *cdce706_divider_name[] = { 105 "p0", "p1", "p2", "p3", "p4", "p5", 106 }; 107 108 static const char * const cdce706_clkout_name[] = { 109 "clk_out0", "clk_out1", "clk_out2", "clk_out3", "clk_out4", "clk_out5", 110 }; 111 112 static int cdce706_reg_read(struct cdce706_dev_data *dev_data, unsigned reg, 113 unsigned *val) 114 { 115 int rc = regmap_read(dev_data->regmap, reg | 0x80, val); 116 117 if (rc < 0) 118 dev_err(&dev_data->client->dev, "error reading reg %u", reg); 119 return rc; 120 } 121 122 static int cdce706_reg_write(struct cdce706_dev_data *dev_data, unsigned reg, 123 unsigned val) 124 { 125 int rc = regmap_write(dev_data->regmap, reg | 0x80, val); 126 127 if (rc < 0) 128 dev_err(&dev_data->client->dev, "error writing reg %u", reg); 129 return rc; 130 } 131 132 static int cdce706_reg_update(struct cdce706_dev_data *dev_data, unsigned reg, 133 unsigned mask, unsigned val) 134 { 135 int rc = regmap_update_bits(dev_data->regmap, reg | 0x80, mask, val); 136 137 if (rc < 0) 138 dev_err(&dev_data->client->dev, "error updating reg %u", reg); 139 return rc; 140 } 141 142 static int cdce706_clkin_set_parent(struct clk_hw *hw, u8 index) 143 { 144 struct cdce706_hw_data *hwd = to_hw_data(hw); 145 146 hwd->parent = index; 147 return 0; 148 } 149 150 static u8 cdce706_clkin_get_parent(struct clk_hw *hw) 151 { 152 struct cdce706_hw_data *hwd = to_hw_data(hw); 153 154 return hwd->parent; 155 } 156 157 static const struct clk_ops cdce706_clkin_ops = { 158 .determine_rate = clk_hw_determine_rate_no_reparent, 159 .set_parent = cdce706_clkin_set_parent, 160 .get_parent = cdce706_clkin_get_parent, 161 }; 162 163 static unsigned long cdce706_pll_recalc_rate(struct clk_hw *hw, 164 unsigned long parent_rate) 165 { 166 struct cdce706_hw_data *hwd = to_hw_data(hw); 167 168 dev_dbg(&hwd->dev_data->client->dev, 169 "%s, pll: %d, mux: %d, mul: %u, div: %u\n", 170 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); 171 172 if (!hwd->mux) { 173 if (hwd->div && hwd->mul) { 174 u64 res = (u64)parent_rate * hwd->mul; 175 176 do_div(res, hwd->div); 177 return res; 178 } 179 } else { 180 if (hwd->div) 181 return parent_rate / hwd->div; 182 } 183 return 0; 184 } 185 186 static int cdce706_pll_determine_rate(struct clk_hw *hw, 187 struct clk_rate_request *req) 188 { 189 struct cdce706_hw_data *hwd = to_hw_data(hw); 190 unsigned long mul, div; 191 u64 res; 192 193 dev_dbg(&hwd->dev_data->client->dev, 194 "%s, rate: %lu, parent_rate: %lu\n", 195 __func__, req->rate, req->best_parent_rate); 196 197 rational_best_approximation(req->rate, req->best_parent_rate, 198 CDCE706_PLL_N_MAX, CDCE706_PLL_M_MAX, 199 &mul, &div); 200 hwd->mul = mul; 201 hwd->div = div; 202 203 dev_dbg(&hwd->dev_data->client->dev, 204 "%s, pll: %d, mul: %lu, div: %lu\n", 205 __func__, hwd->idx, mul, div); 206 207 res = (u64)req->best_parent_rate * hwd->mul; 208 do_div(res, hwd->div); 209 req->rate = res; 210 211 return 0; 212 } 213 214 static int cdce706_pll_set_rate(struct clk_hw *hw, unsigned long rate, 215 unsigned long parent_rate) 216 { 217 struct cdce706_hw_data *hwd = to_hw_data(hw); 218 unsigned long mul = hwd->mul, div = hwd->div; 219 int err; 220 221 dev_dbg(&hwd->dev_data->client->dev, 222 "%s, pll: %d, mul: %lu, div: %lu\n", 223 __func__, hwd->idx, mul, div); 224 225 err = cdce706_reg_update(hwd->dev_data, 226 CDCE706_PLL_HI(hwd->idx), 227 CDCE706_PLL_HI_M_MASK | CDCE706_PLL_HI_N_MASK, 228 ((div >> 8) & CDCE706_PLL_HI_M_MASK) | 229 ((mul >> (8 - CDCE706_PLL_HI_N_SHIFT)) & 230 CDCE706_PLL_HI_N_MASK)); 231 if (err < 0) 232 return err; 233 234 err = cdce706_reg_write(hwd->dev_data, 235 CDCE706_PLL_M_LOW(hwd->idx), 236 div & CDCE706_PLL_LOW_M_MASK); 237 if (err < 0) 238 return err; 239 240 err = cdce706_reg_write(hwd->dev_data, 241 CDCE706_PLL_N_LOW(hwd->idx), 242 mul & CDCE706_PLL_LOW_N_MASK); 243 if (err < 0) 244 return err; 245 246 err = cdce706_reg_update(hwd->dev_data, 247 CDCE706_PLL_FVCO, 248 CDCE706_PLL_FVCO_MASK(hwd->idx), 249 rate > CDCE706_PLL_FREQ_HI ? 250 CDCE706_PLL_FVCO_MASK(hwd->idx) : 0); 251 return err; 252 } 253 254 static const struct clk_ops cdce706_pll_ops = { 255 .recalc_rate = cdce706_pll_recalc_rate, 256 .determine_rate = cdce706_pll_determine_rate, 257 .set_rate = cdce706_pll_set_rate, 258 }; 259 260 static int cdce706_divider_set_parent(struct clk_hw *hw, u8 index) 261 { 262 struct cdce706_hw_data *hwd = to_hw_data(hw); 263 264 if (hwd->parent == index) 265 return 0; 266 hwd->parent = index; 267 return cdce706_reg_update(hwd->dev_data, 268 CDCE706_DIVIDER_PLL(hwd->idx), 269 CDCE706_DIVIDER_PLL_MASK(hwd->idx), 270 index << CDCE706_DIVIDER_PLL_SHIFT(hwd->idx)); 271 } 272 273 static u8 cdce706_divider_get_parent(struct clk_hw *hw) 274 { 275 struct cdce706_hw_data *hwd = to_hw_data(hw); 276 277 return hwd->parent; 278 } 279 280 static unsigned long cdce706_divider_recalc_rate(struct clk_hw *hw, 281 unsigned long parent_rate) 282 { 283 struct cdce706_hw_data *hwd = to_hw_data(hw); 284 285 dev_dbg(&hwd->dev_data->client->dev, 286 "%s, divider: %d, div: %u\n", 287 __func__, hwd->idx, hwd->div); 288 if (hwd->div) 289 return parent_rate / hwd->div; 290 return 0; 291 } 292 293 static int cdce706_divider_determine_rate(struct clk_hw *hw, 294 struct clk_rate_request *req) 295 { 296 struct cdce706_hw_data *hwd = to_hw_data(hw); 297 struct cdce706_dev_data *cdce = hwd->dev_data; 298 unsigned long rate = req->rate; 299 unsigned long mul, div; 300 301 dev_dbg(&hwd->dev_data->client->dev, 302 "%s, rate: %lu, parent_rate: %lu\n", 303 __func__, rate, req->best_parent_rate); 304 305 rational_best_approximation(rate, req->best_parent_rate, 306 1, CDCE706_DIVIDER_DIVIDER_MAX, 307 &mul, &div); 308 if (!mul) 309 div = CDCE706_DIVIDER_DIVIDER_MAX; 310 311 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { 312 unsigned long best_diff = rate; 313 unsigned long best_div = 0; 314 struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0].parent]; 315 unsigned long gp_rate = gp_clk ? clk_get_rate(gp_clk) : 0; 316 317 for (div = CDCE706_PLL_FREQ_MIN / rate; best_diff && 318 div <= CDCE706_PLL_FREQ_MAX / rate; ++div) { 319 unsigned long n, m; 320 unsigned long diff; 321 unsigned long div_rate; 322 u64 div_rate64; 323 324 if (rate * div < CDCE706_PLL_FREQ_MIN) 325 continue; 326 327 rational_best_approximation(rate * div, gp_rate, 328 CDCE706_PLL_N_MAX, 329 CDCE706_PLL_M_MAX, 330 &n, &m); 331 div_rate64 = (u64)gp_rate * n; 332 do_div(div_rate64, m); 333 do_div(div_rate64, div); 334 div_rate = div_rate64; 335 diff = max(div_rate, rate) - min(div_rate, rate); 336 337 if (diff < best_diff) { 338 best_diff = diff; 339 best_div = div; 340 dev_dbg(&hwd->dev_data->client->dev, 341 "%s, %lu * %lu / %lu / %lu = %lu\n", 342 __func__, gp_rate, n, m, div, div_rate); 343 } 344 } 345 346 div = best_div; 347 348 dev_dbg(&hwd->dev_data->client->dev, 349 "%s, altering parent rate: %lu -> %lu\n", 350 __func__, req->best_parent_rate, rate * div); 351 req->best_parent_rate = rate * div; 352 } 353 hwd->div = div; 354 355 dev_dbg(&hwd->dev_data->client->dev, 356 "%s, divider: %d, div: %lu\n", 357 __func__, hwd->idx, div); 358 359 req->rate = req->best_parent_rate / div; 360 return 0; 361 } 362 363 static int cdce706_divider_set_rate(struct clk_hw *hw, unsigned long rate, 364 unsigned long parent_rate) 365 { 366 struct cdce706_hw_data *hwd = to_hw_data(hw); 367 368 dev_dbg(&hwd->dev_data->client->dev, 369 "%s, divider: %d, div: %u\n", 370 __func__, hwd->idx, hwd->div); 371 372 return cdce706_reg_update(hwd->dev_data, 373 CDCE706_DIVIDER(hwd->idx), 374 CDCE706_DIVIDER_DIVIDER_MASK, 375 hwd->div); 376 } 377 378 static const struct clk_ops cdce706_divider_ops = { 379 .set_parent = cdce706_divider_set_parent, 380 .get_parent = cdce706_divider_get_parent, 381 .recalc_rate = cdce706_divider_recalc_rate, 382 .determine_rate = cdce706_divider_determine_rate, 383 .set_rate = cdce706_divider_set_rate, 384 }; 385 386 static int cdce706_clkout_prepare(struct clk_hw *hw) 387 { 388 struct cdce706_hw_data *hwd = to_hw_data(hw); 389 390 return cdce706_reg_update(hwd->dev_data, CDCE706_CLKOUT(hwd->idx), 391 CDCE706_CLKOUT_ENABLE_MASK, 392 CDCE706_CLKOUT_ENABLE_MASK); 393 } 394 395 static void cdce706_clkout_unprepare(struct clk_hw *hw) 396 { 397 struct cdce706_hw_data *hwd = to_hw_data(hw); 398 399 cdce706_reg_update(hwd->dev_data, CDCE706_CLKOUT(hwd->idx), 400 CDCE706_CLKOUT_ENABLE_MASK, 0); 401 } 402 403 static int cdce706_clkout_set_parent(struct clk_hw *hw, u8 index) 404 { 405 struct cdce706_hw_data *hwd = to_hw_data(hw); 406 407 if (hwd->parent == index) 408 return 0; 409 hwd->parent = index; 410 return cdce706_reg_update(hwd->dev_data, 411 CDCE706_CLKOUT(hwd->idx), 412 CDCE706_CLKOUT_ENABLE_MASK, index); 413 } 414 415 static u8 cdce706_clkout_get_parent(struct clk_hw *hw) 416 { 417 struct cdce706_hw_data *hwd = to_hw_data(hw); 418 419 return hwd->parent; 420 } 421 422 static unsigned long cdce706_clkout_recalc_rate(struct clk_hw *hw, 423 unsigned long parent_rate) 424 { 425 return parent_rate; 426 } 427 428 static int cdce706_clkout_determine_rate(struct clk_hw *hw, 429 struct clk_rate_request *req) 430 { 431 req->best_parent_rate = req->rate; 432 433 return 0; 434 } 435 436 static int cdce706_clkout_set_rate(struct clk_hw *hw, unsigned long rate, 437 unsigned long parent_rate) 438 { 439 return 0; 440 } 441 442 static const struct clk_ops cdce706_clkout_ops = { 443 .prepare = cdce706_clkout_prepare, 444 .unprepare = cdce706_clkout_unprepare, 445 .set_parent = cdce706_clkout_set_parent, 446 .get_parent = cdce706_clkout_get_parent, 447 .recalc_rate = cdce706_clkout_recalc_rate, 448 .determine_rate = cdce706_clkout_determine_rate, 449 .set_rate = cdce706_clkout_set_rate, 450 }; 451 452 static int cdce706_register_hw(struct cdce706_dev_data *cdce, 453 struct cdce706_hw_data *hw, unsigned num_hw, 454 const char * const *clk_names, 455 struct clk_init_data *init) 456 { 457 unsigned i; 458 int ret; 459 460 for (i = 0; i < num_hw; ++i, ++hw) { 461 init->name = clk_names[i]; 462 hw->dev_data = cdce; 463 hw->idx = i; 464 hw->hw.init = init; 465 ret = devm_clk_hw_register(&cdce->client->dev, 466 &hw->hw); 467 if (ret) { 468 dev_err(&cdce->client->dev, "Failed to register %s\n", 469 clk_names[i]); 470 return ret; 471 } 472 } 473 return 0; 474 } 475 476 static int cdce706_register_clkin(struct cdce706_dev_data *cdce) 477 { 478 struct clk_init_data init = { 479 .ops = &cdce706_clkin_ops, 480 .parent_names = cdce->clkin_name, 481 .num_parents = ARRAY_SIZE(cdce->clkin_name), 482 }; 483 unsigned i; 484 int ret; 485 unsigned clock, source; 486 487 for (i = 0; i < ARRAY_SIZE(cdce->clkin_name); ++i) { 488 struct clk *parent = devm_clk_get(&cdce->client->dev, 489 cdce706_source_name[i]); 490 491 if (IS_ERR(parent)) { 492 cdce->clkin_name[i] = cdce706_source_name[i]; 493 } else { 494 cdce->clkin_name[i] = __clk_get_name(parent); 495 cdce->clkin_clk[i] = parent; 496 } 497 } 498 499 ret = cdce706_reg_read(cdce, CDCE706_CLKIN_SOURCE, &source); 500 if (ret < 0) 501 return ret; 502 if ((source & CDCE706_CLKIN_SOURCE_MASK) == 503 CDCE706_CLKIN_SOURCE_LVCMOS) { 504 ret = cdce706_reg_read(cdce, CDCE706_CLKIN_CLOCK, &clock); 505 if (ret < 0) 506 return ret; 507 cdce->clkin[0].parent = !!(clock & CDCE706_CLKIN_CLOCK_MASK); 508 } 509 510 ret = cdce706_register_hw(cdce, cdce->clkin, 511 ARRAY_SIZE(cdce->clkin), 512 cdce706_clkin_name, &init); 513 return ret; 514 } 515 516 static int cdce706_register_plls(struct cdce706_dev_data *cdce) 517 { 518 struct clk_init_data init = { 519 .ops = &cdce706_pll_ops, 520 .parent_names = cdce706_clkin_name, 521 .num_parents = ARRAY_SIZE(cdce706_clkin_name), 522 }; 523 unsigned i; 524 int ret; 525 unsigned mux; 526 527 ret = cdce706_reg_read(cdce, CDCE706_PLL_MUX, &mux); 528 if (ret < 0) 529 return ret; 530 531 for (i = 0; i < ARRAY_SIZE(cdce->pll); ++i) { 532 unsigned m, n, v; 533 534 ret = cdce706_reg_read(cdce, CDCE706_PLL_M_LOW(i), &m); 535 if (ret < 0) 536 return ret; 537 ret = cdce706_reg_read(cdce, CDCE706_PLL_N_LOW(i), &n); 538 if (ret < 0) 539 return ret; 540 ret = cdce706_reg_read(cdce, CDCE706_PLL_HI(i), &v); 541 if (ret < 0) 542 return ret; 543 cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8); 544 cdce->pll[i].mul = n | ((v & CDCE706_PLL_HI_N_MASK) << 545 (8 - CDCE706_PLL_HI_N_SHIFT)); 546 cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i); 547 dev_dbg(&cdce->client->dev, 548 "%s: i: %u, div: %u, mul: %u, mux: %d\n", __func__, i, 549 cdce->pll[i].div, cdce->pll[i].mul, cdce->pll[i].mux); 550 } 551 552 ret = cdce706_register_hw(cdce, cdce->pll, 553 ARRAY_SIZE(cdce->pll), 554 cdce706_pll_name, &init); 555 return ret; 556 } 557 558 static int cdce706_register_dividers(struct cdce706_dev_data *cdce) 559 { 560 struct clk_init_data init = { 561 .ops = &cdce706_divider_ops, 562 .parent_names = cdce706_divider_parent_name, 563 .num_parents = ARRAY_SIZE(cdce706_divider_parent_name), 564 .flags = CLK_SET_RATE_PARENT, 565 }; 566 unsigned i; 567 int ret; 568 569 for (i = 0; i < ARRAY_SIZE(cdce->divider); ++i) { 570 unsigned val; 571 572 ret = cdce706_reg_read(cdce, CDCE706_DIVIDER_PLL(i), &val); 573 if (ret < 0) 574 return ret; 575 cdce->divider[i].parent = 576 (val & CDCE706_DIVIDER_PLL_MASK(i)) >> 577 CDCE706_DIVIDER_PLL_SHIFT(i); 578 579 ret = cdce706_reg_read(cdce, CDCE706_DIVIDER(i), &val); 580 if (ret < 0) 581 return ret; 582 cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK; 583 dev_dbg(&cdce->client->dev, 584 "%s: i: %u, parent: %u, div: %u\n", __func__, i, 585 cdce->divider[i].parent, cdce->divider[i].div); 586 } 587 588 ret = cdce706_register_hw(cdce, cdce->divider, 589 ARRAY_SIZE(cdce->divider), 590 cdce706_divider_name, &init); 591 return ret; 592 } 593 594 static int cdce706_register_clkouts(struct cdce706_dev_data *cdce) 595 { 596 struct clk_init_data init = { 597 .ops = &cdce706_clkout_ops, 598 .parent_names = cdce706_divider_name, 599 .num_parents = ARRAY_SIZE(cdce706_divider_name), 600 .flags = CLK_SET_RATE_PARENT, 601 }; 602 unsigned i; 603 int ret; 604 605 for (i = 0; i < ARRAY_SIZE(cdce->clkout); ++i) { 606 unsigned val; 607 608 ret = cdce706_reg_read(cdce, CDCE706_CLKOUT(i), &val); 609 if (ret < 0) 610 return ret; 611 cdce->clkout[i].parent = val & CDCE706_CLKOUT_DIVIDER_MASK; 612 dev_dbg(&cdce->client->dev, 613 "%s: i: %u, parent: %u\n", __func__, i, 614 cdce->clkout[i].parent); 615 } 616 617 return cdce706_register_hw(cdce, cdce->clkout, 618 ARRAY_SIZE(cdce->clkout), 619 cdce706_clkout_name, &init); 620 } 621 622 static struct clk_hw * 623 of_clk_cdce_get(struct of_phandle_args *clkspec, void *data) 624 { 625 struct cdce706_dev_data *cdce = data; 626 unsigned int idx = clkspec->args[0]; 627 628 if (idx >= ARRAY_SIZE(cdce->clkout)) { 629 pr_err("%s: invalid index %u\n", __func__, idx); 630 return ERR_PTR(-EINVAL); 631 } 632 633 return &cdce->clkout[idx].hw; 634 } 635 636 static int cdce706_probe(struct i2c_client *client) 637 { 638 struct i2c_adapter *adapter = client->adapter; 639 struct cdce706_dev_data *cdce; 640 int ret; 641 642 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 643 return -EIO; 644 645 cdce = devm_kzalloc(&client->dev, sizeof(*cdce), GFP_KERNEL); 646 if (!cdce) 647 return -ENOMEM; 648 649 cdce->client = client; 650 cdce->regmap = devm_regmap_init_i2c(client, &cdce706_regmap_config); 651 if (IS_ERR(cdce->regmap)) { 652 dev_err(&client->dev, "Failed to initialize regmap\n"); 653 return -EINVAL; 654 } 655 656 i2c_set_clientdata(client, cdce); 657 658 ret = cdce706_register_clkin(cdce); 659 if (ret < 0) 660 return ret; 661 ret = cdce706_register_plls(cdce); 662 if (ret < 0) 663 return ret; 664 ret = cdce706_register_dividers(cdce); 665 if (ret < 0) 666 return ret; 667 ret = cdce706_register_clkouts(cdce); 668 if (ret < 0) 669 return ret; 670 return devm_of_clk_add_hw_provider(&client->dev, of_clk_cdce_get, 671 cdce); 672 } 673 674 #ifdef CONFIG_OF 675 static const struct of_device_id cdce706_dt_match[] = { 676 { .compatible = "ti,cdce706" }, 677 { }, 678 }; 679 MODULE_DEVICE_TABLE(of, cdce706_dt_match); 680 #endif 681 682 static const struct i2c_device_id cdce706_id[] = { 683 { "cdce706" }, 684 { } 685 }; 686 MODULE_DEVICE_TABLE(i2c, cdce706_id); 687 688 static struct i2c_driver cdce706_i2c_driver = { 689 .driver = { 690 .name = "cdce706", 691 .of_match_table = of_match_ptr(cdce706_dt_match), 692 }, 693 .probe = cdce706_probe, 694 .id_table = cdce706_id, 695 }; 696 module_i2c_driver(cdce706_i2c_driver); 697 698 MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>"); 699 MODULE_DESCRIPTION("TI CDCE 706 clock synthesizer driver"); 700 MODULE_LICENSE("GPL"); 701