1 // SPDX-License-Identifier: GPL-2.0-or-later 2 // Copyright IBM Corp 3 // Copyright ASPEED Technology 4 5 #define pr_fmt(fmt) "clk-ast2600: " fmt 6 7 #include <linux/mfd/syscon.h> 8 #include <linux/of_address.h> 9 #include <linux/of_device.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 #include <linux/slab.h> 13 14 #include <dt-bindings/clock/ast2600-clock.h> 15 16 #include "clk-aspeed.h" 17 18 #define ASPEED_G6_NUM_CLKS 67 19 20 #define ASPEED_G6_SILICON_REV 0x004 21 22 #define ASPEED_G6_RESET_CTRL 0x040 23 #define ASPEED_G6_RESET_CTRL2 0x050 24 25 #define ASPEED_G6_CLK_STOP_CTRL 0x080 26 #define ASPEED_G6_CLK_STOP_CTRL2 0x090 27 28 #define ASPEED_G6_MISC_CTRL 0x0C0 29 #define UART_DIV13_EN BIT(12) 30 31 #define ASPEED_G6_CLK_SELECTION1 0x300 32 #define ASPEED_G6_CLK_SELECTION2 0x304 33 #define ASPEED_G6_CLK_SELECTION4 0x310 34 35 #define ASPEED_HPLL_PARAM 0x200 36 #define ASPEED_APLL_PARAM 0x210 37 #define ASPEED_MPLL_PARAM 0x220 38 #define ASPEED_EPLL_PARAM 0x240 39 #define ASPEED_DPLL_PARAM 0x260 40 41 #define ASPEED_G6_STRAP1 0x500 42 43 /* Globally visible clocks */ 44 static DEFINE_SPINLOCK(aspeed_g6_clk_lock); 45 46 /* Keeps track of all clocks */ 47 static struct clk_hw_onecell_data *aspeed_g6_clk_data; 48 49 static void __iomem *scu_g6_base; 50 51 /* 52 * Clocks marked with CLK_IS_CRITICAL: 53 * 54 * ref0 and ref1 are essential for the SoC to operate 55 * mpll is required if SDRAM is used 56 */ 57 static const struct aspeed_gate_data aspeed_g6_gates[] = { 58 /* clk rst name parent flags */ 59 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ 60 [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */ 61 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ 62 /* vclk parent - dclk/d1clk/hclk/mclk */ 63 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */ 64 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */ 65 /* From dpll */ 66 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */ 67 [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL }, 68 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ 69 /* Reserved 8 */ 70 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */ 71 /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */ 72 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */ 73 /* Reserved 11/12 */ 74 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */ 75 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */ 76 [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */ 77 /* Reserved 16/19 */ 78 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */ 79 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */ 80 /* Reserved 22/23 */ 81 [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */ 82 [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */ 83 /* Reserved 26 */ 84 [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */ 85 /* Reserved 28/29/30 */ 86 [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */ 87 [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */ 88 [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL }, 89 /* Reserved 35 */ 90 [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */ 91 [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ 92 /* Reserved 38 RSA: no longer used */ 93 /* Reserved 39 */ 94 [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */ 95 [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */ 96 [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */ 97 [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */ 98 [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */ 99 [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */ 100 [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */ 101 [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */ 102 [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */ 103 [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */ 104 [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */ 105 [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */ 106 [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */ 107 [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */ 108 [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */ 109 [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */ 110 [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */ 111 [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */ 112 [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */ 113 [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */ 114 [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */ 115 [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */ 116 [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */ 117 }; 118 119 static const char * const eclk_parent_names[] = { "mpll", "hpll", "dpll" }; 120 121 static const struct clk_div_table ast2600_eclk_div_table[] = { 122 { 0x0, 2 }, 123 { 0x1, 2 }, 124 { 0x2, 3 }, 125 { 0x3, 4 }, 126 { 0x4, 5 }, 127 { 0x5, 6 }, 128 { 0x6, 7 }, 129 { 0x7, 8 }, 130 { 0 } 131 }; 132 133 static const struct clk_div_table ast2600_mac_div_table[] = { 134 { 0x0, 4 }, 135 { 0x1, 4 }, 136 { 0x2, 6 }, 137 { 0x3, 8 }, 138 { 0x4, 10 }, 139 { 0x5, 12 }, 140 { 0x6, 14 }, 141 { 0x7, 16 }, 142 { 0 } 143 }; 144 145 static const struct clk_div_table ast2600_div_table[] = { 146 { 0x0, 4 }, 147 { 0x1, 8 }, 148 { 0x2, 12 }, 149 { 0x3, 16 }, 150 { 0x4, 20 }, 151 { 0x5, 24 }, 152 { 0x6, 28 }, 153 { 0x7, 32 }, 154 { 0 } 155 }; 156 157 /* For hpll/dpll/epll/mpll */ 158 static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) 159 { 160 unsigned int mult, div; 161 162 if (val & BIT(24)) { 163 /* Pass through mode */ 164 mult = div = 1; 165 } else { 166 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 167 u32 m = val & 0x1fff; 168 u32 n = (val >> 13) & 0x3f; 169 u32 p = (val >> 19) & 0xf; 170 mult = (m + 1) / (n + 1); 171 div = (p + 1); 172 } 173 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, 174 mult, div); 175 }; 176 177 static struct clk_hw *ast2600_calc_apll(const char *name, u32 val) 178 { 179 unsigned int mult, div; 180 181 if (val & BIT(20)) { 182 /* Pass through mode */ 183 mult = div = 1; 184 } else { 185 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 186 u32 m = (val >> 5) & 0x3f; 187 u32 od = (val >> 4) & 0x1; 188 u32 n = val & 0xf; 189 190 mult = (2 - od) * (m + 2); 191 div = n + 1; 192 } 193 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, 194 mult, div); 195 }; 196 197 static u32 get_bit(u8 idx) 198 { 199 return BIT(idx % 32); 200 } 201 202 static u32 get_reset_reg(struct aspeed_clk_gate *gate) 203 { 204 if (gate->reset_idx < 32) 205 return ASPEED_G6_RESET_CTRL; 206 207 return ASPEED_G6_RESET_CTRL2; 208 } 209 210 static u32 get_clock_reg(struct aspeed_clk_gate *gate) 211 { 212 if (gate->clock_idx < 32) 213 return ASPEED_G6_CLK_STOP_CTRL; 214 215 return ASPEED_G6_CLK_STOP_CTRL2; 216 } 217 218 static int aspeed_g6_clk_is_enabled(struct clk_hw *hw) 219 { 220 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); 221 u32 clk = get_bit(gate->clock_idx); 222 u32 rst = get_bit(gate->reset_idx); 223 u32 reg; 224 u32 enval; 225 226 /* 227 * If the IP is in reset, treat the clock as not enabled, 228 * this happens with some clocks such as the USB one when 229 * coming from cold reset. Without this, aspeed_clk_enable() 230 * will fail to lift the reset. 231 */ 232 if (gate->reset_idx >= 0) { 233 regmap_read(gate->map, get_reset_reg(gate), ®); 234 235 if (reg & rst) 236 return 0; 237 } 238 239 regmap_read(gate->map, get_clock_reg(gate), ®); 240 241 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; 242 243 return ((reg & clk) == enval) ? 1 : 0; 244 } 245 246 static int aspeed_g6_clk_enable(struct clk_hw *hw) 247 { 248 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); 249 unsigned long flags; 250 u32 clk = get_bit(gate->clock_idx); 251 u32 rst = get_bit(gate->reset_idx); 252 253 spin_lock_irqsave(gate->lock, flags); 254 255 if (aspeed_g6_clk_is_enabled(hw)) { 256 spin_unlock_irqrestore(gate->lock, flags); 257 return 0; 258 } 259 260 if (gate->reset_idx >= 0) { 261 /* Put IP in reset */ 262 regmap_write(gate->map, get_reset_reg(gate), rst); 263 /* Delay 100us */ 264 udelay(100); 265 } 266 267 /* Enable clock */ 268 if (gate->flags & CLK_GATE_SET_TO_DISABLE) { 269 regmap_write(gate->map, get_clock_reg(gate), clk); 270 } else { 271 /* Use set to clear register */ 272 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk); 273 } 274 275 if (gate->reset_idx >= 0) { 276 /* A delay of 10ms is specified by the ASPEED docs */ 277 mdelay(10); 278 /* Take IP out of reset */ 279 regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst); 280 } 281 282 spin_unlock_irqrestore(gate->lock, flags); 283 284 return 0; 285 } 286 287 static void aspeed_g6_clk_disable(struct clk_hw *hw) 288 { 289 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); 290 unsigned long flags; 291 u32 clk = get_bit(gate->clock_idx); 292 293 spin_lock_irqsave(gate->lock, flags); 294 295 if (gate->flags & CLK_GATE_SET_TO_DISABLE) { 296 regmap_write(gate->map, get_clock_reg(gate), clk); 297 } else { 298 /* Use set to clear register */ 299 regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk); 300 } 301 302 spin_unlock_irqrestore(gate->lock, flags); 303 } 304 305 static const struct clk_ops aspeed_g6_clk_gate_ops = { 306 .enable = aspeed_g6_clk_enable, 307 .disable = aspeed_g6_clk_disable, 308 .is_enabled = aspeed_g6_clk_is_enabled, 309 }; 310 311 static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev, 312 unsigned long id) 313 { 314 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 315 u32 rst = get_bit(id); 316 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; 317 318 /* Use set to clear register */ 319 return regmap_write(ar->map, reg + 0x04, rst); 320 } 321 322 static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev, 323 unsigned long id) 324 { 325 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 326 u32 rst = get_bit(id); 327 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; 328 329 return regmap_write(ar->map, reg, rst); 330 } 331 332 static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev, 333 unsigned long id) 334 { 335 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 336 int ret; 337 u32 val; 338 u32 rst = get_bit(id); 339 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; 340 341 ret = regmap_read(ar->map, reg, &val); 342 if (ret) 343 return ret; 344 345 return !!(val & rst); 346 } 347 348 static const struct reset_control_ops aspeed_g6_reset_ops = { 349 .assert = aspeed_g6_reset_assert, 350 .deassert = aspeed_g6_reset_deassert, 351 .status = aspeed_g6_reset_status, 352 }; 353 354 static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev, 355 const char *name, const char *parent_name, unsigned long flags, 356 struct regmap *map, u8 clock_idx, u8 reset_idx, 357 u8 clk_gate_flags, spinlock_t *lock) 358 { 359 struct aspeed_clk_gate *gate; 360 struct clk_init_data init; 361 struct clk_hw *hw; 362 int ret; 363 364 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 365 if (!gate) 366 return ERR_PTR(-ENOMEM); 367 368 init.name = name; 369 init.ops = &aspeed_g6_clk_gate_ops; 370 init.flags = flags; 371 init.parent_names = parent_name ? &parent_name : NULL; 372 init.num_parents = parent_name ? 1 : 0; 373 374 gate->map = map; 375 gate->clock_idx = clock_idx; 376 gate->reset_idx = reset_idx; 377 gate->flags = clk_gate_flags; 378 gate->lock = lock; 379 gate->hw.init = &init; 380 381 hw = &gate->hw; 382 ret = clk_hw_register(dev, hw); 383 if (ret) { 384 kfree(gate); 385 hw = ERR_PTR(ret); 386 } 387 388 return hw; 389 } 390 391 static const char * const vclk_parent_names[] = { 392 "dpll", 393 "d1pll", 394 "hclk", 395 "mclk", 396 }; 397 398 static const char * const d1clk_parent_names[] = { 399 "dpll", 400 "epll", 401 "usb-phy-40m", 402 "gpioc6_clkin", 403 "dp_phy_pll", 404 }; 405 406 static int aspeed_g6_clk_probe(struct platform_device *pdev) 407 { 408 struct device *dev = &pdev->dev; 409 struct aspeed_reset *ar; 410 struct regmap *map; 411 struct clk_hw *hw; 412 u32 val, rate; 413 int i, ret; 414 415 map = syscon_node_to_regmap(dev->of_node); 416 if (IS_ERR(map)) { 417 dev_err(dev, "no syscon regmap\n"); 418 return PTR_ERR(map); 419 } 420 421 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); 422 if (!ar) 423 return -ENOMEM; 424 425 ar->map = map; 426 427 ar->rcdev.owner = THIS_MODULE; 428 ar->rcdev.nr_resets = 64; 429 ar->rcdev.ops = &aspeed_g6_reset_ops; 430 ar->rcdev.of_node = dev->of_node; 431 432 ret = devm_reset_controller_register(dev, &ar->rcdev); 433 if (ret) { 434 dev_err(dev, "could not register reset controller\n"); 435 return ret; 436 } 437 438 /* UART clock div13 setting */ 439 regmap_read(map, ASPEED_G6_MISC_CTRL, &val); 440 if (val & UART_DIV13_EN) 441 rate = 24000000 / 13; 442 else 443 rate = 24000000; 444 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); 445 if (IS_ERR(hw)) 446 return PTR_ERR(hw); 447 aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw; 448 449 /* UART6~13 clock div13 setting */ 450 regmap_read(map, 0x80, &val); 451 if (val & BIT(31)) 452 rate = 24000000 / 13; 453 else 454 rate = 24000000; 455 hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate); 456 if (IS_ERR(hw)) 457 return PTR_ERR(hw); 458 aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw; 459 460 /* EMMC ext clock divider */ 461 hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0, 462 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0, 463 &aspeed_g6_clk_lock); 464 if (IS_ERR(hw)) 465 return PTR_ERR(hw); 466 hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0, 467 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0, 468 ast2600_div_table, 469 &aspeed_g6_clk_lock); 470 if (IS_ERR(hw)) 471 return PTR_ERR(hw); 472 aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw; 473 474 /* SD/SDIO clock divider and gate */ 475 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0, 476 scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0, 477 &aspeed_g6_clk_lock); 478 if (IS_ERR(hw)) 479 return PTR_ERR(hw); 480 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", 481 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, 482 ast2600_div_table, 483 &aspeed_g6_clk_lock); 484 if (IS_ERR(hw)) 485 return PTR_ERR(hw); 486 aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw; 487 488 /* MAC1/2 AHB bus clock divider */ 489 hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0, 490 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0, 491 ast2600_mac_div_table, 492 &aspeed_g6_clk_lock); 493 if (IS_ERR(hw)) 494 return PTR_ERR(hw); 495 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw; 496 497 /* MAC3/4 AHB bus clock divider */ 498 hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0, 499 scu_g6_base + 0x310, 24, 3, 0, 500 ast2600_mac_div_table, 501 &aspeed_g6_clk_lock); 502 if (IS_ERR(hw)) 503 return PTR_ERR(hw); 504 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw; 505 506 /* LPC Host (LHCLK) clock divider */ 507 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, 508 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0, 509 ast2600_div_table, 510 &aspeed_g6_clk_lock); 511 if (IS_ERR(hw)) 512 return PTR_ERR(hw); 513 aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw; 514 515 /* gfx d1clk : use dp clk */ 516 regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10)); 517 /* SoC Display clock selection */ 518 hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names, 519 ARRAY_SIZE(d1clk_parent_names), 0, 520 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0, 521 &aspeed_g6_clk_lock); 522 if (IS_ERR(hw)) 523 return PTR_ERR(hw); 524 aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw; 525 526 /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */ 527 regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */ 528 529 /* P-Bus (BCLK) clock divider */ 530 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, 531 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0, 532 ast2600_div_table, 533 &aspeed_g6_clk_lock); 534 if (IS_ERR(hw)) 535 return PTR_ERR(hw); 536 aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw; 537 538 /* Video Capture clock selection */ 539 hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names, 540 ARRAY_SIZE(vclk_parent_names), 0, 541 scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0, 542 &aspeed_g6_clk_lock); 543 if (IS_ERR(hw)) 544 return PTR_ERR(hw); 545 aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw; 546 547 /* Video Engine clock divider */ 548 hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0, 549 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0, 550 ast2600_eclk_div_table, 551 &aspeed_g6_clk_lock); 552 if (IS_ERR(hw)) 553 return PTR_ERR(hw); 554 aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw; 555 556 for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) { 557 const struct aspeed_gate_data *gd = &aspeed_g6_gates[i]; 558 u32 gate_flags; 559 560 /* 561 * Special case: the USB port 1 clock (bit 14) is always 562 * working the opposite way from the other ones. 563 */ 564 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE; 565 hw = aspeed_g6_clk_hw_register_gate(dev, 566 gd->name, 567 gd->parent_name, 568 gd->flags, 569 map, 570 gd->clock_idx, 571 gd->reset_idx, 572 gate_flags, 573 &aspeed_g6_clk_lock); 574 if (IS_ERR(hw)) 575 return PTR_ERR(hw); 576 aspeed_g6_clk_data->hws[i] = hw; 577 } 578 579 return 0; 580 }; 581 582 static const struct of_device_id aspeed_g6_clk_dt_ids[] = { 583 { .compatible = "aspeed,ast2600-scu" }, 584 { } 585 }; 586 587 static struct platform_driver aspeed_g6_clk_driver = { 588 .probe = aspeed_g6_clk_probe, 589 .driver = { 590 .name = "ast2600-clk", 591 .of_match_table = aspeed_g6_clk_dt_ids, 592 .suppress_bind_attrs = true, 593 }, 594 }; 595 builtin_platform_driver(aspeed_g6_clk_driver); 596 597 static const u32 ast2600_a0_axi_ahb_div_table[] = { 598 2, 2, 3, 5, 599 }; 600 601 static const u32 ast2600_a1_axi_ahb_div_table[] = { 602 4, 6, 2, 4, 603 }; 604 605 static void __init aspeed_g6_cc(struct regmap *map) 606 { 607 struct clk_hw *hw; 608 u32 val, div, chip_id, axi_div, ahb_div; 609 610 clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000); 611 612 /* 613 * High-speed PLL clock derived from the crystal. This the CPU clock, 614 * and we assume that it is enabled 615 */ 616 regmap_read(map, ASPEED_HPLL_PARAM, &val); 617 aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val); 618 619 regmap_read(map, ASPEED_MPLL_PARAM, &val); 620 aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val); 621 622 regmap_read(map, ASPEED_DPLL_PARAM, &val); 623 aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val); 624 625 regmap_read(map, ASPEED_EPLL_PARAM, &val); 626 aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val); 627 628 regmap_read(map, ASPEED_APLL_PARAM, &val); 629 aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val); 630 631 /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/ 632 regmap_read(map, ASPEED_G6_STRAP1, &val); 633 if (val & BIT(16)) 634 axi_div = 1; 635 else 636 axi_div = 2; 637 638 regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id); 639 if (chip_id & BIT(16)) 640 ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3]; 641 else 642 ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3]; 643 644 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div); 645 aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw; 646 647 regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val); 648 val = (val >> 23) & 0x7; 649 div = 4 * (val + 1); 650 hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div); 651 aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw; 652 653 regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val); 654 val = (val >> 9) & 0x7; 655 div = 2 * (val + 1); 656 hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div); 657 aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw; 658 659 /* USB 2.0 port1 phy 40MHz clock */ 660 hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000); 661 aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw; 662 }; 663 664 static void __init aspeed_g6_cc_init(struct device_node *np) 665 { 666 struct regmap *map; 667 int ret; 668 int i; 669 670 scu_g6_base = of_iomap(np, 0); 671 if (!scu_g6_base) 672 return; 673 674 aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws, 675 ASPEED_G6_NUM_CLKS), GFP_KERNEL); 676 if (!aspeed_g6_clk_data) 677 return; 678 679 /* 680 * This way all clocks fetched before the platform device probes, 681 * except those we assign here for early use, will be deferred. 682 */ 683 for (i = 0; i < ASPEED_G6_NUM_CLKS; i++) 684 aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 685 686 /* 687 * We check that the regmap works on this very first access, 688 * but as this is an MMIO-backed regmap, subsequent regmap 689 * access is not going to fail and we skip error checks from 690 * this point. 691 */ 692 map = syscon_node_to_regmap(np); 693 if (IS_ERR(map)) { 694 pr_err("no syscon regmap\n"); 695 return; 696 } 697 698 aspeed_g6_cc(map); 699 aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS; 700 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data); 701 if (ret) 702 pr_err("failed to add DT provider: %d\n", ret); 703 }; 704 CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init); 705