1*3730fe60SJoakim Zhang# SPDX-License-Identifier: GPL-2.0 2*3730fe60SJoakim Zhang# Audio subsystem clock support for Cixtech SoC family 3*3730fe60SJoakim Zhangmenu "Cixtech Audio Subsystem Clock Driver" 4*3730fe60SJoakim Zhang 5*3730fe60SJoakim Zhangconfig CLK_SKY1_AUDSS 6*3730fe60SJoakim Zhang tristate "Cixtech Sky1 Audio Subsystem Clock Driver" 7*3730fe60SJoakim Zhang depends on ARCH_CIX || COMPILE_TEST 8*3730fe60SJoakim Zhang select AUXILIARY_BUS 9*3730fe60SJoakim Zhang select REGMAP_MMIO 10*3730fe60SJoakim Zhang select RESET_CONTROLLER 11*3730fe60SJoakim Zhang help 12*3730fe60SJoakim Zhang Support for the Audio Subsystem clock controller present on 13*3730fe60SJoakim Zhang Cixtech Sky1 SoC. This driver provides mux, divider and gate 14*3730fe60SJoakim Zhang clocks for DSP, I2S, HDA and related blocks in the audio 15*3730fe60SJoakim Zhang subsystem. Say M or Y here if you want to build this driver. 16*3730fe60SJoakim Zhangendmenu 17