1 /* 2 * Copyright (C) 2014 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/err.h> 16 #include <linux/clk-provider.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/clkdev.h> 20 #include <linux/of_address.h> 21 #include <linux/delay.h> 22 23 #include "clk-iproc.h" 24 25 struct iproc_asiu; 26 27 struct iproc_asiu_clk { 28 struct clk_hw hw; 29 const char *name; 30 struct iproc_asiu *asiu; 31 unsigned long rate; 32 struct iproc_asiu_div div; 33 struct iproc_asiu_gate gate; 34 }; 35 36 struct iproc_asiu { 37 void __iomem *div_base; 38 void __iomem *gate_base; 39 40 struct clk_onecell_data clk_data; 41 struct iproc_asiu_clk *clks; 42 }; 43 44 #define to_asiu_clk(hw) container_of(hw, struct iproc_asiu_clk, hw) 45 46 static int iproc_asiu_clk_enable(struct clk_hw *hw) 47 { 48 struct iproc_asiu_clk *clk = to_asiu_clk(hw); 49 struct iproc_asiu *asiu = clk->asiu; 50 u32 val; 51 52 /* some clocks at the ASIU level are always enabled */ 53 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) 54 return 0; 55 56 val = readl(asiu->gate_base + clk->gate.offset); 57 val |= (1 << clk->gate.en_shift); 58 writel(val, asiu->gate_base + clk->gate.offset); 59 60 return 0; 61 } 62 63 static void iproc_asiu_clk_disable(struct clk_hw *hw) 64 { 65 struct iproc_asiu_clk *clk = to_asiu_clk(hw); 66 struct iproc_asiu *asiu = clk->asiu; 67 u32 val; 68 69 /* some clocks at the ASIU level are always enabled */ 70 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) 71 return; 72 73 val = readl(asiu->gate_base + clk->gate.offset); 74 val &= ~(1 << clk->gate.en_shift); 75 writel(val, asiu->gate_base + clk->gate.offset); 76 } 77 78 static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw, 79 unsigned long parent_rate) 80 { 81 struct iproc_asiu_clk *clk = to_asiu_clk(hw); 82 struct iproc_asiu *asiu = clk->asiu; 83 u32 val; 84 unsigned int div_h, div_l; 85 86 if (parent_rate == 0) { 87 clk->rate = 0; 88 return 0; 89 } 90 91 /* if clock divisor is not enabled, simply return parent rate */ 92 val = readl(asiu->div_base + clk->div.offset); 93 if ((val & (1 << clk->div.en_shift)) == 0) { 94 clk->rate = parent_rate; 95 return parent_rate; 96 } 97 98 /* clock rate = parent rate / (high_div + 1) + (low_div + 1) */ 99 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); 100 div_h++; 101 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); 102 div_l++; 103 104 clk->rate = parent_rate / (div_h + div_l); 105 pr_debug("%s: rate: %lu. parent rate: %lu div_h: %u div_l: %u\n", 106 __func__, clk->rate, parent_rate, div_h, div_l); 107 108 return clk->rate; 109 } 110 111 static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate, 112 unsigned long *parent_rate) 113 { 114 unsigned int div; 115 116 if (rate == 0 || *parent_rate == 0) 117 return -EINVAL; 118 119 if (rate == *parent_rate) 120 return *parent_rate; 121 122 div = DIV_ROUND_UP(*parent_rate, rate); 123 if (div < 2) 124 return *parent_rate; 125 126 return *parent_rate / div; 127 } 128 129 static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate, 130 unsigned long parent_rate) 131 { 132 struct iproc_asiu_clk *clk = to_asiu_clk(hw); 133 struct iproc_asiu *asiu = clk->asiu; 134 unsigned int div, div_h, div_l; 135 u32 val; 136 137 if (rate == 0 || parent_rate == 0) 138 return -EINVAL; 139 140 /* simply disable the divisor if one wants the same rate as parent */ 141 if (rate == parent_rate) { 142 val = readl(asiu->div_base + clk->div.offset); 143 val &= ~(1 << clk->div.en_shift); 144 writel(val, asiu->div_base + clk->div.offset); 145 return 0; 146 } 147 148 div = DIV_ROUND_UP(parent_rate, rate); 149 if (div < 2) 150 return -EINVAL; 151 152 div_h = div_l = div >> 1; 153 div_h--; 154 div_l--; 155 156 val = readl(asiu->div_base + clk->div.offset); 157 val |= 1 << clk->div.en_shift; 158 if (div_h) { 159 val &= ~(bit_mask(clk->div.high_width) 160 << clk->div.high_shift); 161 val |= div_h << clk->div.high_shift; 162 } else { 163 val &= ~(bit_mask(clk->div.high_width) 164 << clk->div.high_shift); 165 } 166 if (div_l) { 167 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift); 168 val |= div_l << clk->div.low_shift; 169 } else { 170 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift); 171 } 172 writel(val, asiu->div_base + clk->div.offset); 173 174 return 0; 175 } 176 177 static const struct clk_ops iproc_asiu_ops = { 178 .enable = iproc_asiu_clk_enable, 179 .disable = iproc_asiu_clk_disable, 180 .recalc_rate = iproc_asiu_clk_recalc_rate, 181 .round_rate = iproc_asiu_clk_round_rate, 182 .set_rate = iproc_asiu_clk_set_rate, 183 }; 184 185 void __init iproc_asiu_setup(struct device_node *node, 186 const struct iproc_asiu_div *div, 187 const struct iproc_asiu_gate *gate, 188 unsigned int num_clks) 189 { 190 int i, ret; 191 struct iproc_asiu *asiu; 192 193 if (WARN_ON(!gate || !div)) 194 return; 195 196 asiu = kzalloc(sizeof(*asiu), GFP_KERNEL); 197 if (WARN_ON(!asiu)) 198 return; 199 200 asiu->clk_data.clk_num = num_clks; 201 asiu->clk_data.clks = kcalloc(num_clks, sizeof(*asiu->clk_data.clks), 202 GFP_KERNEL); 203 if (WARN_ON(!asiu->clk_data.clks)) 204 goto err_clks; 205 206 asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL); 207 if (WARN_ON(!asiu->clks)) 208 goto err_asiu_clks; 209 210 asiu->div_base = of_iomap(node, 0); 211 if (WARN_ON(!asiu->div_base)) 212 goto err_iomap_div; 213 214 asiu->gate_base = of_iomap(node, 1); 215 if (WARN_ON(!asiu->gate_base)) 216 goto err_iomap_gate; 217 218 for (i = 0; i < num_clks; i++) { 219 struct clk_init_data init; 220 struct clk *clk; 221 const char *parent_name; 222 struct iproc_asiu_clk *asiu_clk; 223 const char *clk_name; 224 225 ret = of_property_read_string_index(node, "clock-output-names", 226 i, &clk_name); 227 if (WARN_ON(ret)) 228 goto err_clk_register; 229 230 asiu_clk = &asiu->clks[i]; 231 asiu_clk->name = clk_name; 232 asiu_clk->asiu = asiu; 233 asiu_clk->div = div[i]; 234 asiu_clk->gate = gate[i]; 235 init.name = clk_name; 236 init.ops = &iproc_asiu_ops; 237 init.flags = 0; 238 parent_name = of_clk_get_parent_name(node, 0); 239 init.parent_names = (parent_name ? &parent_name : NULL); 240 init.num_parents = (parent_name ? 1 : 0); 241 asiu_clk->hw.init = &init; 242 243 clk = clk_register(NULL, &asiu_clk->hw); 244 if (WARN_ON(IS_ERR(clk))) 245 goto err_clk_register; 246 asiu->clk_data.clks[i] = clk; 247 } 248 249 ret = of_clk_add_provider(node, of_clk_src_onecell_get, 250 &asiu->clk_data); 251 if (WARN_ON(ret)) 252 goto err_clk_register; 253 254 return; 255 256 err_clk_register: 257 for (i = 0; i < num_clks; i++) 258 clk_unregister(asiu->clk_data.clks[i]); 259 iounmap(asiu->gate_base); 260 261 err_iomap_gate: 262 iounmap(asiu->div_base); 263 264 err_iomap_div: 265 kfree(asiu->clks); 266 267 err_asiu_clks: 268 kfree(asiu->clk_data.clks); 269 270 err_clks: 271 kfree(asiu); 272 } 273