1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2010,2015 Broadcom 4 * Copyright (C) 2012 Stephen Warren 5 */ 6 7 /** 8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain) 9 * 10 * The clock tree on the 2835 has several levels. There's a root 11 * oscillator running at 19.2Mhz. After the oscillator there are 5 12 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays", 13 * and "HDMI displays". Those 5 PLLs each can divide their output to 14 * produce up to 4 channels. Finally, there is the level of clocks to 15 * be consumed by other hardware components (like "H264" or "HDMI 16 * state machine"), which divide off of some subset of the PLL 17 * channels. 18 * 19 * All of the clocks in the tree are exposed in the DT, because the DT 20 * may want to make assignments of the final layer of clocks to the 21 * PLL channels, and some components of the hardware will actually 22 * skip layers of the tree (for example, the pixel clock comes 23 * directly from the PLLH PIX channel without using a CM_*CTL clock 24 * generator). 25 */ 26 27 #include <linux/clk-provider.h> 28 #include <linux/clkdev.h> 29 #include <linux/clk.h> 30 #include <linux/debugfs.h> 31 #include <linux/delay.h> 32 #include <linux/io.h> 33 #include <linux/module.h> 34 #include <linux/of.h> 35 #include <linux/platform_device.h> 36 #include <linux/slab.h> 37 #include <dt-bindings/clock/bcm2835.h> 38 39 #define CM_PASSWORD 0x5a000000 40 41 #define CM_GNRICCTL 0x000 42 #define CM_GNRICDIV 0x004 43 # define CM_DIV_FRAC_BITS 12 44 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0) 45 46 #define CM_VPUCTL 0x008 47 #define CM_VPUDIV 0x00c 48 #define CM_SYSCTL 0x010 49 #define CM_SYSDIV 0x014 50 #define CM_PERIACTL 0x018 51 #define CM_PERIADIV 0x01c 52 #define CM_PERIICTL 0x020 53 #define CM_PERIIDIV 0x024 54 #define CM_H264CTL 0x028 55 #define CM_H264DIV 0x02c 56 #define CM_ISPCTL 0x030 57 #define CM_ISPDIV 0x034 58 #define CM_V3DCTL 0x038 59 #define CM_V3DDIV 0x03c 60 #define CM_CAM0CTL 0x040 61 #define CM_CAM0DIV 0x044 62 #define CM_CAM1CTL 0x048 63 #define CM_CAM1DIV 0x04c 64 #define CM_CCP2CTL 0x050 65 #define CM_CCP2DIV 0x054 66 #define CM_DSI0ECTL 0x058 67 #define CM_DSI0EDIV 0x05c 68 #define CM_DSI0PCTL 0x060 69 #define CM_DSI0PDIV 0x064 70 #define CM_DPICTL 0x068 71 #define CM_DPIDIV 0x06c 72 #define CM_GP0CTL 0x070 73 #define CM_GP0DIV 0x074 74 #define CM_GP1CTL 0x078 75 #define CM_GP1DIV 0x07c 76 #define CM_GP2CTL 0x080 77 #define CM_GP2DIV 0x084 78 #define CM_HSMCTL 0x088 79 #define CM_HSMDIV 0x08c 80 #define CM_OTPCTL 0x090 81 #define CM_OTPDIV 0x094 82 #define CM_PCMCTL 0x098 83 #define CM_PCMDIV 0x09c 84 #define CM_PWMCTL 0x0a0 85 #define CM_PWMDIV 0x0a4 86 #define CM_SLIMCTL 0x0a8 87 #define CM_SLIMDIV 0x0ac 88 #define CM_SMICTL 0x0b0 89 #define CM_SMIDIV 0x0b4 90 /* no definition for 0x0b8 and 0x0bc */ 91 #define CM_TCNTCTL 0x0c0 92 # define CM_TCNT_SRC1_SHIFT 12 93 #define CM_TCNTCNT 0x0c4 94 #define CM_TECCTL 0x0c8 95 #define CM_TECDIV 0x0cc 96 #define CM_TD0CTL 0x0d0 97 #define CM_TD0DIV 0x0d4 98 #define CM_TD1CTL 0x0d8 99 #define CM_TD1DIV 0x0dc 100 #define CM_TSENSCTL 0x0e0 101 #define CM_TSENSDIV 0x0e4 102 #define CM_TIMERCTL 0x0e8 103 #define CM_TIMERDIV 0x0ec 104 #define CM_UARTCTL 0x0f0 105 #define CM_UARTDIV 0x0f4 106 #define CM_VECCTL 0x0f8 107 #define CM_VECDIV 0x0fc 108 #define CM_PULSECTL 0x190 109 #define CM_PULSEDIV 0x194 110 #define CM_SDCCTL 0x1a8 111 #define CM_SDCDIV 0x1ac 112 #define CM_ARMCTL 0x1b0 113 #define CM_AVEOCTL 0x1b8 114 #define CM_AVEODIV 0x1bc 115 #define CM_EMMCCTL 0x1c0 116 #define CM_EMMCDIV 0x1c4 117 118 /* General bits for the CM_*CTL regs */ 119 # define CM_ENABLE BIT(4) 120 # define CM_KILL BIT(5) 121 # define CM_GATE_BIT 6 122 # define CM_GATE BIT(CM_GATE_BIT) 123 # define CM_BUSY BIT(7) 124 # define CM_BUSYD BIT(8) 125 # define CM_FRAC BIT(9) 126 # define CM_SRC_SHIFT 0 127 # define CM_SRC_BITS 4 128 # define CM_SRC_MASK 0xf 129 # define CM_SRC_GND 0 130 # define CM_SRC_OSC 1 131 # define CM_SRC_TESTDEBUG0 2 132 # define CM_SRC_TESTDEBUG1 3 133 # define CM_SRC_PLLA_CORE 4 134 # define CM_SRC_PLLA_PER 4 135 # define CM_SRC_PLLC_CORE0 5 136 # define CM_SRC_PLLC_PER 5 137 # define CM_SRC_PLLC_CORE1 8 138 # define CM_SRC_PLLD_CORE 6 139 # define CM_SRC_PLLD_PER 6 140 # define CM_SRC_PLLH_AUX 7 141 # define CM_SRC_PLLC_CORE1 8 142 # define CM_SRC_PLLC_CORE2 9 143 144 #define CM_OSCCOUNT 0x100 145 146 #define CM_PLLA 0x104 147 # define CM_PLL_ANARST BIT(8) 148 # define CM_PLLA_HOLDPER BIT(7) 149 # define CM_PLLA_LOADPER BIT(6) 150 # define CM_PLLA_HOLDCORE BIT(5) 151 # define CM_PLLA_LOADCORE BIT(4) 152 # define CM_PLLA_HOLDCCP2 BIT(3) 153 # define CM_PLLA_LOADCCP2 BIT(2) 154 # define CM_PLLA_HOLDDSI0 BIT(1) 155 # define CM_PLLA_LOADDSI0 BIT(0) 156 157 #define CM_PLLC 0x108 158 # define CM_PLLC_HOLDPER BIT(7) 159 # define CM_PLLC_LOADPER BIT(6) 160 # define CM_PLLC_HOLDCORE2 BIT(5) 161 # define CM_PLLC_LOADCORE2 BIT(4) 162 # define CM_PLLC_HOLDCORE1 BIT(3) 163 # define CM_PLLC_LOADCORE1 BIT(2) 164 # define CM_PLLC_HOLDCORE0 BIT(1) 165 # define CM_PLLC_LOADCORE0 BIT(0) 166 167 #define CM_PLLD 0x10c 168 # define CM_PLLD_HOLDPER BIT(7) 169 # define CM_PLLD_LOADPER BIT(6) 170 # define CM_PLLD_HOLDCORE BIT(5) 171 # define CM_PLLD_LOADCORE BIT(4) 172 # define CM_PLLD_HOLDDSI1 BIT(3) 173 # define CM_PLLD_LOADDSI1 BIT(2) 174 # define CM_PLLD_HOLDDSI0 BIT(1) 175 # define CM_PLLD_LOADDSI0 BIT(0) 176 177 #define CM_PLLH 0x110 178 # define CM_PLLH_LOADRCAL BIT(2) 179 # define CM_PLLH_LOADAUX BIT(1) 180 # define CM_PLLH_LOADPIX BIT(0) 181 182 #define CM_LOCK 0x114 183 # define CM_LOCK_FLOCKH BIT(12) 184 # define CM_LOCK_FLOCKD BIT(11) 185 # define CM_LOCK_FLOCKC BIT(10) 186 # define CM_LOCK_FLOCKB BIT(9) 187 # define CM_LOCK_FLOCKA BIT(8) 188 189 #define CM_EVENT 0x118 190 #define CM_DSI1ECTL 0x158 191 #define CM_DSI1EDIV 0x15c 192 #define CM_DSI1PCTL 0x160 193 #define CM_DSI1PDIV 0x164 194 #define CM_DFTCTL 0x168 195 #define CM_DFTDIV 0x16c 196 197 #define CM_PLLB 0x170 198 # define CM_PLLB_HOLDARM BIT(1) 199 # define CM_PLLB_LOADARM BIT(0) 200 201 #define A2W_PLLA_CTRL 0x1100 202 #define A2W_PLLC_CTRL 0x1120 203 #define A2W_PLLD_CTRL 0x1140 204 #define A2W_PLLH_CTRL 0x1160 205 #define A2W_PLLB_CTRL 0x11e0 206 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17) 207 # define A2W_PLL_CTRL_PWRDN BIT(16) 208 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000 209 # define A2W_PLL_CTRL_PDIV_SHIFT 12 210 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff 211 # define A2W_PLL_CTRL_NDIV_SHIFT 0 212 213 #define A2W_PLLA_ANA0 0x1010 214 #define A2W_PLLC_ANA0 0x1030 215 #define A2W_PLLD_ANA0 0x1050 216 #define A2W_PLLH_ANA0 0x1070 217 #define A2W_PLLB_ANA0 0x10f0 218 219 #define A2W_PLL_KA_SHIFT 7 220 #define A2W_PLL_KA_MASK GENMASK(9, 7) 221 #define A2W_PLL_KI_SHIFT 19 222 #define A2W_PLL_KI_MASK GENMASK(21, 19) 223 #define A2W_PLL_KP_SHIFT 15 224 #define A2W_PLL_KP_MASK GENMASK(18, 15) 225 226 #define A2W_PLLH_KA_SHIFT 19 227 #define A2W_PLLH_KA_MASK GENMASK(21, 19) 228 #define A2W_PLLH_KI_LOW_SHIFT 22 229 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22) 230 #define A2W_PLLH_KI_HIGH_SHIFT 0 231 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0) 232 #define A2W_PLLH_KP_SHIFT 1 233 #define A2W_PLLH_KP_MASK GENMASK(4, 1) 234 235 #define A2W_XOSC_CTRL 0x1190 236 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7) 237 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6) 238 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5) 239 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4) 240 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3) 241 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2) 242 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1) 243 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0) 244 245 #define A2W_PLLA_FRAC 0x1200 246 #define A2W_PLLC_FRAC 0x1220 247 #define A2W_PLLD_FRAC 0x1240 248 #define A2W_PLLH_FRAC 0x1260 249 #define A2W_PLLB_FRAC 0x12e0 250 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1) 251 # define A2W_PLL_FRAC_BITS 20 252 253 #define A2W_PLL_CHANNEL_DISABLE BIT(8) 254 #define A2W_PLL_DIV_BITS 8 255 #define A2W_PLL_DIV_SHIFT 0 256 257 #define A2W_PLLA_DSI0 0x1300 258 #define A2W_PLLA_CORE 0x1400 259 #define A2W_PLLA_PER 0x1500 260 #define A2W_PLLA_CCP2 0x1600 261 262 #define A2W_PLLC_CORE2 0x1320 263 #define A2W_PLLC_CORE1 0x1420 264 #define A2W_PLLC_PER 0x1520 265 #define A2W_PLLC_CORE0 0x1620 266 267 #define A2W_PLLD_DSI0 0x1340 268 #define A2W_PLLD_CORE 0x1440 269 #define A2W_PLLD_PER 0x1540 270 #define A2W_PLLD_DSI1 0x1640 271 272 #define A2W_PLLH_AUX 0x1360 273 #define A2W_PLLH_RCAL 0x1460 274 #define A2W_PLLH_PIX 0x1560 275 #define A2W_PLLH_STS 0x1660 276 277 #define A2W_PLLH_CTRLR 0x1960 278 #define A2W_PLLH_FRACR 0x1a60 279 #define A2W_PLLH_AUXR 0x1b60 280 #define A2W_PLLH_RCALR 0x1c60 281 #define A2W_PLLH_PIXR 0x1d60 282 #define A2W_PLLH_STSR 0x1e60 283 284 #define A2W_PLLB_ARM 0x13e0 285 #define A2W_PLLB_SP0 0x14e0 286 #define A2W_PLLB_SP1 0x15e0 287 #define A2W_PLLB_SP2 0x16e0 288 289 #define LOCK_TIMEOUT_NS 100000000 290 #define BCM2835_MAX_FB_RATE 1750000000u 291 292 /* 293 * Names of clocks used within the driver that need to be replaced 294 * with an external parent's name. This array is in the order that 295 * the clocks node in the DT references external clocks. 296 */ 297 static const char *const cprman_parent_names[] = { 298 "xosc", 299 "dsi0_byte", 300 "dsi0_ddr2", 301 "dsi0_ddr", 302 "dsi1_byte", 303 "dsi1_ddr2", 304 "dsi1_ddr", 305 }; 306 307 struct bcm2835_cprman { 308 struct device *dev; 309 void __iomem *regs; 310 spinlock_t regs_lock; /* spinlock for all clocks */ 311 312 /* 313 * Real names of cprman clock parents looked up through 314 * of_clk_get_parent_name(), which will be used in the 315 * parent_names[] arrays for clock registration. 316 */ 317 const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)]; 318 319 /* Must be last */ 320 struct clk_hw_onecell_data onecell; 321 }; 322 323 static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) 324 { 325 writel(CM_PASSWORD | val, cprman->regs + reg); 326 } 327 328 static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg) 329 { 330 return readl(cprman->regs + reg); 331 } 332 333 /* Does a cycle of measuring a clock through the TCNT clock, which may 334 * source from many other clocks in the system. 335 */ 336 static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman, 337 u32 tcnt_mux) 338 { 339 u32 osccount = 19200; /* 1ms */ 340 u32 count; 341 ktime_t timeout; 342 343 spin_lock(&cprman->regs_lock); 344 345 cprman_write(cprman, CM_TCNTCTL, CM_KILL); 346 347 cprman_write(cprman, CM_TCNTCTL, 348 (tcnt_mux & CM_SRC_MASK) | 349 (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT); 350 351 cprman_write(cprman, CM_OSCCOUNT, osccount); 352 353 /* do a kind delay at the start */ 354 mdelay(1); 355 356 /* Finish off whatever is left of OSCCOUNT */ 357 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 358 while (cprman_read(cprman, CM_OSCCOUNT)) { 359 if (ktime_after(ktime_get(), timeout)) { 360 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n"); 361 count = 0; 362 goto out; 363 } 364 cpu_relax(); 365 } 366 367 /* Wait for BUSY to clear. */ 368 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 369 while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) { 370 if (ktime_after(ktime_get(), timeout)) { 371 dev_err(cprman->dev, "timeout waiting for !BUSY\n"); 372 count = 0; 373 goto out; 374 } 375 cpu_relax(); 376 } 377 378 count = cprman_read(cprman, CM_TCNTCNT); 379 380 cprman_write(cprman, CM_TCNTCTL, 0); 381 382 out: 383 spin_unlock(&cprman->regs_lock); 384 385 return count * 1000; 386 } 387 388 static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, 389 struct debugfs_reg32 *regs, size_t nregs, 390 struct dentry *dentry) 391 { 392 struct debugfs_regset32 *regset; 393 394 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL); 395 if (!regset) 396 return; 397 398 regset->regs = regs; 399 regset->nregs = nregs; 400 regset->base = cprman->regs + base; 401 402 debugfs_create_regset32("regdump", S_IRUGO, dentry, regset); 403 } 404 405 struct bcm2835_pll_data { 406 const char *name; 407 u32 cm_ctrl_reg; 408 u32 a2w_ctrl_reg; 409 u32 frac_reg; 410 u32 ana_reg_base; 411 u32 reference_enable_mask; 412 /* Bit in CM_LOCK to indicate when the PLL has locked. */ 413 u32 lock_mask; 414 415 const struct bcm2835_pll_ana_bits *ana; 416 417 unsigned long min_rate; 418 unsigned long max_rate; 419 /* 420 * Highest rate for the VCO before we have to use the 421 * pre-divide-by-2. 422 */ 423 unsigned long max_fb_rate; 424 }; 425 426 struct bcm2835_pll_ana_bits { 427 u32 mask0; 428 u32 set0; 429 u32 mask1; 430 u32 set1; 431 u32 mask3; 432 u32 set3; 433 u32 fb_prediv_mask; 434 }; 435 436 static const struct bcm2835_pll_ana_bits bcm2835_ana_default = { 437 .mask0 = 0, 438 .set0 = 0, 439 .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK, 440 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT), 441 .mask3 = A2W_PLL_KA_MASK, 442 .set3 = (2 << A2W_PLL_KA_SHIFT), 443 .fb_prediv_mask = BIT(14), 444 }; 445 446 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = { 447 .mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK, 448 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT), 449 .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK, 450 .set1 = (6 << A2W_PLLH_KP_SHIFT), 451 .mask3 = 0, 452 .set3 = 0, 453 .fb_prediv_mask = BIT(11), 454 }; 455 456 struct bcm2835_pll_divider_data { 457 const char *name; 458 const char *source_pll; 459 460 u32 cm_reg; 461 u32 a2w_reg; 462 463 u32 load_mask; 464 u32 hold_mask; 465 u32 fixed_divider; 466 u32 flags; 467 }; 468 469 struct bcm2835_clock_data { 470 const char *name; 471 472 const char *const *parents; 473 int num_mux_parents; 474 475 /* Bitmap encoding which parents accept rate change propagation. */ 476 unsigned int set_rate_parent; 477 478 u32 ctl_reg; 479 u32 div_reg; 480 481 /* Number of integer bits in the divider */ 482 u32 int_bits; 483 /* Number of fractional bits in the divider */ 484 u32 frac_bits; 485 486 u32 flags; 487 488 bool is_vpu_clock; 489 bool is_mash_clock; 490 bool low_jitter; 491 492 u32 tcnt_mux; 493 }; 494 495 struct bcm2835_gate_data { 496 const char *name; 497 const char *parent; 498 499 u32 ctl_reg; 500 }; 501 502 struct bcm2835_pll { 503 struct clk_hw hw; 504 struct bcm2835_cprman *cprman; 505 const struct bcm2835_pll_data *data; 506 }; 507 508 static int bcm2835_pll_is_on(struct clk_hw *hw) 509 { 510 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 511 struct bcm2835_cprman *cprman = pll->cprman; 512 const struct bcm2835_pll_data *data = pll->data; 513 514 return cprman_read(cprman, data->a2w_ctrl_reg) & 515 A2W_PLL_CTRL_PRST_DISABLE; 516 } 517 518 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate, 519 unsigned long parent_rate, 520 u32 *ndiv, u32 *fdiv) 521 { 522 u64 div; 523 524 div = (u64)rate << A2W_PLL_FRAC_BITS; 525 do_div(div, parent_rate); 526 527 *ndiv = div >> A2W_PLL_FRAC_BITS; 528 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); 529 } 530 531 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate, 532 u32 ndiv, u32 fdiv, u32 pdiv) 533 { 534 u64 rate; 535 536 if (pdiv == 0) 537 return 0; 538 539 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); 540 do_div(rate, pdiv); 541 return rate >> A2W_PLL_FRAC_BITS; 542 } 543 544 static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate, 545 unsigned long *parent_rate) 546 { 547 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 548 const struct bcm2835_pll_data *data = pll->data; 549 u32 ndiv, fdiv; 550 551 rate = clamp(rate, data->min_rate, data->max_rate); 552 553 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); 554 555 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); 556 } 557 558 static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw, 559 unsigned long parent_rate) 560 { 561 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 562 struct bcm2835_cprman *cprman = pll->cprman; 563 const struct bcm2835_pll_data *data = pll->data; 564 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); 565 u32 ndiv, pdiv, fdiv; 566 bool using_prediv; 567 568 if (parent_rate == 0) 569 return 0; 570 571 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; 572 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT; 573 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT; 574 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & 575 data->ana->fb_prediv_mask; 576 577 if (using_prediv) { 578 ndiv *= 2; 579 fdiv *= 2; 580 } 581 582 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv); 583 } 584 585 static void bcm2835_pll_off(struct clk_hw *hw) 586 { 587 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 588 struct bcm2835_cprman *cprman = pll->cprman; 589 const struct bcm2835_pll_data *data = pll->data; 590 591 spin_lock(&cprman->regs_lock); 592 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST); 593 cprman_write(cprman, data->a2w_ctrl_reg, 594 cprman_read(cprman, data->a2w_ctrl_reg) | 595 A2W_PLL_CTRL_PWRDN); 596 spin_unlock(&cprman->regs_lock); 597 } 598 599 static int bcm2835_pll_on(struct clk_hw *hw) 600 { 601 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 602 struct bcm2835_cprman *cprman = pll->cprman; 603 const struct bcm2835_pll_data *data = pll->data; 604 ktime_t timeout; 605 606 cprman_write(cprman, data->a2w_ctrl_reg, 607 cprman_read(cprman, data->a2w_ctrl_reg) & 608 ~A2W_PLL_CTRL_PWRDN); 609 610 /* Take the PLL out of reset. */ 611 spin_lock(&cprman->regs_lock); 612 cprman_write(cprman, data->cm_ctrl_reg, 613 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); 614 spin_unlock(&cprman->regs_lock); 615 616 /* Wait for the PLL to lock. */ 617 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 618 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { 619 if (ktime_after(ktime_get(), timeout)) { 620 dev_err(cprman->dev, "%s: couldn't lock PLL\n", 621 clk_hw_get_name(hw)); 622 return -ETIMEDOUT; 623 } 624 625 cpu_relax(); 626 } 627 628 cprman_write(cprman, data->a2w_ctrl_reg, 629 cprman_read(cprman, data->a2w_ctrl_reg) | 630 A2W_PLL_CTRL_PRST_DISABLE); 631 632 return 0; 633 } 634 635 static void 636 bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana) 637 { 638 int i; 639 640 /* 641 * ANA register setup is done as a series of writes to 642 * ANA3-ANA0, in that order. This lets us write all 4 643 * registers as a single cycle of the serdes interface (taking 644 * 100 xosc clocks), whereas if we were to update ana0, 1, and 645 * 3 individually through their partial-write registers, each 646 * would be their own serdes cycle. 647 */ 648 for (i = 3; i >= 0; i--) 649 cprman_write(cprman, ana_reg_base + i * 4, ana[i]); 650 } 651 652 static int bcm2835_pll_set_rate(struct clk_hw *hw, 653 unsigned long rate, unsigned long parent_rate) 654 { 655 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 656 struct bcm2835_cprman *cprman = pll->cprman; 657 const struct bcm2835_pll_data *data = pll->data; 658 bool was_using_prediv, use_fb_prediv, do_ana_setup_first; 659 u32 ndiv, fdiv, a2w_ctl; 660 u32 ana[4]; 661 int i; 662 663 if (rate > data->max_fb_rate) { 664 use_fb_prediv = true; 665 rate /= 2; 666 } else { 667 use_fb_prediv = false; 668 } 669 670 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv); 671 672 for (i = 3; i >= 0; i--) 673 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); 674 675 was_using_prediv = ana[1] & data->ana->fb_prediv_mask; 676 677 ana[0] &= ~data->ana->mask0; 678 ana[0] |= data->ana->set0; 679 ana[1] &= ~data->ana->mask1; 680 ana[1] |= data->ana->set1; 681 ana[3] &= ~data->ana->mask3; 682 ana[3] |= data->ana->set3; 683 684 if (was_using_prediv && !use_fb_prediv) { 685 ana[1] &= ~data->ana->fb_prediv_mask; 686 do_ana_setup_first = true; 687 } else if (!was_using_prediv && use_fb_prediv) { 688 ana[1] |= data->ana->fb_prediv_mask; 689 do_ana_setup_first = false; 690 } else { 691 do_ana_setup_first = true; 692 } 693 694 /* Unmask the reference clock from the oscillator. */ 695 spin_lock(&cprman->regs_lock); 696 cprman_write(cprman, A2W_XOSC_CTRL, 697 cprman_read(cprman, A2W_XOSC_CTRL) | 698 data->reference_enable_mask); 699 spin_unlock(&cprman->regs_lock); 700 701 if (do_ana_setup_first) 702 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); 703 704 /* Set the PLL multiplier from the oscillator. */ 705 cprman_write(cprman, data->frac_reg, fdiv); 706 707 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); 708 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK; 709 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT; 710 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK; 711 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT; 712 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); 713 714 if (!do_ana_setup_first) 715 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); 716 717 return 0; 718 } 719 720 static void bcm2835_pll_debug_init(struct clk_hw *hw, 721 struct dentry *dentry) 722 { 723 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 724 struct bcm2835_cprman *cprman = pll->cprman; 725 const struct bcm2835_pll_data *data = pll->data; 726 struct debugfs_reg32 *regs; 727 728 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL); 729 if (!regs) 730 return; 731 732 regs[0].name = "cm_ctrl"; 733 regs[0].offset = data->cm_ctrl_reg; 734 regs[1].name = "a2w_ctrl"; 735 regs[1].offset = data->a2w_ctrl_reg; 736 regs[2].name = "frac"; 737 regs[2].offset = data->frac_reg; 738 regs[3].name = "ana0"; 739 regs[3].offset = data->ana_reg_base + 0 * 4; 740 regs[4].name = "ana1"; 741 regs[4].offset = data->ana_reg_base + 1 * 4; 742 regs[5].name = "ana2"; 743 regs[5].offset = data->ana_reg_base + 2 * 4; 744 regs[6].name = "ana3"; 745 regs[6].offset = data->ana_reg_base + 3 * 4; 746 747 bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry); 748 } 749 750 static const struct clk_ops bcm2835_pll_clk_ops = { 751 .is_prepared = bcm2835_pll_is_on, 752 .prepare = bcm2835_pll_on, 753 .unprepare = bcm2835_pll_off, 754 .recalc_rate = bcm2835_pll_get_rate, 755 .set_rate = bcm2835_pll_set_rate, 756 .round_rate = bcm2835_pll_round_rate, 757 .debug_init = bcm2835_pll_debug_init, 758 }; 759 760 struct bcm2835_pll_divider { 761 struct clk_divider div; 762 struct bcm2835_cprman *cprman; 763 const struct bcm2835_pll_divider_data *data; 764 }; 765 766 static struct bcm2835_pll_divider * 767 bcm2835_pll_divider_from_hw(struct clk_hw *hw) 768 { 769 return container_of(hw, struct bcm2835_pll_divider, div.hw); 770 } 771 772 static int bcm2835_pll_divider_is_on(struct clk_hw *hw) 773 { 774 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 775 struct bcm2835_cprman *cprman = divider->cprman; 776 const struct bcm2835_pll_divider_data *data = divider->data; 777 778 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); 779 } 780 781 static long bcm2835_pll_divider_round_rate(struct clk_hw *hw, 782 unsigned long rate, 783 unsigned long *parent_rate) 784 { 785 return clk_divider_ops.round_rate(hw, rate, parent_rate); 786 } 787 788 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw, 789 unsigned long parent_rate) 790 { 791 return clk_divider_ops.recalc_rate(hw, parent_rate); 792 } 793 794 static void bcm2835_pll_divider_off(struct clk_hw *hw) 795 { 796 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 797 struct bcm2835_cprman *cprman = divider->cprman; 798 const struct bcm2835_pll_divider_data *data = divider->data; 799 800 spin_lock(&cprman->regs_lock); 801 cprman_write(cprman, data->cm_reg, 802 (cprman_read(cprman, data->cm_reg) & 803 ~data->load_mask) | data->hold_mask); 804 cprman_write(cprman, data->a2w_reg, 805 cprman_read(cprman, data->a2w_reg) | 806 A2W_PLL_CHANNEL_DISABLE); 807 spin_unlock(&cprman->regs_lock); 808 } 809 810 static int bcm2835_pll_divider_on(struct clk_hw *hw) 811 { 812 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 813 struct bcm2835_cprman *cprman = divider->cprman; 814 const struct bcm2835_pll_divider_data *data = divider->data; 815 816 spin_lock(&cprman->regs_lock); 817 cprman_write(cprman, data->a2w_reg, 818 cprman_read(cprman, data->a2w_reg) & 819 ~A2W_PLL_CHANNEL_DISABLE); 820 821 cprman_write(cprman, data->cm_reg, 822 cprman_read(cprman, data->cm_reg) & ~data->hold_mask); 823 spin_unlock(&cprman->regs_lock); 824 825 return 0; 826 } 827 828 static int bcm2835_pll_divider_set_rate(struct clk_hw *hw, 829 unsigned long rate, 830 unsigned long parent_rate) 831 { 832 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 833 struct bcm2835_cprman *cprman = divider->cprman; 834 const struct bcm2835_pll_divider_data *data = divider->data; 835 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS; 836 837 div = DIV_ROUND_UP_ULL(parent_rate, rate); 838 839 div = min(div, max_div); 840 if (div == max_div) 841 div = 0; 842 843 cprman_write(cprman, data->a2w_reg, div); 844 cm = cprman_read(cprman, data->cm_reg); 845 cprman_write(cprman, data->cm_reg, cm | data->load_mask); 846 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); 847 848 return 0; 849 } 850 851 static void bcm2835_pll_divider_debug_init(struct clk_hw *hw, 852 struct dentry *dentry) 853 { 854 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 855 struct bcm2835_cprman *cprman = divider->cprman; 856 const struct bcm2835_pll_divider_data *data = divider->data; 857 struct debugfs_reg32 *regs; 858 859 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL); 860 if (!regs) 861 return; 862 863 regs[0].name = "cm"; 864 regs[0].offset = data->cm_reg; 865 regs[1].name = "a2w"; 866 regs[1].offset = data->a2w_reg; 867 868 bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry); 869 } 870 871 static const struct clk_ops bcm2835_pll_divider_clk_ops = { 872 .is_prepared = bcm2835_pll_divider_is_on, 873 .prepare = bcm2835_pll_divider_on, 874 .unprepare = bcm2835_pll_divider_off, 875 .recalc_rate = bcm2835_pll_divider_get_rate, 876 .set_rate = bcm2835_pll_divider_set_rate, 877 .round_rate = bcm2835_pll_divider_round_rate, 878 .debug_init = bcm2835_pll_divider_debug_init, 879 }; 880 881 /* 882 * The CM dividers do fixed-point division, so we can't use the 883 * generic integer divider code like the PLL dividers do (and we can't 884 * fake it by having some fixed shifts preceding it in the clock tree, 885 * because we'd run out of bits in a 32-bit unsigned long). 886 */ 887 struct bcm2835_clock { 888 struct clk_hw hw; 889 struct bcm2835_cprman *cprman; 890 const struct bcm2835_clock_data *data; 891 }; 892 893 static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw) 894 { 895 return container_of(hw, struct bcm2835_clock, hw); 896 } 897 898 static int bcm2835_clock_is_on(struct clk_hw *hw) 899 { 900 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 901 struct bcm2835_cprman *cprman = clock->cprman; 902 const struct bcm2835_clock_data *data = clock->data; 903 904 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; 905 } 906 907 static u32 bcm2835_clock_choose_div(struct clk_hw *hw, 908 unsigned long rate, 909 unsigned long parent_rate, 910 bool round_up) 911 { 912 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 913 const struct bcm2835_clock_data *data = clock->data; 914 u32 unused_frac_mask = 915 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; 916 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; 917 u64 rem; 918 u32 div, mindiv, maxdiv; 919 920 rem = do_div(temp, rate); 921 div = temp; 922 923 /* Round up and mask off the unused bits */ 924 if (round_up && ((div & unused_frac_mask) != 0 || rem != 0)) 925 div += unused_frac_mask + 1; 926 div &= ~unused_frac_mask; 927 928 /* different clamping limits apply for a mash clock */ 929 if (data->is_mash_clock) { 930 /* clamp to min divider of 2 */ 931 mindiv = 2 << CM_DIV_FRAC_BITS; 932 /* clamp to the highest possible integer divider */ 933 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; 934 } else { 935 /* clamp to min divider of 1 */ 936 mindiv = 1 << CM_DIV_FRAC_BITS; 937 /* clamp to the highest possible fractional divider */ 938 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, 939 CM_DIV_FRAC_BITS - data->frac_bits); 940 } 941 942 /* apply the clamping limits */ 943 div = max_t(u32, div, mindiv); 944 div = min_t(u32, div, maxdiv); 945 946 return div; 947 } 948 949 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, 950 unsigned long parent_rate, 951 u32 div) 952 { 953 const struct bcm2835_clock_data *data = clock->data; 954 u64 temp; 955 956 if (data->int_bits == 0 && data->frac_bits == 0) 957 return parent_rate; 958 959 /* 960 * The divisor is a 12.12 fixed point field, but only some of 961 * the bits are populated in any given clock. 962 */ 963 div >>= CM_DIV_FRAC_BITS - data->frac_bits; 964 div &= (1 << (data->int_bits + data->frac_bits)) - 1; 965 966 if (div == 0) 967 return 0; 968 969 temp = (u64)parent_rate << data->frac_bits; 970 971 do_div(temp, div); 972 973 return temp; 974 } 975 976 static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, 977 unsigned long parent_rate) 978 { 979 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 980 struct bcm2835_cprman *cprman = clock->cprman; 981 const struct bcm2835_clock_data *data = clock->data; 982 u32 div; 983 984 if (data->int_bits == 0 && data->frac_bits == 0) 985 return parent_rate; 986 987 div = cprman_read(cprman, data->div_reg); 988 989 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); 990 } 991 992 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) 993 { 994 struct bcm2835_cprman *cprman = clock->cprman; 995 const struct bcm2835_clock_data *data = clock->data; 996 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 997 998 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { 999 if (ktime_after(ktime_get(), timeout)) { 1000 dev_err(cprman->dev, "%s: couldn't lock PLL\n", 1001 clk_hw_get_name(&clock->hw)); 1002 return; 1003 } 1004 cpu_relax(); 1005 } 1006 } 1007 1008 static void bcm2835_clock_off(struct clk_hw *hw) 1009 { 1010 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1011 struct bcm2835_cprman *cprman = clock->cprman; 1012 const struct bcm2835_clock_data *data = clock->data; 1013 1014 spin_lock(&cprman->regs_lock); 1015 cprman_write(cprman, data->ctl_reg, 1016 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); 1017 spin_unlock(&cprman->regs_lock); 1018 1019 /* BUSY will remain high until the divider completes its cycle. */ 1020 bcm2835_clock_wait_busy(clock); 1021 } 1022 1023 static int bcm2835_clock_on(struct clk_hw *hw) 1024 { 1025 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1026 struct bcm2835_cprman *cprman = clock->cprman; 1027 const struct bcm2835_clock_data *data = clock->data; 1028 1029 spin_lock(&cprman->regs_lock); 1030 cprman_write(cprman, data->ctl_reg, 1031 cprman_read(cprman, data->ctl_reg) | 1032 CM_ENABLE | 1033 CM_GATE); 1034 spin_unlock(&cprman->regs_lock); 1035 1036 /* Debug code to measure the clock once it's turned on to see 1037 * if it's ticking at the rate we expect. 1038 */ 1039 if (data->tcnt_mux && false) { 1040 dev_info(cprman->dev, 1041 "clk %s: rate %ld, measure %ld\n", 1042 data->name, 1043 clk_hw_get_rate(hw), 1044 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux)); 1045 } 1046 1047 return 0; 1048 } 1049 1050 static int bcm2835_clock_set_rate(struct clk_hw *hw, 1051 unsigned long rate, unsigned long parent_rate) 1052 { 1053 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1054 struct bcm2835_cprman *cprman = clock->cprman; 1055 const struct bcm2835_clock_data *data = clock->data; 1056 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); 1057 u32 ctl; 1058 1059 spin_lock(&cprman->regs_lock); 1060 1061 /* 1062 * Setting up frac support 1063 * 1064 * In principle it is recommended to stop/start the clock first, 1065 * but as we set CLK_SET_RATE_GATE during registration of the 1066 * clock this requirement should be take care of by the 1067 * clk-framework. 1068 */ 1069 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; 1070 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; 1071 cprman_write(cprman, data->ctl_reg, ctl); 1072 1073 cprman_write(cprman, data->div_reg, div); 1074 1075 spin_unlock(&cprman->regs_lock); 1076 1077 return 0; 1078 } 1079 1080 static bool 1081 bcm2835_clk_is_pllc(struct clk_hw *hw) 1082 { 1083 if (!hw) 1084 return false; 1085 1086 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0; 1087 } 1088 1089 static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw, 1090 int parent_idx, 1091 unsigned long rate, 1092 u32 *div, 1093 unsigned long *prate, 1094 unsigned long *avgrate) 1095 { 1096 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1097 struct bcm2835_cprman *cprman = clock->cprman; 1098 const struct bcm2835_clock_data *data = clock->data; 1099 unsigned long best_rate = 0; 1100 u32 curdiv, mindiv, maxdiv; 1101 struct clk_hw *parent; 1102 1103 parent = clk_hw_get_parent_by_index(hw, parent_idx); 1104 1105 if (!(BIT(parent_idx) & data->set_rate_parent)) { 1106 *prate = clk_hw_get_rate(parent); 1107 *div = bcm2835_clock_choose_div(hw, rate, *prate, true); 1108 1109 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div); 1110 1111 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) { 1112 unsigned long high, low; 1113 u32 int_div = *div & ~CM_DIV_FRAC_MASK; 1114 1115 high = bcm2835_clock_rate_from_divisor(clock, *prate, 1116 int_div); 1117 int_div += CM_DIV_FRAC_MASK + 1; 1118 low = bcm2835_clock_rate_from_divisor(clock, *prate, 1119 int_div); 1120 1121 /* 1122 * Return a value which is the maximum deviation 1123 * below the ideal rate, for use as a metric. 1124 */ 1125 return *avgrate - max(*avgrate - low, high - *avgrate); 1126 } 1127 return *avgrate; 1128 } 1129 1130 if (data->frac_bits) 1131 dev_warn(cprman->dev, 1132 "frac bits are not used when propagating rate change"); 1133 1134 /* clamp to min divider of 2 if we're dealing with a mash clock */ 1135 mindiv = data->is_mash_clock ? 2 : 1; 1136 maxdiv = BIT(data->int_bits) - 1; 1137 1138 /* TODO: Be smart, and only test a subset of the available divisors. */ 1139 for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) { 1140 unsigned long tmp_rate; 1141 1142 tmp_rate = clk_hw_round_rate(parent, rate * curdiv); 1143 tmp_rate /= curdiv; 1144 if (curdiv == mindiv || 1145 (tmp_rate > best_rate && tmp_rate <= rate)) 1146 best_rate = tmp_rate; 1147 1148 if (best_rate == rate) 1149 break; 1150 } 1151 1152 *div = curdiv << CM_DIV_FRAC_BITS; 1153 *prate = curdiv * best_rate; 1154 *avgrate = best_rate; 1155 1156 return best_rate; 1157 } 1158 1159 static int bcm2835_clock_determine_rate(struct clk_hw *hw, 1160 struct clk_rate_request *req) 1161 { 1162 struct clk_hw *parent, *best_parent = NULL; 1163 bool current_parent_is_pllc; 1164 unsigned long rate, best_rate = 0; 1165 unsigned long prate, best_prate = 0; 1166 unsigned long avgrate, best_avgrate = 0; 1167 size_t i; 1168 u32 div; 1169 1170 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw)); 1171 1172 /* 1173 * Select parent clock that results in the closest but lower rate 1174 */ 1175 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) { 1176 parent = clk_hw_get_parent_by_index(hw, i); 1177 if (!parent) 1178 continue; 1179 1180 /* 1181 * Don't choose a PLLC-derived clock as our parent 1182 * unless it had been manually set that way. PLLC's 1183 * frequency gets adjusted by the firmware due to 1184 * over-temp or under-voltage conditions, without 1185 * prior notification to our clock consumer. 1186 */ 1187 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc) 1188 continue; 1189 1190 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate, 1191 &div, &prate, 1192 &avgrate); 1193 if (rate > best_rate && rate <= req->rate) { 1194 best_parent = parent; 1195 best_prate = prate; 1196 best_rate = rate; 1197 best_avgrate = avgrate; 1198 } 1199 } 1200 1201 if (!best_parent) 1202 return -EINVAL; 1203 1204 req->best_parent_hw = best_parent; 1205 req->best_parent_rate = best_prate; 1206 1207 req->rate = best_avgrate; 1208 1209 return 0; 1210 } 1211 1212 static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index) 1213 { 1214 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1215 struct bcm2835_cprman *cprman = clock->cprman; 1216 const struct bcm2835_clock_data *data = clock->data; 1217 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK; 1218 1219 cprman_write(cprman, data->ctl_reg, src); 1220 return 0; 1221 } 1222 1223 static u8 bcm2835_clock_get_parent(struct clk_hw *hw) 1224 { 1225 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1226 struct bcm2835_cprman *cprman = clock->cprman; 1227 const struct bcm2835_clock_data *data = clock->data; 1228 u32 src = cprman_read(cprman, data->ctl_reg); 1229 1230 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; 1231 } 1232 1233 static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = { 1234 { 1235 .name = "ctl", 1236 .offset = 0, 1237 }, 1238 { 1239 .name = "div", 1240 .offset = 4, 1241 }, 1242 }; 1243 1244 static void bcm2835_clock_debug_init(struct clk_hw *hw, 1245 struct dentry *dentry) 1246 { 1247 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1248 struct bcm2835_cprman *cprman = clock->cprman; 1249 const struct bcm2835_clock_data *data = clock->data; 1250 1251 bcm2835_debugfs_regset(cprman, data->ctl_reg, 1252 bcm2835_debugfs_clock_reg32, 1253 ARRAY_SIZE(bcm2835_debugfs_clock_reg32), 1254 dentry); 1255 } 1256 1257 static const struct clk_ops bcm2835_clock_clk_ops = { 1258 .is_prepared = bcm2835_clock_is_on, 1259 .prepare = bcm2835_clock_on, 1260 .unprepare = bcm2835_clock_off, 1261 .recalc_rate = bcm2835_clock_get_rate, 1262 .set_rate = bcm2835_clock_set_rate, 1263 .determine_rate = bcm2835_clock_determine_rate, 1264 .set_parent = bcm2835_clock_set_parent, 1265 .get_parent = bcm2835_clock_get_parent, 1266 .debug_init = bcm2835_clock_debug_init, 1267 }; 1268 1269 static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) 1270 { 1271 return true; 1272 } 1273 1274 /* 1275 * The VPU clock can never be disabled (it doesn't have an ENABLE 1276 * bit), so it gets its own set of clock ops. 1277 */ 1278 static const struct clk_ops bcm2835_vpu_clock_clk_ops = { 1279 .is_prepared = bcm2835_vpu_clock_is_on, 1280 .recalc_rate = bcm2835_clock_get_rate, 1281 .set_rate = bcm2835_clock_set_rate, 1282 .determine_rate = bcm2835_clock_determine_rate, 1283 .set_parent = bcm2835_clock_set_parent, 1284 .get_parent = bcm2835_clock_get_parent, 1285 .debug_init = bcm2835_clock_debug_init, 1286 }; 1287 1288 static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, 1289 const struct bcm2835_pll_data *data) 1290 { 1291 struct bcm2835_pll *pll; 1292 struct clk_init_data init; 1293 int ret; 1294 1295 memset(&init, 0, sizeof(init)); 1296 1297 /* All of the PLLs derive from the external oscillator. */ 1298 init.parent_names = &cprman->real_parent_names[0]; 1299 init.num_parents = 1; 1300 init.name = data->name; 1301 init.ops = &bcm2835_pll_clk_ops; 1302 init.flags = CLK_IGNORE_UNUSED; 1303 1304 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1305 if (!pll) 1306 return NULL; 1307 1308 pll->cprman = cprman; 1309 pll->data = data; 1310 pll->hw.init = &init; 1311 1312 ret = devm_clk_hw_register(cprman->dev, &pll->hw); 1313 if (ret) 1314 return NULL; 1315 return &pll->hw; 1316 } 1317 1318 static struct clk_hw * 1319 bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, 1320 const struct bcm2835_pll_divider_data *data) 1321 { 1322 struct bcm2835_pll_divider *divider; 1323 struct clk_init_data init; 1324 const char *divider_name; 1325 int ret; 1326 1327 if (data->fixed_divider != 1) { 1328 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, 1329 "%s_prediv", data->name); 1330 if (!divider_name) 1331 return NULL; 1332 } else { 1333 divider_name = data->name; 1334 } 1335 1336 memset(&init, 0, sizeof(init)); 1337 1338 init.parent_names = &data->source_pll; 1339 init.num_parents = 1; 1340 init.name = divider_name; 1341 init.ops = &bcm2835_pll_divider_clk_ops; 1342 init.flags = data->flags | CLK_IGNORE_UNUSED; 1343 1344 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); 1345 if (!divider) 1346 return NULL; 1347 1348 divider->div.reg = cprman->regs + data->a2w_reg; 1349 divider->div.shift = A2W_PLL_DIV_SHIFT; 1350 divider->div.width = A2W_PLL_DIV_BITS; 1351 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; 1352 divider->div.lock = &cprman->regs_lock; 1353 divider->div.hw.init = &init; 1354 divider->div.table = NULL; 1355 1356 divider->cprman = cprman; 1357 divider->data = data; 1358 1359 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw); 1360 if (ret) 1361 return ERR_PTR(ret); 1362 1363 /* 1364 * PLLH's channels have a fixed divide by 10 afterwards, which 1365 * is what our consumers are actually using. 1366 */ 1367 if (data->fixed_divider != 1) { 1368 return clk_hw_register_fixed_factor(cprman->dev, data->name, 1369 divider_name, 1370 CLK_SET_RATE_PARENT, 1371 1, 1372 data->fixed_divider); 1373 } 1374 1375 return ÷r->div.hw; 1376 } 1377 1378 static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, 1379 const struct bcm2835_clock_data *data) 1380 { 1381 struct bcm2835_clock *clock; 1382 struct clk_init_data init; 1383 const char *parents[1 << CM_SRC_BITS]; 1384 size_t i; 1385 int ret; 1386 1387 /* 1388 * Replace our strings referencing parent clocks with the 1389 * actual clock-output-name of the parent. 1390 */ 1391 for (i = 0; i < data->num_mux_parents; i++) { 1392 parents[i] = data->parents[i]; 1393 1394 ret = match_string(cprman_parent_names, 1395 ARRAY_SIZE(cprman_parent_names), 1396 parents[i]); 1397 if (ret >= 0) 1398 parents[i] = cprman->real_parent_names[ret]; 1399 } 1400 1401 memset(&init, 0, sizeof(init)); 1402 init.parent_names = parents; 1403 init.num_parents = data->num_mux_parents; 1404 init.name = data->name; 1405 init.flags = data->flags | CLK_IGNORE_UNUSED; 1406 1407 /* 1408 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate 1409 * rate changes on at least of the parents. 1410 */ 1411 if (data->set_rate_parent) 1412 init.flags |= CLK_SET_RATE_PARENT; 1413 1414 if (data->is_vpu_clock) { 1415 init.ops = &bcm2835_vpu_clock_clk_ops; 1416 } else { 1417 init.ops = &bcm2835_clock_clk_ops; 1418 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; 1419 1420 /* If the clock wasn't actually enabled at boot, it's not 1421 * critical. 1422 */ 1423 if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE)) 1424 init.flags &= ~CLK_IS_CRITICAL; 1425 } 1426 1427 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); 1428 if (!clock) 1429 return NULL; 1430 1431 clock->cprman = cprman; 1432 clock->data = data; 1433 clock->hw.init = &init; 1434 1435 ret = devm_clk_hw_register(cprman->dev, &clock->hw); 1436 if (ret) 1437 return ERR_PTR(ret); 1438 return &clock->hw; 1439 } 1440 1441 static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman, 1442 const struct bcm2835_gate_data *data) 1443 { 1444 return clk_register_gate(cprman->dev, data->name, data->parent, 1445 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 1446 cprman->regs + data->ctl_reg, 1447 CM_GATE_BIT, 0, &cprman->regs_lock); 1448 } 1449 1450 typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman, 1451 const void *data); 1452 struct bcm2835_clk_desc { 1453 bcm2835_clk_register clk_register; 1454 const void *data; 1455 }; 1456 1457 /* assignment helper macros for different clock types */ 1458 #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \ 1459 .data = __VA_ARGS__ } 1460 #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \ 1461 &(struct bcm2835_pll_data) \ 1462 {__VA_ARGS__}) 1463 #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \ 1464 &(struct bcm2835_pll_divider_data) \ 1465 {__VA_ARGS__}) 1466 #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \ 1467 &(struct bcm2835_clock_data) \ 1468 {__VA_ARGS__}) 1469 #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \ 1470 &(struct bcm2835_gate_data) \ 1471 {__VA_ARGS__}) 1472 1473 /* parent mux arrays plus helper macros */ 1474 1475 /* main oscillator parent mux */ 1476 static const char *const bcm2835_clock_osc_parents[] = { 1477 "gnd", 1478 "xosc", 1479 "testdebug0", 1480 "testdebug1" 1481 }; 1482 1483 #define REGISTER_OSC_CLK(...) REGISTER_CLK( \ 1484 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \ 1485 .parents = bcm2835_clock_osc_parents, \ 1486 __VA_ARGS__) 1487 1488 /* main peripherial parent mux */ 1489 static const char *const bcm2835_clock_per_parents[] = { 1490 "gnd", 1491 "xosc", 1492 "testdebug0", 1493 "testdebug1", 1494 "plla_per", 1495 "pllc_per", 1496 "plld_per", 1497 "pllh_aux", 1498 }; 1499 1500 #define REGISTER_PER_CLK(...) REGISTER_CLK( \ 1501 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \ 1502 .parents = bcm2835_clock_per_parents, \ 1503 __VA_ARGS__) 1504 1505 /* 1506 * Restrict clock sources for the PCM peripheral to the oscillator and 1507 * PLLD_PER because other source may have varying rates or be switched 1508 * off. 1509 * 1510 * Prevent other sources from being selected by replacing their names in 1511 * the list of potential parents with dummy entries (entry index is 1512 * significant). 1513 */ 1514 static const char *const bcm2835_pcm_per_parents[] = { 1515 "-", 1516 "xosc", 1517 "-", 1518 "-", 1519 "-", 1520 "-", 1521 "plld_per", 1522 "-", 1523 }; 1524 1525 #define REGISTER_PCM_CLK(...) REGISTER_CLK( \ 1526 .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \ 1527 .parents = bcm2835_pcm_per_parents, \ 1528 __VA_ARGS__) 1529 1530 /* main vpu parent mux */ 1531 static const char *const bcm2835_clock_vpu_parents[] = { 1532 "gnd", 1533 "xosc", 1534 "testdebug0", 1535 "testdebug1", 1536 "plla_core", 1537 "pllc_core0", 1538 "plld_core", 1539 "pllh_aux", 1540 "pllc_core1", 1541 "pllc_core2", 1542 }; 1543 1544 #define REGISTER_VPU_CLK(...) REGISTER_CLK( \ 1545 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \ 1546 .parents = bcm2835_clock_vpu_parents, \ 1547 __VA_ARGS__) 1548 1549 /* 1550 * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI 1551 * analog PHY. The _inv variants are generated internally to cprman, 1552 * but we don't use them so they aren't hooked up. 1553 */ 1554 static const char *const bcm2835_clock_dsi0_parents[] = { 1555 "gnd", 1556 "xosc", 1557 "testdebug0", 1558 "testdebug1", 1559 "dsi0_ddr", 1560 "dsi0_ddr_inv", 1561 "dsi0_ddr2", 1562 "dsi0_ddr2_inv", 1563 "dsi0_byte", 1564 "dsi0_byte_inv", 1565 }; 1566 1567 static const char *const bcm2835_clock_dsi1_parents[] = { 1568 "gnd", 1569 "xosc", 1570 "testdebug0", 1571 "testdebug1", 1572 "dsi1_ddr", 1573 "dsi1_ddr_inv", 1574 "dsi1_ddr2", 1575 "dsi1_ddr2_inv", 1576 "dsi1_byte", 1577 "dsi1_byte_inv", 1578 }; 1579 1580 #define REGISTER_DSI0_CLK(...) REGISTER_CLK( \ 1581 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \ 1582 .parents = bcm2835_clock_dsi0_parents, \ 1583 __VA_ARGS__) 1584 1585 #define REGISTER_DSI1_CLK(...) REGISTER_CLK( \ 1586 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \ 1587 .parents = bcm2835_clock_dsi1_parents, \ 1588 __VA_ARGS__) 1589 1590 /* 1591 * the real definition of all the pll, pll_dividers and clocks 1592 * these make use of the above REGISTER_* macros 1593 */ 1594 static const struct bcm2835_clk_desc clk_desc_array[] = { 1595 /* the PLL + PLL dividers */ 1596 1597 /* 1598 * PLLA is the auxiliary PLL, used to drive the CCP2 1599 * (Compact Camera Port 2) transmitter clock. 1600 * 1601 * It is in the PX LDO power domain, which is on when the 1602 * AUDIO domain is on. 1603 */ 1604 [BCM2835_PLLA] = REGISTER_PLL( 1605 .name = "plla", 1606 .cm_ctrl_reg = CM_PLLA, 1607 .a2w_ctrl_reg = A2W_PLLA_CTRL, 1608 .frac_reg = A2W_PLLA_FRAC, 1609 .ana_reg_base = A2W_PLLA_ANA0, 1610 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE, 1611 .lock_mask = CM_LOCK_FLOCKA, 1612 1613 .ana = &bcm2835_ana_default, 1614 1615 .min_rate = 600000000u, 1616 .max_rate = 2400000000u, 1617 .max_fb_rate = BCM2835_MAX_FB_RATE), 1618 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV( 1619 .name = "plla_core", 1620 .source_pll = "plla", 1621 .cm_reg = CM_PLLA, 1622 .a2w_reg = A2W_PLLA_CORE, 1623 .load_mask = CM_PLLA_LOADCORE, 1624 .hold_mask = CM_PLLA_HOLDCORE, 1625 .fixed_divider = 1, 1626 .flags = CLK_SET_RATE_PARENT), 1627 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( 1628 .name = "plla_per", 1629 .source_pll = "plla", 1630 .cm_reg = CM_PLLA, 1631 .a2w_reg = A2W_PLLA_PER, 1632 .load_mask = CM_PLLA_LOADPER, 1633 .hold_mask = CM_PLLA_HOLDPER, 1634 .fixed_divider = 1, 1635 .flags = CLK_SET_RATE_PARENT), 1636 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( 1637 .name = "plla_dsi0", 1638 .source_pll = "plla", 1639 .cm_reg = CM_PLLA, 1640 .a2w_reg = A2W_PLLA_DSI0, 1641 .load_mask = CM_PLLA_LOADDSI0, 1642 .hold_mask = CM_PLLA_HOLDDSI0, 1643 .fixed_divider = 1), 1644 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( 1645 .name = "plla_ccp2", 1646 .source_pll = "plla", 1647 .cm_reg = CM_PLLA, 1648 .a2w_reg = A2W_PLLA_CCP2, 1649 .load_mask = CM_PLLA_LOADCCP2, 1650 .hold_mask = CM_PLLA_HOLDCCP2, 1651 .fixed_divider = 1, 1652 .flags = CLK_SET_RATE_PARENT), 1653 1654 /* PLLB is used for the ARM's clock. */ 1655 [BCM2835_PLLB] = REGISTER_PLL( 1656 .name = "pllb", 1657 .cm_ctrl_reg = CM_PLLB, 1658 .a2w_ctrl_reg = A2W_PLLB_CTRL, 1659 .frac_reg = A2W_PLLB_FRAC, 1660 .ana_reg_base = A2W_PLLB_ANA0, 1661 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE, 1662 .lock_mask = CM_LOCK_FLOCKB, 1663 1664 .ana = &bcm2835_ana_default, 1665 1666 .min_rate = 600000000u, 1667 .max_rate = 3000000000u, 1668 .max_fb_rate = BCM2835_MAX_FB_RATE), 1669 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV( 1670 .name = "pllb_arm", 1671 .source_pll = "pllb", 1672 .cm_reg = CM_PLLB, 1673 .a2w_reg = A2W_PLLB_ARM, 1674 .load_mask = CM_PLLB_LOADARM, 1675 .hold_mask = CM_PLLB_HOLDARM, 1676 .fixed_divider = 1, 1677 .flags = CLK_SET_RATE_PARENT), 1678 1679 /* 1680 * PLLC is the core PLL, used to drive the core VPU clock. 1681 * 1682 * It is in the PX LDO power domain, which is on when the 1683 * AUDIO domain is on. 1684 */ 1685 [BCM2835_PLLC] = REGISTER_PLL( 1686 .name = "pllc", 1687 .cm_ctrl_reg = CM_PLLC, 1688 .a2w_ctrl_reg = A2W_PLLC_CTRL, 1689 .frac_reg = A2W_PLLC_FRAC, 1690 .ana_reg_base = A2W_PLLC_ANA0, 1691 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, 1692 .lock_mask = CM_LOCK_FLOCKC, 1693 1694 .ana = &bcm2835_ana_default, 1695 1696 .min_rate = 600000000u, 1697 .max_rate = 3000000000u, 1698 .max_fb_rate = BCM2835_MAX_FB_RATE), 1699 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV( 1700 .name = "pllc_core0", 1701 .source_pll = "pllc", 1702 .cm_reg = CM_PLLC, 1703 .a2w_reg = A2W_PLLC_CORE0, 1704 .load_mask = CM_PLLC_LOADCORE0, 1705 .hold_mask = CM_PLLC_HOLDCORE0, 1706 .fixed_divider = 1, 1707 .flags = CLK_SET_RATE_PARENT), 1708 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( 1709 .name = "pllc_core1", 1710 .source_pll = "pllc", 1711 .cm_reg = CM_PLLC, 1712 .a2w_reg = A2W_PLLC_CORE1, 1713 .load_mask = CM_PLLC_LOADCORE1, 1714 .hold_mask = CM_PLLC_HOLDCORE1, 1715 .fixed_divider = 1, 1716 .flags = CLK_SET_RATE_PARENT), 1717 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( 1718 .name = "pllc_core2", 1719 .source_pll = "pllc", 1720 .cm_reg = CM_PLLC, 1721 .a2w_reg = A2W_PLLC_CORE2, 1722 .load_mask = CM_PLLC_LOADCORE2, 1723 .hold_mask = CM_PLLC_HOLDCORE2, 1724 .fixed_divider = 1, 1725 .flags = CLK_SET_RATE_PARENT), 1726 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( 1727 .name = "pllc_per", 1728 .source_pll = "pllc", 1729 .cm_reg = CM_PLLC, 1730 .a2w_reg = A2W_PLLC_PER, 1731 .load_mask = CM_PLLC_LOADPER, 1732 .hold_mask = CM_PLLC_HOLDPER, 1733 .fixed_divider = 1, 1734 .flags = CLK_SET_RATE_PARENT), 1735 1736 /* 1737 * PLLD is the display PLL, used to drive DSI display panels. 1738 * 1739 * It is in the PX LDO power domain, which is on when the 1740 * AUDIO domain is on. 1741 */ 1742 [BCM2835_PLLD] = REGISTER_PLL( 1743 .name = "plld", 1744 .cm_ctrl_reg = CM_PLLD, 1745 .a2w_ctrl_reg = A2W_PLLD_CTRL, 1746 .frac_reg = A2W_PLLD_FRAC, 1747 .ana_reg_base = A2W_PLLD_ANA0, 1748 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE, 1749 .lock_mask = CM_LOCK_FLOCKD, 1750 1751 .ana = &bcm2835_ana_default, 1752 1753 .min_rate = 600000000u, 1754 .max_rate = 2400000000u, 1755 .max_fb_rate = BCM2835_MAX_FB_RATE), 1756 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV( 1757 .name = "plld_core", 1758 .source_pll = "plld", 1759 .cm_reg = CM_PLLD, 1760 .a2w_reg = A2W_PLLD_CORE, 1761 .load_mask = CM_PLLD_LOADCORE, 1762 .hold_mask = CM_PLLD_HOLDCORE, 1763 .fixed_divider = 1, 1764 .flags = CLK_SET_RATE_PARENT), 1765 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( 1766 .name = "plld_per", 1767 .source_pll = "plld", 1768 .cm_reg = CM_PLLD, 1769 .a2w_reg = A2W_PLLD_PER, 1770 .load_mask = CM_PLLD_LOADPER, 1771 .hold_mask = CM_PLLD_HOLDPER, 1772 .fixed_divider = 1, 1773 .flags = CLK_SET_RATE_PARENT), 1774 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( 1775 .name = "plld_dsi0", 1776 .source_pll = "plld", 1777 .cm_reg = CM_PLLD, 1778 .a2w_reg = A2W_PLLD_DSI0, 1779 .load_mask = CM_PLLD_LOADDSI0, 1780 .hold_mask = CM_PLLD_HOLDDSI0, 1781 .fixed_divider = 1), 1782 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( 1783 .name = "plld_dsi1", 1784 .source_pll = "plld", 1785 .cm_reg = CM_PLLD, 1786 .a2w_reg = A2W_PLLD_DSI1, 1787 .load_mask = CM_PLLD_LOADDSI1, 1788 .hold_mask = CM_PLLD_HOLDDSI1, 1789 .fixed_divider = 1), 1790 1791 /* 1792 * PLLH is used to supply the pixel clock or the AUX clock for the 1793 * TV encoder. 1794 * 1795 * It is in the HDMI power domain. 1796 */ 1797 [BCM2835_PLLH] = REGISTER_PLL( 1798 "pllh", 1799 .cm_ctrl_reg = CM_PLLH, 1800 .a2w_ctrl_reg = A2W_PLLH_CTRL, 1801 .frac_reg = A2W_PLLH_FRAC, 1802 .ana_reg_base = A2W_PLLH_ANA0, 1803 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, 1804 .lock_mask = CM_LOCK_FLOCKH, 1805 1806 .ana = &bcm2835_ana_pllh, 1807 1808 .min_rate = 600000000u, 1809 .max_rate = 3000000000u, 1810 .max_fb_rate = BCM2835_MAX_FB_RATE), 1811 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV( 1812 .name = "pllh_rcal", 1813 .source_pll = "pllh", 1814 .cm_reg = CM_PLLH, 1815 .a2w_reg = A2W_PLLH_RCAL, 1816 .load_mask = CM_PLLH_LOADRCAL, 1817 .hold_mask = 0, 1818 .fixed_divider = 10, 1819 .flags = CLK_SET_RATE_PARENT), 1820 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( 1821 .name = "pllh_aux", 1822 .source_pll = "pllh", 1823 .cm_reg = CM_PLLH, 1824 .a2w_reg = A2W_PLLH_AUX, 1825 .load_mask = CM_PLLH_LOADAUX, 1826 .hold_mask = 0, 1827 .fixed_divider = 1, 1828 .flags = CLK_SET_RATE_PARENT), 1829 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( 1830 .name = "pllh_pix", 1831 .source_pll = "pllh", 1832 .cm_reg = CM_PLLH, 1833 .a2w_reg = A2W_PLLH_PIX, 1834 .load_mask = CM_PLLH_LOADPIX, 1835 .hold_mask = 0, 1836 .fixed_divider = 10, 1837 .flags = CLK_SET_RATE_PARENT), 1838 1839 /* the clocks */ 1840 1841 /* clocks with oscillator parent mux */ 1842 1843 /* One Time Programmable Memory clock. Maximum 10Mhz. */ 1844 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK( 1845 .name = "otp", 1846 .ctl_reg = CM_OTPCTL, 1847 .div_reg = CM_OTPDIV, 1848 .int_bits = 4, 1849 .frac_bits = 0, 1850 .tcnt_mux = 6), 1851 /* 1852 * Used for a 1Mhz clock for the system clocksource, and also used 1853 * bythe watchdog timer and the camera pulse generator. 1854 */ 1855 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK( 1856 .name = "timer", 1857 .ctl_reg = CM_TIMERCTL, 1858 .div_reg = CM_TIMERDIV, 1859 .int_bits = 6, 1860 .frac_bits = 12), 1861 /* 1862 * Clock for the temperature sensor. 1863 * Generally run at 2Mhz, max 5Mhz. 1864 */ 1865 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK( 1866 .name = "tsens", 1867 .ctl_reg = CM_TSENSCTL, 1868 .div_reg = CM_TSENSDIV, 1869 .int_bits = 5, 1870 .frac_bits = 0), 1871 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK( 1872 .name = "tec", 1873 .ctl_reg = CM_TECCTL, 1874 .div_reg = CM_TECDIV, 1875 .int_bits = 6, 1876 .frac_bits = 0), 1877 1878 /* clocks with vpu parent mux */ 1879 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( 1880 .name = "h264", 1881 .ctl_reg = CM_H264CTL, 1882 .div_reg = CM_H264DIV, 1883 .int_bits = 4, 1884 .frac_bits = 8, 1885 .tcnt_mux = 1), 1886 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK( 1887 .name = "isp", 1888 .ctl_reg = CM_ISPCTL, 1889 .div_reg = CM_ISPDIV, 1890 .int_bits = 4, 1891 .frac_bits = 8, 1892 .tcnt_mux = 2), 1893 1894 /* 1895 * Secondary SDRAM clock. Used for low-voltage modes when the PLL 1896 * in the SDRAM controller can't be used. 1897 */ 1898 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK( 1899 .name = "sdram", 1900 .ctl_reg = CM_SDCCTL, 1901 .div_reg = CM_SDCDIV, 1902 .int_bits = 6, 1903 .frac_bits = 0, 1904 .tcnt_mux = 3), 1905 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( 1906 .name = "v3d", 1907 .ctl_reg = CM_V3DCTL, 1908 .div_reg = CM_V3DDIV, 1909 .int_bits = 4, 1910 .frac_bits = 8, 1911 .tcnt_mux = 4), 1912 /* 1913 * VPU clock. This doesn't have an enable bit, since it drives 1914 * the bus for everything else, and is special so it doesn't need 1915 * to be gated for rate changes. It is also known as "clk_audio" 1916 * in various hardware documentation. 1917 */ 1918 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK( 1919 .name = "vpu", 1920 .ctl_reg = CM_VPUCTL, 1921 .div_reg = CM_VPUDIV, 1922 .int_bits = 12, 1923 .frac_bits = 8, 1924 .flags = CLK_IS_CRITICAL, 1925 .is_vpu_clock = true, 1926 .tcnt_mux = 5), 1927 1928 /* clocks with per parent mux */ 1929 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK( 1930 .name = "aveo", 1931 .ctl_reg = CM_AVEOCTL, 1932 .div_reg = CM_AVEODIV, 1933 .int_bits = 4, 1934 .frac_bits = 0, 1935 .tcnt_mux = 38), 1936 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK( 1937 .name = "cam0", 1938 .ctl_reg = CM_CAM0CTL, 1939 .div_reg = CM_CAM0DIV, 1940 .int_bits = 4, 1941 .frac_bits = 8, 1942 .tcnt_mux = 14), 1943 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK( 1944 .name = "cam1", 1945 .ctl_reg = CM_CAM1CTL, 1946 .div_reg = CM_CAM1DIV, 1947 .int_bits = 4, 1948 .frac_bits = 8, 1949 .tcnt_mux = 15), 1950 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK( 1951 .name = "dft", 1952 .ctl_reg = CM_DFTCTL, 1953 .div_reg = CM_DFTDIV, 1954 .int_bits = 5, 1955 .frac_bits = 0), 1956 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK( 1957 .name = "dpi", 1958 .ctl_reg = CM_DPICTL, 1959 .div_reg = CM_DPIDIV, 1960 .int_bits = 4, 1961 .frac_bits = 8, 1962 .tcnt_mux = 17), 1963 1964 /* Arasan EMMC clock */ 1965 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( 1966 .name = "emmc", 1967 .ctl_reg = CM_EMMCCTL, 1968 .div_reg = CM_EMMCDIV, 1969 .int_bits = 4, 1970 .frac_bits = 8, 1971 .tcnt_mux = 39), 1972 1973 /* General purpose (GPIO) clocks */ 1974 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( 1975 .name = "gp0", 1976 .ctl_reg = CM_GP0CTL, 1977 .div_reg = CM_GP0DIV, 1978 .int_bits = 12, 1979 .frac_bits = 12, 1980 .is_mash_clock = true, 1981 .tcnt_mux = 20), 1982 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK( 1983 .name = "gp1", 1984 .ctl_reg = CM_GP1CTL, 1985 .div_reg = CM_GP1DIV, 1986 .int_bits = 12, 1987 .frac_bits = 12, 1988 .flags = CLK_IS_CRITICAL, 1989 .is_mash_clock = true, 1990 .tcnt_mux = 21), 1991 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK( 1992 .name = "gp2", 1993 .ctl_reg = CM_GP2CTL, 1994 .div_reg = CM_GP2DIV, 1995 .int_bits = 12, 1996 .frac_bits = 12, 1997 .flags = CLK_IS_CRITICAL), 1998 1999 /* HDMI state machine */ 2000 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( 2001 .name = "hsm", 2002 .ctl_reg = CM_HSMCTL, 2003 .div_reg = CM_HSMDIV, 2004 .int_bits = 4, 2005 .frac_bits = 8, 2006 .tcnt_mux = 22), 2007 [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK( 2008 .name = "pcm", 2009 .ctl_reg = CM_PCMCTL, 2010 .div_reg = CM_PCMDIV, 2011 .int_bits = 12, 2012 .frac_bits = 12, 2013 .is_mash_clock = true, 2014 .low_jitter = true, 2015 .tcnt_mux = 23), 2016 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK( 2017 .name = "pwm", 2018 .ctl_reg = CM_PWMCTL, 2019 .div_reg = CM_PWMDIV, 2020 .int_bits = 12, 2021 .frac_bits = 12, 2022 .is_mash_clock = true, 2023 .tcnt_mux = 24), 2024 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK( 2025 .name = "slim", 2026 .ctl_reg = CM_SLIMCTL, 2027 .div_reg = CM_SLIMDIV, 2028 .int_bits = 12, 2029 .frac_bits = 12, 2030 .is_mash_clock = true, 2031 .tcnt_mux = 25), 2032 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK( 2033 .name = "smi", 2034 .ctl_reg = CM_SMICTL, 2035 .div_reg = CM_SMIDIV, 2036 .int_bits = 4, 2037 .frac_bits = 8, 2038 .tcnt_mux = 27), 2039 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK( 2040 .name = "uart", 2041 .ctl_reg = CM_UARTCTL, 2042 .div_reg = CM_UARTDIV, 2043 .int_bits = 10, 2044 .frac_bits = 12, 2045 .tcnt_mux = 28), 2046 2047 /* TV encoder clock. Only operating frequency is 108Mhz. */ 2048 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( 2049 .name = "vec", 2050 .ctl_reg = CM_VECCTL, 2051 .div_reg = CM_VECDIV, 2052 .int_bits = 4, 2053 .frac_bits = 0, 2054 /* 2055 * Allow rate change propagation only on PLLH_AUX which is 2056 * assigned index 7 in the parent array. 2057 */ 2058 .set_rate_parent = BIT(7), 2059 .tcnt_mux = 29), 2060 2061 /* dsi clocks */ 2062 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( 2063 .name = "dsi0e", 2064 .ctl_reg = CM_DSI0ECTL, 2065 .div_reg = CM_DSI0EDIV, 2066 .int_bits = 4, 2067 .frac_bits = 8, 2068 .tcnt_mux = 18), 2069 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK( 2070 .name = "dsi1e", 2071 .ctl_reg = CM_DSI1ECTL, 2072 .div_reg = CM_DSI1EDIV, 2073 .int_bits = 4, 2074 .frac_bits = 8, 2075 .tcnt_mux = 19), 2076 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK( 2077 .name = "dsi0p", 2078 .ctl_reg = CM_DSI0PCTL, 2079 .div_reg = CM_DSI0PDIV, 2080 .int_bits = 0, 2081 .frac_bits = 0, 2082 .tcnt_mux = 12), 2083 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK( 2084 .name = "dsi1p", 2085 .ctl_reg = CM_DSI1PCTL, 2086 .div_reg = CM_DSI1PDIV, 2087 .int_bits = 0, 2088 .frac_bits = 0, 2089 .tcnt_mux = 13), 2090 2091 /* the gates */ 2092 2093 /* 2094 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if 2095 * you have the debug bit set in the power manager, which we 2096 * don't bother exposing) are individual gates off of the 2097 * non-stop vpu clock. 2098 */ 2099 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE( 2100 .name = "peri_image", 2101 .parent = "vpu", 2102 .ctl_reg = CM_PERIICTL), 2103 }; 2104 2105 /* 2106 * Permanently take a reference on the parent of the SDRAM clock. 2107 * 2108 * While the SDRAM is being driven by its dedicated PLL most of the 2109 * time, there is a little loop running in the firmware that 2110 * periodically switches the SDRAM to using our CM clock to do PVT 2111 * recalibration, with the assumption that the previously configured 2112 * SDRAM parent is still enabled and running. 2113 */ 2114 static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) 2115 { 2116 struct clk *parent = clk_get_parent(sdc); 2117 2118 if (IS_ERR(parent)) 2119 return PTR_ERR(parent); 2120 2121 return clk_prepare_enable(parent); 2122 } 2123 2124 static int bcm2835_clk_probe(struct platform_device *pdev) 2125 { 2126 struct device *dev = &pdev->dev; 2127 struct clk_hw **hws; 2128 struct bcm2835_cprman *cprman; 2129 struct resource *res; 2130 const struct bcm2835_clk_desc *desc; 2131 const size_t asize = ARRAY_SIZE(clk_desc_array); 2132 size_t i; 2133 int ret; 2134 2135 cprman = devm_kzalloc(dev, 2136 struct_size(cprman, onecell.hws, asize), 2137 GFP_KERNEL); 2138 if (!cprman) 2139 return -ENOMEM; 2140 2141 spin_lock_init(&cprman->regs_lock); 2142 cprman->dev = dev; 2143 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2144 cprman->regs = devm_ioremap_resource(dev, res); 2145 if (IS_ERR(cprman->regs)) 2146 return PTR_ERR(cprman->regs); 2147 2148 memcpy(cprman->real_parent_names, cprman_parent_names, 2149 sizeof(cprman_parent_names)); 2150 of_clk_parent_fill(dev->of_node, cprman->real_parent_names, 2151 ARRAY_SIZE(cprman_parent_names)); 2152 2153 /* 2154 * Make sure the external oscillator has been registered. 2155 * 2156 * The other (DSI) clocks are not present on older device 2157 * trees, which we still need to support for backwards 2158 * compatibility. 2159 */ 2160 if (!cprman->real_parent_names[0]) 2161 return -ENODEV; 2162 2163 platform_set_drvdata(pdev, cprman); 2164 2165 cprman->onecell.num = asize; 2166 hws = cprman->onecell.hws; 2167 2168 for (i = 0; i < asize; i++) { 2169 desc = &clk_desc_array[i]; 2170 if (desc->clk_register && desc->data) 2171 hws[i] = desc->clk_register(cprman, desc->data); 2172 } 2173 2174 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk); 2175 if (ret) 2176 return ret; 2177 2178 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 2179 &cprman->onecell); 2180 } 2181 2182 static const struct of_device_id bcm2835_clk_of_match[] = { 2183 { .compatible = "brcm,bcm2835-cprman", }, 2184 {} 2185 }; 2186 MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); 2187 2188 static struct platform_driver bcm2835_clk_driver = { 2189 .driver = { 2190 .name = "bcm2835-clk", 2191 .of_match_table = bcm2835_clk_of_match, 2192 }, 2193 .probe = bcm2835_clk_probe, 2194 }; 2195 2196 builtin_platform_driver(bcm2835_clk_driver); 2197 2198 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 2199 MODULE_DESCRIPTION("BCM2835 clock driver"); 2200 MODULE_LICENSE("GPL"); 2201