1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2010,2015 Broadcom 4 * Copyright (C) 2012 Stephen Warren 5 */ 6 7 /** 8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain) 9 * 10 * The clock tree on the 2835 has several levels. There's a root 11 * oscillator running at 19.2Mhz. After the oscillator there are 5 12 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays", 13 * and "HDMI displays". Those 5 PLLs each can divide their output to 14 * produce up to 4 channels. Finally, there is the level of clocks to 15 * be consumed by other hardware components (like "H264" or "HDMI 16 * state machine"), which divide off of some subset of the PLL 17 * channels. 18 * 19 * All of the clocks in the tree are exposed in the DT, because the DT 20 * may want to make assignments of the final layer of clocks to the 21 * PLL channels, and some components of the hardware will actually 22 * skip layers of the tree (for example, the pixel clock comes 23 * directly from the PLLH PIX channel without using a CM_*CTL clock 24 * generator). 25 */ 26 27 #include <linux/clk-provider.h> 28 #include <linux/clkdev.h> 29 #include <linux/clk.h> 30 #include <linux/debugfs.h> 31 #include <linux/delay.h> 32 #include <linux/io.h> 33 #include <linux/module.h> 34 #include <linux/of_device.h> 35 #include <linux/platform_device.h> 36 #include <linux/slab.h> 37 #include <dt-bindings/clock/bcm2835.h> 38 39 #define CM_PASSWORD 0x5a000000 40 41 #define CM_GNRICCTL 0x000 42 #define CM_GNRICDIV 0x004 43 # define CM_DIV_FRAC_BITS 12 44 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0) 45 46 #define CM_VPUCTL 0x008 47 #define CM_VPUDIV 0x00c 48 #define CM_SYSCTL 0x010 49 #define CM_SYSDIV 0x014 50 #define CM_PERIACTL 0x018 51 #define CM_PERIADIV 0x01c 52 #define CM_PERIICTL 0x020 53 #define CM_PERIIDIV 0x024 54 #define CM_H264CTL 0x028 55 #define CM_H264DIV 0x02c 56 #define CM_ISPCTL 0x030 57 #define CM_ISPDIV 0x034 58 #define CM_V3DCTL 0x038 59 #define CM_V3DDIV 0x03c 60 #define CM_CAM0CTL 0x040 61 #define CM_CAM0DIV 0x044 62 #define CM_CAM1CTL 0x048 63 #define CM_CAM1DIV 0x04c 64 #define CM_CCP2CTL 0x050 65 #define CM_CCP2DIV 0x054 66 #define CM_DSI0ECTL 0x058 67 #define CM_DSI0EDIV 0x05c 68 #define CM_DSI0PCTL 0x060 69 #define CM_DSI0PDIV 0x064 70 #define CM_DPICTL 0x068 71 #define CM_DPIDIV 0x06c 72 #define CM_GP0CTL 0x070 73 #define CM_GP0DIV 0x074 74 #define CM_GP1CTL 0x078 75 #define CM_GP1DIV 0x07c 76 #define CM_GP2CTL 0x080 77 #define CM_GP2DIV 0x084 78 #define CM_HSMCTL 0x088 79 #define CM_HSMDIV 0x08c 80 #define CM_OTPCTL 0x090 81 #define CM_OTPDIV 0x094 82 #define CM_PCMCTL 0x098 83 #define CM_PCMDIV 0x09c 84 #define CM_PWMCTL 0x0a0 85 #define CM_PWMDIV 0x0a4 86 #define CM_SLIMCTL 0x0a8 87 #define CM_SLIMDIV 0x0ac 88 #define CM_SMICTL 0x0b0 89 #define CM_SMIDIV 0x0b4 90 /* no definition for 0x0b8 and 0x0bc */ 91 #define CM_TCNTCTL 0x0c0 92 # define CM_TCNT_SRC1_SHIFT 12 93 #define CM_TCNTCNT 0x0c4 94 #define CM_TECCTL 0x0c8 95 #define CM_TECDIV 0x0cc 96 #define CM_TD0CTL 0x0d0 97 #define CM_TD0DIV 0x0d4 98 #define CM_TD1CTL 0x0d8 99 #define CM_TD1DIV 0x0dc 100 #define CM_TSENSCTL 0x0e0 101 #define CM_TSENSDIV 0x0e4 102 #define CM_TIMERCTL 0x0e8 103 #define CM_TIMERDIV 0x0ec 104 #define CM_UARTCTL 0x0f0 105 #define CM_UARTDIV 0x0f4 106 #define CM_VECCTL 0x0f8 107 #define CM_VECDIV 0x0fc 108 #define CM_PULSECTL 0x190 109 #define CM_PULSEDIV 0x194 110 #define CM_SDCCTL 0x1a8 111 #define CM_SDCDIV 0x1ac 112 #define CM_ARMCTL 0x1b0 113 #define CM_AVEOCTL 0x1b8 114 #define CM_AVEODIV 0x1bc 115 #define CM_EMMCCTL 0x1c0 116 #define CM_EMMCDIV 0x1c4 117 #define CM_EMMC2CTL 0x1d0 118 #define CM_EMMC2DIV 0x1d4 119 120 /* General bits for the CM_*CTL regs */ 121 # define CM_ENABLE BIT(4) 122 # define CM_KILL BIT(5) 123 # define CM_GATE_BIT 6 124 # define CM_GATE BIT(CM_GATE_BIT) 125 # define CM_BUSY BIT(7) 126 # define CM_BUSYD BIT(8) 127 # define CM_FRAC BIT(9) 128 # define CM_SRC_SHIFT 0 129 # define CM_SRC_BITS 4 130 # define CM_SRC_MASK 0xf 131 # define CM_SRC_GND 0 132 # define CM_SRC_OSC 1 133 # define CM_SRC_TESTDEBUG0 2 134 # define CM_SRC_TESTDEBUG1 3 135 # define CM_SRC_PLLA_CORE 4 136 # define CM_SRC_PLLA_PER 4 137 # define CM_SRC_PLLC_CORE0 5 138 # define CM_SRC_PLLC_PER 5 139 # define CM_SRC_PLLC_CORE1 8 140 # define CM_SRC_PLLD_CORE 6 141 # define CM_SRC_PLLD_PER 6 142 # define CM_SRC_PLLH_AUX 7 143 # define CM_SRC_PLLC_CORE1 8 144 # define CM_SRC_PLLC_CORE2 9 145 146 #define CM_OSCCOUNT 0x100 147 148 #define CM_PLLA 0x104 149 # define CM_PLL_ANARST BIT(8) 150 # define CM_PLLA_HOLDPER BIT(7) 151 # define CM_PLLA_LOADPER BIT(6) 152 # define CM_PLLA_HOLDCORE BIT(5) 153 # define CM_PLLA_LOADCORE BIT(4) 154 # define CM_PLLA_HOLDCCP2 BIT(3) 155 # define CM_PLLA_LOADCCP2 BIT(2) 156 # define CM_PLLA_HOLDDSI0 BIT(1) 157 # define CM_PLLA_LOADDSI0 BIT(0) 158 159 #define CM_PLLC 0x108 160 # define CM_PLLC_HOLDPER BIT(7) 161 # define CM_PLLC_LOADPER BIT(6) 162 # define CM_PLLC_HOLDCORE2 BIT(5) 163 # define CM_PLLC_LOADCORE2 BIT(4) 164 # define CM_PLLC_HOLDCORE1 BIT(3) 165 # define CM_PLLC_LOADCORE1 BIT(2) 166 # define CM_PLLC_HOLDCORE0 BIT(1) 167 # define CM_PLLC_LOADCORE0 BIT(0) 168 169 #define CM_PLLD 0x10c 170 # define CM_PLLD_HOLDPER BIT(7) 171 # define CM_PLLD_LOADPER BIT(6) 172 # define CM_PLLD_HOLDCORE BIT(5) 173 # define CM_PLLD_LOADCORE BIT(4) 174 # define CM_PLLD_HOLDDSI1 BIT(3) 175 # define CM_PLLD_LOADDSI1 BIT(2) 176 # define CM_PLLD_HOLDDSI0 BIT(1) 177 # define CM_PLLD_LOADDSI0 BIT(0) 178 179 #define CM_PLLH 0x110 180 # define CM_PLLH_LOADRCAL BIT(2) 181 # define CM_PLLH_LOADAUX BIT(1) 182 # define CM_PLLH_LOADPIX BIT(0) 183 184 #define CM_LOCK 0x114 185 # define CM_LOCK_FLOCKH BIT(12) 186 # define CM_LOCK_FLOCKD BIT(11) 187 # define CM_LOCK_FLOCKC BIT(10) 188 # define CM_LOCK_FLOCKB BIT(9) 189 # define CM_LOCK_FLOCKA BIT(8) 190 191 #define CM_EVENT 0x118 192 #define CM_DSI1ECTL 0x158 193 #define CM_DSI1EDIV 0x15c 194 #define CM_DSI1PCTL 0x160 195 #define CM_DSI1PDIV 0x164 196 #define CM_DFTCTL 0x168 197 #define CM_DFTDIV 0x16c 198 199 #define CM_PLLB 0x170 200 # define CM_PLLB_HOLDARM BIT(1) 201 # define CM_PLLB_LOADARM BIT(0) 202 203 #define A2W_PLLA_CTRL 0x1100 204 #define A2W_PLLC_CTRL 0x1120 205 #define A2W_PLLD_CTRL 0x1140 206 #define A2W_PLLH_CTRL 0x1160 207 #define A2W_PLLB_CTRL 0x11e0 208 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17) 209 # define A2W_PLL_CTRL_PWRDN BIT(16) 210 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000 211 # define A2W_PLL_CTRL_PDIV_SHIFT 12 212 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff 213 # define A2W_PLL_CTRL_NDIV_SHIFT 0 214 215 #define A2W_PLLA_ANA0 0x1010 216 #define A2W_PLLC_ANA0 0x1030 217 #define A2W_PLLD_ANA0 0x1050 218 #define A2W_PLLH_ANA0 0x1070 219 #define A2W_PLLB_ANA0 0x10f0 220 221 #define A2W_PLL_KA_SHIFT 7 222 #define A2W_PLL_KA_MASK GENMASK(9, 7) 223 #define A2W_PLL_KI_SHIFT 19 224 #define A2W_PLL_KI_MASK GENMASK(21, 19) 225 #define A2W_PLL_KP_SHIFT 15 226 #define A2W_PLL_KP_MASK GENMASK(18, 15) 227 228 #define A2W_PLLH_KA_SHIFT 19 229 #define A2W_PLLH_KA_MASK GENMASK(21, 19) 230 #define A2W_PLLH_KI_LOW_SHIFT 22 231 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22) 232 #define A2W_PLLH_KI_HIGH_SHIFT 0 233 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0) 234 #define A2W_PLLH_KP_SHIFT 1 235 #define A2W_PLLH_KP_MASK GENMASK(4, 1) 236 237 #define A2W_XOSC_CTRL 0x1190 238 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7) 239 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6) 240 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5) 241 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4) 242 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3) 243 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2) 244 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1) 245 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0) 246 247 #define A2W_PLLA_FRAC 0x1200 248 #define A2W_PLLC_FRAC 0x1220 249 #define A2W_PLLD_FRAC 0x1240 250 #define A2W_PLLH_FRAC 0x1260 251 #define A2W_PLLB_FRAC 0x12e0 252 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1) 253 # define A2W_PLL_FRAC_BITS 20 254 255 #define A2W_PLL_CHANNEL_DISABLE BIT(8) 256 #define A2W_PLL_DIV_BITS 8 257 #define A2W_PLL_DIV_SHIFT 0 258 259 #define A2W_PLLA_DSI0 0x1300 260 #define A2W_PLLA_CORE 0x1400 261 #define A2W_PLLA_PER 0x1500 262 #define A2W_PLLA_CCP2 0x1600 263 264 #define A2W_PLLC_CORE2 0x1320 265 #define A2W_PLLC_CORE1 0x1420 266 #define A2W_PLLC_PER 0x1520 267 #define A2W_PLLC_CORE0 0x1620 268 269 #define A2W_PLLD_DSI0 0x1340 270 #define A2W_PLLD_CORE 0x1440 271 #define A2W_PLLD_PER 0x1540 272 #define A2W_PLLD_DSI1 0x1640 273 274 #define A2W_PLLH_AUX 0x1360 275 #define A2W_PLLH_RCAL 0x1460 276 #define A2W_PLLH_PIX 0x1560 277 #define A2W_PLLH_STS 0x1660 278 279 #define A2W_PLLH_CTRLR 0x1960 280 #define A2W_PLLH_FRACR 0x1a60 281 #define A2W_PLLH_AUXR 0x1b60 282 #define A2W_PLLH_RCALR 0x1c60 283 #define A2W_PLLH_PIXR 0x1d60 284 #define A2W_PLLH_STSR 0x1e60 285 286 #define A2W_PLLB_ARM 0x13e0 287 #define A2W_PLLB_SP0 0x14e0 288 #define A2W_PLLB_SP1 0x15e0 289 #define A2W_PLLB_SP2 0x16e0 290 291 #define LOCK_TIMEOUT_NS 100000000 292 #define BCM2835_MAX_FB_RATE 1750000000u 293 294 #define SOC_BCM2835 BIT(0) 295 #define SOC_BCM2711 BIT(1) 296 #define SOC_ALL (SOC_BCM2835 | SOC_BCM2711) 297 298 /* 299 * Names of clocks used within the driver that need to be replaced 300 * with an external parent's name. This array is in the order that 301 * the clocks node in the DT references external clocks. 302 */ 303 static const char *const cprman_parent_names[] = { 304 "xosc", 305 "dsi0_byte", 306 "dsi0_ddr2", 307 "dsi0_ddr", 308 "dsi1_byte", 309 "dsi1_ddr2", 310 "dsi1_ddr", 311 }; 312 313 struct bcm2835_cprman { 314 struct device *dev; 315 void __iomem *regs; 316 spinlock_t regs_lock; /* spinlock for all clocks */ 317 unsigned int soc; 318 319 /* 320 * Real names of cprman clock parents looked up through 321 * of_clk_get_parent_name(), which will be used in the 322 * parent_names[] arrays for clock registration. 323 */ 324 const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)]; 325 326 /* Must be last */ 327 struct clk_hw_onecell_data onecell; 328 }; 329 330 struct cprman_plat_data { 331 unsigned int soc; 332 }; 333 334 static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) 335 { 336 writel(CM_PASSWORD | val, cprman->regs + reg); 337 } 338 339 static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg) 340 { 341 return readl(cprman->regs + reg); 342 } 343 344 /* Does a cycle of measuring a clock through the TCNT clock, which may 345 * source from many other clocks in the system. 346 */ 347 static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman, 348 u32 tcnt_mux) 349 { 350 u32 osccount = 19200; /* 1ms */ 351 u32 count; 352 ktime_t timeout; 353 354 spin_lock(&cprman->regs_lock); 355 356 cprman_write(cprman, CM_TCNTCTL, CM_KILL); 357 358 cprman_write(cprman, CM_TCNTCTL, 359 (tcnt_mux & CM_SRC_MASK) | 360 (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT); 361 362 cprman_write(cprman, CM_OSCCOUNT, osccount); 363 364 /* do a kind delay at the start */ 365 mdelay(1); 366 367 /* Finish off whatever is left of OSCCOUNT */ 368 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 369 while (cprman_read(cprman, CM_OSCCOUNT)) { 370 if (ktime_after(ktime_get(), timeout)) { 371 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n"); 372 count = 0; 373 goto out; 374 } 375 cpu_relax(); 376 } 377 378 /* Wait for BUSY to clear. */ 379 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 380 while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) { 381 if (ktime_after(ktime_get(), timeout)) { 382 dev_err(cprman->dev, "timeout waiting for !BUSY\n"); 383 count = 0; 384 goto out; 385 } 386 cpu_relax(); 387 } 388 389 count = cprman_read(cprman, CM_TCNTCNT); 390 391 cprman_write(cprman, CM_TCNTCTL, 0); 392 393 out: 394 spin_unlock(&cprman->regs_lock); 395 396 return count * 1000; 397 } 398 399 static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, 400 const struct debugfs_reg32 *regs, 401 size_t nregs, struct dentry *dentry) 402 { 403 struct debugfs_regset32 *regset; 404 405 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL); 406 if (!regset) 407 return; 408 409 regset->regs = regs; 410 regset->nregs = nregs; 411 regset->base = cprman->regs + base; 412 413 debugfs_create_regset32("regdump", S_IRUGO, dentry, regset); 414 } 415 416 struct bcm2835_pll_data { 417 const char *name; 418 u32 cm_ctrl_reg; 419 u32 a2w_ctrl_reg; 420 u32 frac_reg; 421 u32 ana_reg_base; 422 u32 reference_enable_mask; 423 /* Bit in CM_LOCK to indicate when the PLL has locked. */ 424 u32 lock_mask; 425 u32 flags; 426 427 const struct bcm2835_pll_ana_bits *ana; 428 429 unsigned long min_rate; 430 unsigned long max_rate; 431 /* 432 * Highest rate for the VCO before we have to use the 433 * pre-divide-by-2. 434 */ 435 unsigned long max_fb_rate; 436 }; 437 438 struct bcm2835_pll_ana_bits { 439 u32 mask0; 440 u32 set0; 441 u32 mask1; 442 u32 set1; 443 u32 mask3; 444 u32 set3; 445 u32 fb_prediv_mask; 446 }; 447 448 static const struct bcm2835_pll_ana_bits bcm2835_ana_default = { 449 .mask0 = 0, 450 .set0 = 0, 451 .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK, 452 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT), 453 .mask3 = A2W_PLL_KA_MASK, 454 .set3 = (2 << A2W_PLL_KA_SHIFT), 455 .fb_prediv_mask = BIT(14), 456 }; 457 458 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = { 459 .mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK, 460 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT), 461 .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK, 462 .set1 = (6 << A2W_PLLH_KP_SHIFT), 463 .mask3 = 0, 464 .set3 = 0, 465 .fb_prediv_mask = BIT(11), 466 }; 467 468 struct bcm2835_pll_divider_data { 469 const char *name; 470 const char *source_pll; 471 472 u32 cm_reg; 473 u32 a2w_reg; 474 475 u32 load_mask; 476 u32 hold_mask; 477 u32 fixed_divider; 478 u32 flags; 479 }; 480 481 struct bcm2835_clock_data { 482 const char *name; 483 484 const char *const *parents; 485 int num_mux_parents; 486 487 /* Bitmap encoding which parents accept rate change propagation. */ 488 unsigned int set_rate_parent; 489 490 u32 ctl_reg; 491 u32 div_reg; 492 493 /* Number of integer bits in the divider */ 494 u32 int_bits; 495 /* Number of fractional bits in the divider */ 496 u32 frac_bits; 497 498 u32 flags; 499 500 bool is_vpu_clock; 501 bool is_mash_clock; 502 bool low_jitter; 503 504 u32 tcnt_mux; 505 }; 506 507 struct bcm2835_gate_data { 508 const char *name; 509 const char *parent; 510 511 u32 ctl_reg; 512 }; 513 514 struct bcm2835_pll { 515 struct clk_hw hw; 516 struct bcm2835_cprman *cprman; 517 const struct bcm2835_pll_data *data; 518 }; 519 520 static int bcm2835_pll_is_on(struct clk_hw *hw) 521 { 522 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 523 struct bcm2835_cprman *cprman = pll->cprman; 524 const struct bcm2835_pll_data *data = pll->data; 525 526 return cprman_read(cprman, data->a2w_ctrl_reg) & 527 A2W_PLL_CTRL_PRST_DISABLE; 528 } 529 530 static u32 bcm2835_pll_get_prediv_mask(struct bcm2835_cprman *cprman, 531 const struct bcm2835_pll_data *data) 532 { 533 /* 534 * On BCM2711 there isn't a pre-divisor available in the PLL feedback 535 * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed 536 * for to for VCO RANGE bits. 537 */ 538 if (cprman->soc & SOC_BCM2711) 539 return 0; 540 541 return data->ana->fb_prediv_mask; 542 } 543 544 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate, 545 unsigned long parent_rate, 546 u32 *ndiv, u32 *fdiv) 547 { 548 u64 div; 549 550 div = (u64)rate << A2W_PLL_FRAC_BITS; 551 do_div(div, parent_rate); 552 553 *ndiv = div >> A2W_PLL_FRAC_BITS; 554 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); 555 } 556 557 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate, 558 u32 ndiv, u32 fdiv, u32 pdiv) 559 { 560 u64 rate; 561 562 if (pdiv == 0) 563 return 0; 564 565 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); 566 do_div(rate, pdiv); 567 return rate >> A2W_PLL_FRAC_BITS; 568 } 569 570 static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate, 571 unsigned long *parent_rate) 572 { 573 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 574 const struct bcm2835_pll_data *data = pll->data; 575 u32 ndiv, fdiv; 576 577 rate = clamp(rate, data->min_rate, data->max_rate); 578 579 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); 580 581 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); 582 } 583 584 static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw, 585 unsigned long parent_rate) 586 { 587 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 588 struct bcm2835_cprman *cprman = pll->cprman; 589 const struct bcm2835_pll_data *data = pll->data; 590 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); 591 u32 ndiv, pdiv, fdiv; 592 bool using_prediv; 593 594 if (parent_rate == 0) 595 return 0; 596 597 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; 598 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT; 599 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT; 600 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & 601 bcm2835_pll_get_prediv_mask(cprman, data); 602 603 if (using_prediv) { 604 ndiv *= 2; 605 fdiv *= 2; 606 } 607 608 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv); 609 } 610 611 static void bcm2835_pll_off(struct clk_hw *hw) 612 { 613 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 614 struct bcm2835_cprman *cprman = pll->cprman; 615 const struct bcm2835_pll_data *data = pll->data; 616 617 spin_lock(&cprman->regs_lock); 618 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST); 619 cprman_write(cprman, data->a2w_ctrl_reg, 620 cprman_read(cprman, data->a2w_ctrl_reg) | 621 A2W_PLL_CTRL_PWRDN); 622 spin_unlock(&cprman->regs_lock); 623 } 624 625 static int bcm2835_pll_on(struct clk_hw *hw) 626 { 627 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 628 struct bcm2835_cprman *cprman = pll->cprman; 629 const struct bcm2835_pll_data *data = pll->data; 630 ktime_t timeout; 631 632 cprman_write(cprman, data->a2w_ctrl_reg, 633 cprman_read(cprman, data->a2w_ctrl_reg) & 634 ~A2W_PLL_CTRL_PWRDN); 635 636 /* Take the PLL out of reset. */ 637 spin_lock(&cprman->regs_lock); 638 cprman_write(cprman, data->cm_ctrl_reg, 639 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); 640 spin_unlock(&cprman->regs_lock); 641 642 /* Wait for the PLL to lock. */ 643 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 644 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { 645 if (ktime_after(ktime_get(), timeout)) { 646 dev_err(cprman->dev, "%s: couldn't lock PLL\n", 647 clk_hw_get_name(hw)); 648 return -ETIMEDOUT; 649 } 650 651 cpu_relax(); 652 } 653 654 cprman_write(cprman, data->a2w_ctrl_reg, 655 cprman_read(cprman, data->a2w_ctrl_reg) | 656 A2W_PLL_CTRL_PRST_DISABLE); 657 658 return 0; 659 } 660 661 static void 662 bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana) 663 { 664 int i; 665 666 /* 667 * ANA register setup is done as a series of writes to 668 * ANA3-ANA0, in that order. This lets us write all 4 669 * registers as a single cycle of the serdes interface (taking 670 * 100 xosc clocks), whereas if we were to update ana0, 1, and 671 * 3 individually through their partial-write registers, each 672 * would be their own serdes cycle. 673 */ 674 for (i = 3; i >= 0; i--) 675 cprman_write(cprman, ana_reg_base + i * 4, ana[i]); 676 } 677 678 static int bcm2835_pll_set_rate(struct clk_hw *hw, 679 unsigned long rate, unsigned long parent_rate) 680 { 681 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 682 struct bcm2835_cprman *cprman = pll->cprman; 683 const struct bcm2835_pll_data *data = pll->data; 684 u32 prediv_mask = bcm2835_pll_get_prediv_mask(cprman, data); 685 bool was_using_prediv, use_fb_prediv, do_ana_setup_first; 686 u32 ndiv, fdiv, a2w_ctl; 687 u32 ana[4]; 688 int i; 689 690 if (rate > data->max_fb_rate) { 691 use_fb_prediv = true; 692 rate /= 2; 693 } else { 694 use_fb_prediv = false; 695 } 696 697 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv); 698 699 for (i = 3; i >= 0; i--) 700 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); 701 702 was_using_prediv = ana[1] & prediv_mask; 703 704 ana[0] &= ~data->ana->mask0; 705 ana[0] |= data->ana->set0; 706 ana[1] &= ~data->ana->mask1; 707 ana[1] |= data->ana->set1; 708 ana[3] &= ~data->ana->mask3; 709 ana[3] |= data->ana->set3; 710 711 if (was_using_prediv && !use_fb_prediv) { 712 ana[1] &= ~prediv_mask; 713 do_ana_setup_first = true; 714 } else if (!was_using_prediv && use_fb_prediv) { 715 ana[1] |= prediv_mask; 716 do_ana_setup_first = false; 717 } else { 718 do_ana_setup_first = true; 719 } 720 721 /* Unmask the reference clock from the oscillator. */ 722 spin_lock(&cprman->regs_lock); 723 cprman_write(cprman, A2W_XOSC_CTRL, 724 cprman_read(cprman, A2W_XOSC_CTRL) | 725 data->reference_enable_mask); 726 spin_unlock(&cprman->regs_lock); 727 728 if (do_ana_setup_first) 729 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); 730 731 /* Set the PLL multiplier from the oscillator. */ 732 cprman_write(cprman, data->frac_reg, fdiv); 733 734 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); 735 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK; 736 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT; 737 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK; 738 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT; 739 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); 740 741 if (!do_ana_setup_first) 742 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); 743 744 return 0; 745 } 746 747 static void bcm2835_pll_debug_init(struct clk_hw *hw, 748 struct dentry *dentry) 749 { 750 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 751 struct bcm2835_cprman *cprman = pll->cprman; 752 const struct bcm2835_pll_data *data = pll->data; 753 struct debugfs_reg32 *regs; 754 755 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL); 756 if (!regs) 757 return; 758 759 regs[0].name = "cm_ctrl"; 760 regs[0].offset = data->cm_ctrl_reg; 761 regs[1].name = "a2w_ctrl"; 762 regs[1].offset = data->a2w_ctrl_reg; 763 regs[2].name = "frac"; 764 regs[2].offset = data->frac_reg; 765 regs[3].name = "ana0"; 766 regs[3].offset = data->ana_reg_base + 0 * 4; 767 regs[4].name = "ana1"; 768 regs[4].offset = data->ana_reg_base + 1 * 4; 769 regs[5].name = "ana2"; 770 regs[5].offset = data->ana_reg_base + 2 * 4; 771 regs[6].name = "ana3"; 772 regs[6].offset = data->ana_reg_base + 3 * 4; 773 774 bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry); 775 } 776 777 static const struct clk_ops bcm2835_pll_clk_ops = { 778 .is_prepared = bcm2835_pll_is_on, 779 .prepare = bcm2835_pll_on, 780 .unprepare = bcm2835_pll_off, 781 .recalc_rate = bcm2835_pll_get_rate, 782 .set_rate = bcm2835_pll_set_rate, 783 .round_rate = bcm2835_pll_round_rate, 784 .debug_init = bcm2835_pll_debug_init, 785 }; 786 787 struct bcm2835_pll_divider { 788 struct clk_divider div; 789 struct bcm2835_cprman *cprman; 790 const struct bcm2835_pll_divider_data *data; 791 }; 792 793 static struct bcm2835_pll_divider * 794 bcm2835_pll_divider_from_hw(struct clk_hw *hw) 795 { 796 return container_of(hw, struct bcm2835_pll_divider, div.hw); 797 } 798 799 static int bcm2835_pll_divider_is_on(struct clk_hw *hw) 800 { 801 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 802 struct bcm2835_cprman *cprman = divider->cprman; 803 const struct bcm2835_pll_divider_data *data = divider->data; 804 805 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); 806 } 807 808 static int bcm2835_pll_divider_determine_rate(struct clk_hw *hw, 809 struct clk_rate_request *req) 810 { 811 return clk_divider_ops.determine_rate(hw, req); 812 } 813 814 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw, 815 unsigned long parent_rate) 816 { 817 return clk_divider_ops.recalc_rate(hw, parent_rate); 818 } 819 820 static void bcm2835_pll_divider_off(struct clk_hw *hw) 821 { 822 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 823 struct bcm2835_cprman *cprman = divider->cprman; 824 const struct bcm2835_pll_divider_data *data = divider->data; 825 826 spin_lock(&cprman->regs_lock); 827 cprman_write(cprman, data->cm_reg, 828 (cprman_read(cprman, data->cm_reg) & 829 ~data->load_mask) | data->hold_mask); 830 cprman_write(cprman, data->a2w_reg, 831 cprman_read(cprman, data->a2w_reg) | 832 A2W_PLL_CHANNEL_DISABLE); 833 spin_unlock(&cprman->regs_lock); 834 } 835 836 static int bcm2835_pll_divider_on(struct clk_hw *hw) 837 { 838 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 839 struct bcm2835_cprman *cprman = divider->cprman; 840 const struct bcm2835_pll_divider_data *data = divider->data; 841 842 spin_lock(&cprman->regs_lock); 843 cprman_write(cprman, data->a2w_reg, 844 cprman_read(cprman, data->a2w_reg) & 845 ~A2W_PLL_CHANNEL_DISABLE); 846 847 cprman_write(cprman, data->cm_reg, 848 cprman_read(cprman, data->cm_reg) & ~data->hold_mask); 849 spin_unlock(&cprman->regs_lock); 850 851 return 0; 852 } 853 854 static int bcm2835_pll_divider_set_rate(struct clk_hw *hw, 855 unsigned long rate, 856 unsigned long parent_rate) 857 { 858 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 859 struct bcm2835_cprman *cprman = divider->cprman; 860 const struct bcm2835_pll_divider_data *data = divider->data; 861 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS; 862 863 div = DIV_ROUND_UP_ULL(parent_rate, rate); 864 865 div = min(div, max_div); 866 if (div == max_div) 867 div = 0; 868 869 cprman_write(cprman, data->a2w_reg, div); 870 cm = cprman_read(cprman, data->cm_reg); 871 cprman_write(cprman, data->cm_reg, cm | data->load_mask); 872 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); 873 874 return 0; 875 } 876 877 static void bcm2835_pll_divider_debug_init(struct clk_hw *hw, 878 struct dentry *dentry) 879 { 880 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 881 struct bcm2835_cprman *cprman = divider->cprman; 882 const struct bcm2835_pll_divider_data *data = divider->data; 883 struct debugfs_reg32 *regs; 884 885 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL); 886 if (!regs) 887 return; 888 889 regs[0].name = "cm"; 890 regs[0].offset = data->cm_reg; 891 regs[1].name = "a2w"; 892 regs[1].offset = data->a2w_reg; 893 894 bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry); 895 } 896 897 static const struct clk_ops bcm2835_pll_divider_clk_ops = { 898 .is_prepared = bcm2835_pll_divider_is_on, 899 .prepare = bcm2835_pll_divider_on, 900 .unprepare = bcm2835_pll_divider_off, 901 .recalc_rate = bcm2835_pll_divider_get_rate, 902 .set_rate = bcm2835_pll_divider_set_rate, 903 .determine_rate = bcm2835_pll_divider_determine_rate, 904 .debug_init = bcm2835_pll_divider_debug_init, 905 }; 906 907 /* 908 * The CM dividers do fixed-point division, so we can't use the 909 * generic integer divider code like the PLL dividers do (and we can't 910 * fake it by having some fixed shifts preceding it in the clock tree, 911 * because we'd run out of bits in a 32-bit unsigned long). 912 */ 913 struct bcm2835_clock { 914 struct clk_hw hw; 915 struct bcm2835_cprman *cprman; 916 const struct bcm2835_clock_data *data; 917 }; 918 919 static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw) 920 { 921 return container_of(hw, struct bcm2835_clock, hw); 922 } 923 924 static int bcm2835_clock_is_on(struct clk_hw *hw) 925 { 926 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 927 struct bcm2835_cprman *cprman = clock->cprman; 928 const struct bcm2835_clock_data *data = clock->data; 929 930 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; 931 } 932 933 static u32 bcm2835_clock_choose_div(struct clk_hw *hw, 934 unsigned long rate, 935 unsigned long parent_rate) 936 { 937 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 938 const struct bcm2835_clock_data *data = clock->data; 939 u32 unused_frac_mask = 940 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; 941 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; 942 u32 div, mindiv, maxdiv; 943 944 do_div(temp, rate); 945 div = temp; 946 div &= ~unused_frac_mask; 947 948 /* different clamping limits apply for a mash clock */ 949 if (data->is_mash_clock) { 950 /* clamp to min divider of 2 */ 951 mindiv = 2 << CM_DIV_FRAC_BITS; 952 /* clamp to the highest possible integer divider */ 953 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; 954 } else { 955 /* clamp to min divider of 1 */ 956 mindiv = 1 << CM_DIV_FRAC_BITS; 957 /* clamp to the highest possible fractional divider */ 958 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, 959 CM_DIV_FRAC_BITS - data->frac_bits); 960 } 961 962 /* apply the clamping limits */ 963 div = max_t(u32, div, mindiv); 964 div = min_t(u32, div, maxdiv); 965 966 return div; 967 } 968 969 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, 970 unsigned long parent_rate, 971 u32 div) 972 { 973 const struct bcm2835_clock_data *data = clock->data; 974 u64 temp; 975 976 if (data->int_bits == 0 && data->frac_bits == 0) 977 return parent_rate; 978 979 /* 980 * The divisor is a 12.12 fixed point field, but only some of 981 * the bits are populated in any given clock. 982 */ 983 div >>= CM_DIV_FRAC_BITS - data->frac_bits; 984 div &= (1 << (data->int_bits + data->frac_bits)) - 1; 985 986 if (div == 0) 987 return 0; 988 989 temp = (u64)parent_rate << data->frac_bits; 990 991 do_div(temp, div); 992 993 return temp; 994 } 995 996 static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, 997 unsigned long parent_rate) 998 { 999 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1000 struct bcm2835_cprman *cprman = clock->cprman; 1001 const struct bcm2835_clock_data *data = clock->data; 1002 u32 div; 1003 1004 if (data->int_bits == 0 && data->frac_bits == 0) 1005 return parent_rate; 1006 1007 div = cprman_read(cprman, data->div_reg); 1008 1009 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); 1010 } 1011 1012 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) 1013 { 1014 struct bcm2835_cprman *cprman = clock->cprman; 1015 const struct bcm2835_clock_data *data = clock->data; 1016 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 1017 1018 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { 1019 if (ktime_after(ktime_get(), timeout)) { 1020 dev_err(cprman->dev, "%s: couldn't lock PLL\n", 1021 clk_hw_get_name(&clock->hw)); 1022 return; 1023 } 1024 cpu_relax(); 1025 } 1026 } 1027 1028 static void bcm2835_clock_off(struct clk_hw *hw) 1029 { 1030 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1031 struct bcm2835_cprman *cprman = clock->cprman; 1032 const struct bcm2835_clock_data *data = clock->data; 1033 1034 spin_lock(&cprman->regs_lock); 1035 cprman_write(cprman, data->ctl_reg, 1036 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); 1037 spin_unlock(&cprman->regs_lock); 1038 1039 /* BUSY will remain high until the divider completes its cycle. */ 1040 bcm2835_clock_wait_busy(clock); 1041 } 1042 1043 static int bcm2835_clock_on(struct clk_hw *hw) 1044 { 1045 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1046 struct bcm2835_cprman *cprman = clock->cprman; 1047 const struct bcm2835_clock_data *data = clock->data; 1048 1049 spin_lock(&cprman->regs_lock); 1050 cprman_write(cprman, data->ctl_reg, 1051 cprman_read(cprman, data->ctl_reg) | 1052 CM_ENABLE | 1053 CM_GATE); 1054 spin_unlock(&cprman->regs_lock); 1055 1056 /* Debug code to measure the clock once it's turned on to see 1057 * if it's ticking at the rate we expect. 1058 */ 1059 if (data->tcnt_mux && false) { 1060 dev_info(cprman->dev, 1061 "clk %s: rate %ld, measure %ld\n", 1062 data->name, 1063 clk_hw_get_rate(hw), 1064 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux)); 1065 } 1066 1067 return 0; 1068 } 1069 1070 static int bcm2835_clock_set_rate(struct clk_hw *hw, 1071 unsigned long rate, unsigned long parent_rate) 1072 { 1073 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1074 struct bcm2835_cprman *cprman = clock->cprman; 1075 const struct bcm2835_clock_data *data = clock->data; 1076 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate); 1077 u32 ctl; 1078 1079 spin_lock(&cprman->regs_lock); 1080 1081 /* 1082 * Setting up frac support 1083 * 1084 * In principle it is recommended to stop/start the clock first, 1085 * but as we set CLK_SET_RATE_GATE during registration of the 1086 * clock this requirement should be take care of by the 1087 * clk-framework. 1088 */ 1089 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; 1090 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; 1091 cprman_write(cprman, data->ctl_reg, ctl); 1092 1093 cprman_write(cprman, data->div_reg, div); 1094 1095 spin_unlock(&cprman->regs_lock); 1096 1097 return 0; 1098 } 1099 1100 static bool 1101 bcm2835_clk_is_pllc(struct clk_hw *hw) 1102 { 1103 if (!hw) 1104 return false; 1105 1106 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0; 1107 } 1108 1109 static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw, 1110 int parent_idx, 1111 unsigned long rate, 1112 u32 *div, 1113 unsigned long *prate, 1114 unsigned long *avgrate) 1115 { 1116 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1117 struct bcm2835_cprman *cprman = clock->cprman; 1118 const struct bcm2835_clock_data *data = clock->data; 1119 unsigned long best_rate = 0; 1120 u32 curdiv, mindiv, maxdiv; 1121 struct clk_hw *parent; 1122 1123 parent = clk_hw_get_parent_by_index(hw, parent_idx); 1124 1125 if (!(BIT(parent_idx) & data->set_rate_parent)) { 1126 *prate = clk_hw_get_rate(parent); 1127 *div = bcm2835_clock_choose_div(hw, rate, *prate); 1128 1129 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div); 1130 1131 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) { 1132 unsigned long high, low; 1133 u32 int_div = *div & ~CM_DIV_FRAC_MASK; 1134 1135 high = bcm2835_clock_rate_from_divisor(clock, *prate, 1136 int_div); 1137 int_div += CM_DIV_FRAC_MASK + 1; 1138 low = bcm2835_clock_rate_from_divisor(clock, *prate, 1139 int_div); 1140 1141 /* 1142 * Return a value which is the maximum deviation 1143 * below the ideal rate, for use as a metric. 1144 */ 1145 return *avgrate - max(*avgrate - low, high - *avgrate); 1146 } 1147 return *avgrate; 1148 } 1149 1150 if (data->frac_bits) 1151 dev_warn(cprman->dev, 1152 "frac bits are not used when propagating rate change"); 1153 1154 /* clamp to min divider of 2 if we're dealing with a mash clock */ 1155 mindiv = data->is_mash_clock ? 2 : 1; 1156 maxdiv = BIT(data->int_bits) - 1; 1157 1158 /* TODO: Be smart, and only test a subset of the available divisors. */ 1159 for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) { 1160 unsigned long tmp_rate; 1161 1162 tmp_rate = clk_hw_round_rate(parent, rate * curdiv); 1163 tmp_rate /= curdiv; 1164 if (curdiv == mindiv || 1165 (tmp_rate > best_rate && tmp_rate <= rate)) 1166 best_rate = tmp_rate; 1167 1168 if (best_rate == rate) 1169 break; 1170 } 1171 1172 *div = curdiv << CM_DIV_FRAC_BITS; 1173 *prate = curdiv * best_rate; 1174 *avgrate = best_rate; 1175 1176 return best_rate; 1177 } 1178 1179 static int bcm2835_clock_determine_rate(struct clk_hw *hw, 1180 struct clk_rate_request *req) 1181 { 1182 struct clk_hw *parent, *best_parent = NULL; 1183 bool current_parent_is_pllc; 1184 unsigned long rate, best_rate = 0; 1185 unsigned long prate, best_prate = 0; 1186 unsigned long avgrate, best_avgrate = 0; 1187 size_t i; 1188 u32 div; 1189 1190 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw)); 1191 1192 /* 1193 * Select parent clock that results in the closest but lower rate 1194 */ 1195 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) { 1196 parent = clk_hw_get_parent_by_index(hw, i); 1197 if (!parent) 1198 continue; 1199 1200 /* 1201 * Don't choose a PLLC-derived clock as our parent 1202 * unless it had been manually set that way. PLLC's 1203 * frequency gets adjusted by the firmware due to 1204 * over-temp or under-voltage conditions, without 1205 * prior notification to our clock consumer. 1206 */ 1207 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc) 1208 continue; 1209 1210 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate, 1211 &div, &prate, 1212 &avgrate); 1213 if (abs(req->rate - rate) < abs(req->rate - best_rate)) { 1214 best_parent = parent; 1215 best_prate = prate; 1216 best_rate = rate; 1217 best_avgrate = avgrate; 1218 } 1219 } 1220 1221 if (!best_parent) 1222 return -EINVAL; 1223 1224 req->best_parent_hw = best_parent; 1225 req->best_parent_rate = best_prate; 1226 1227 req->rate = best_avgrate; 1228 1229 return 0; 1230 } 1231 1232 static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index) 1233 { 1234 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1235 struct bcm2835_cprman *cprman = clock->cprman; 1236 const struct bcm2835_clock_data *data = clock->data; 1237 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK; 1238 1239 cprman_write(cprman, data->ctl_reg, src); 1240 return 0; 1241 } 1242 1243 static u8 bcm2835_clock_get_parent(struct clk_hw *hw) 1244 { 1245 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1246 struct bcm2835_cprman *cprman = clock->cprman; 1247 const struct bcm2835_clock_data *data = clock->data; 1248 u32 src = cprman_read(cprman, data->ctl_reg); 1249 1250 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; 1251 } 1252 1253 static const struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = { 1254 { 1255 .name = "ctl", 1256 .offset = 0, 1257 }, 1258 { 1259 .name = "div", 1260 .offset = 4, 1261 }, 1262 }; 1263 1264 static void bcm2835_clock_debug_init(struct clk_hw *hw, 1265 struct dentry *dentry) 1266 { 1267 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1268 struct bcm2835_cprman *cprman = clock->cprman; 1269 const struct bcm2835_clock_data *data = clock->data; 1270 1271 bcm2835_debugfs_regset(cprman, data->ctl_reg, 1272 bcm2835_debugfs_clock_reg32, 1273 ARRAY_SIZE(bcm2835_debugfs_clock_reg32), 1274 dentry); 1275 } 1276 1277 static const struct clk_ops bcm2835_clock_clk_ops = { 1278 .is_prepared = bcm2835_clock_is_on, 1279 .prepare = bcm2835_clock_on, 1280 .unprepare = bcm2835_clock_off, 1281 .recalc_rate = bcm2835_clock_get_rate, 1282 .set_rate = bcm2835_clock_set_rate, 1283 .determine_rate = bcm2835_clock_determine_rate, 1284 .set_parent = bcm2835_clock_set_parent, 1285 .get_parent = bcm2835_clock_get_parent, 1286 .debug_init = bcm2835_clock_debug_init, 1287 }; 1288 1289 static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) 1290 { 1291 return true; 1292 } 1293 1294 /* 1295 * The VPU clock can never be disabled (it doesn't have an ENABLE 1296 * bit), so it gets its own set of clock ops. 1297 */ 1298 static const struct clk_ops bcm2835_vpu_clock_clk_ops = { 1299 .is_prepared = bcm2835_vpu_clock_is_on, 1300 .recalc_rate = bcm2835_clock_get_rate, 1301 .set_rate = bcm2835_clock_set_rate, 1302 .determine_rate = bcm2835_clock_determine_rate, 1303 .set_parent = bcm2835_clock_set_parent, 1304 .get_parent = bcm2835_clock_get_parent, 1305 .debug_init = bcm2835_clock_debug_init, 1306 }; 1307 1308 static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, 1309 const void *data) 1310 { 1311 const struct bcm2835_pll_data *pll_data = data; 1312 struct bcm2835_pll *pll; 1313 struct clk_init_data init; 1314 int ret; 1315 1316 memset(&init, 0, sizeof(init)); 1317 1318 /* All of the PLLs derive from the external oscillator. */ 1319 init.parent_names = &cprman->real_parent_names[0]; 1320 init.num_parents = 1; 1321 init.name = pll_data->name; 1322 init.ops = &bcm2835_pll_clk_ops; 1323 init.flags = pll_data->flags | CLK_IGNORE_UNUSED; 1324 1325 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1326 if (!pll) 1327 return NULL; 1328 1329 pll->cprman = cprman; 1330 pll->data = pll_data; 1331 pll->hw.init = &init; 1332 1333 ret = devm_clk_hw_register(cprman->dev, &pll->hw); 1334 if (ret) { 1335 kfree(pll); 1336 return NULL; 1337 } 1338 return &pll->hw; 1339 } 1340 1341 static struct clk_hw * 1342 bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, 1343 const void *data) 1344 { 1345 const struct bcm2835_pll_divider_data *divider_data = data; 1346 struct bcm2835_pll_divider *divider; 1347 struct clk_init_data init; 1348 const char *divider_name; 1349 int ret; 1350 1351 if (divider_data->fixed_divider != 1) { 1352 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, 1353 "%s_prediv", divider_data->name); 1354 if (!divider_name) 1355 return NULL; 1356 } else { 1357 divider_name = divider_data->name; 1358 } 1359 1360 memset(&init, 0, sizeof(init)); 1361 1362 init.parent_names = ÷r_data->source_pll; 1363 init.num_parents = 1; 1364 init.name = divider_name; 1365 init.ops = &bcm2835_pll_divider_clk_ops; 1366 init.flags = divider_data->flags | CLK_IGNORE_UNUSED; 1367 1368 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); 1369 if (!divider) 1370 return NULL; 1371 1372 divider->div.reg = cprman->regs + divider_data->a2w_reg; 1373 divider->div.shift = A2W_PLL_DIV_SHIFT; 1374 divider->div.width = A2W_PLL_DIV_BITS; 1375 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; 1376 divider->div.lock = &cprman->regs_lock; 1377 divider->div.hw.init = &init; 1378 divider->div.table = NULL; 1379 1380 divider->cprman = cprman; 1381 divider->data = divider_data; 1382 1383 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw); 1384 if (ret) 1385 return ERR_PTR(ret); 1386 1387 /* 1388 * PLLH's channels have a fixed divide by 10 afterwards, which 1389 * is what our consumers are actually using. 1390 */ 1391 if (divider_data->fixed_divider != 1) { 1392 return clk_hw_register_fixed_factor(cprman->dev, 1393 divider_data->name, 1394 divider_name, 1395 CLK_SET_RATE_PARENT, 1396 1, 1397 divider_data->fixed_divider); 1398 } 1399 1400 return ÷r->div.hw; 1401 } 1402 1403 static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, 1404 const void *data) 1405 { 1406 const struct bcm2835_clock_data *clock_data = data; 1407 struct bcm2835_clock *clock; 1408 struct clk_init_data init; 1409 const char *parents[1 << CM_SRC_BITS]; 1410 size_t i; 1411 int ret; 1412 1413 /* 1414 * Replace our strings referencing parent clocks with the 1415 * actual clock-output-name of the parent. 1416 */ 1417 for (i = 0; i < clock_data->num_mux_parents; i++) { 1418 parents[i] = clock_data->parents[i]; 1419 1420 ret = match_string(cprman_parent_names, 1421 ARRAY_SIZE(cprman_parent_names), 1422 parents[i]); 1423 if (ret >= 0) 1424 parents[i] = cprman->real_parent_names[ret]; 1425 } 1426 1427 memset(&init, 0, sizeof(init)); 1428 init.parent_names = parents; 1429 init.num_parents = clock_data->num_mux_parents; 1430 init.name = clock_data->name; 1431 init.flags = clock_data->flags | CLK_IGNORE_UNUSED; 1432 1433 /* 1434 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate 1435 * rate changes on at least of the parents. 1436 */ 1437 if (clock_data->set_rate_parent) 1438 init.flags |= CLK_SET_RATE_PARENT; 1439 1440 if (clock_data->is_vpu_clock) { 1441 init.ops = &bcm2835_vpu_clock_clk_ops; 1442 } else { 1443 init.ops = &bcm2835_clock_clk_ops; 1444 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; 1445 1446 /* If the clock wasn't actually enabled at boot, it's not 1447 * critical. 1448 */ 1449 if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE)) 1450 init.flags &= ~CLK_IS_CRITICAL; 1451 } 1452 1453 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); 1454 if (!clock) 1455 return NULL; 1456 1457 clock->cprman = cprman; 1458 clock->data = clock_data; 1459 clock->hw.init = &init; 1460 1461 ret = devm_clk_hw_register(cprman->dev, &clock->hw); 1462 if (ret) 1463 return ERR_PTR(ret); 1464 return &clock->hw; 1465 } 1466 1467 static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman, 1468 const void *data) 1469 { 1470 const struct bcm2835_gate_data *gate_data = data; 1471 1472 return clk_hw_register_gate(cprman->dev, gate_data->name, 1473 gate_data->parent, 1474 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 1475 cprman->regs + gate_data->ctl_reg, 1476 CM_GATE_BIT, 0, &cprman->regs_lock); 1477 } 1478 1479 struct bcm2835_clk_desc { 1480 struct clk_hw *(*clk_register)(struct bcm2835_cprman *cprman, 1481 const void *data); 1482 unsigned int supported; 1483 const void *data; 1484 }; 1485 1486 /* assignment helper macros for different clock types */ 1487 #define _REGISTER(f, s, ...) { .clk_register = f, \ 1488 .supported = s, \ 1489 .data = __VA_ARGS__ } 1490 #define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \ 1491 s, \ 1492 &(struct bcm2835_pll_data) \ 1493 {__VA_ARGS__}) 1494 #define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \ 1495 s, \ 1496 &(struct bcm2835_pll_divider_data) \ 1497 {__VA_ARGS__}) 1498 #define REGISTER_CLK(s, ...) _REGISTER(&bcm2835_register_clock, \ 1499 s, \ 1500 &(struct bcm2835_clock_data) \ 1501 {__VA_ARGS__}) 1502 #define REGISTER_GATE(s, ...) _REGISTER(&bcm2835_register_gate, \ 1503 s, \ 1504 &(struct bcm2835_gate_data) \ 1505 {__VA_ARGS__}) 1506 1507 /* parent mux arrays plus helper macros */ 1508 1509 /* main oscillator parent mux */ 1510 static const char *const bcm2835_clock_osc_parents[] = { 1511 "gnd", 1512 "xosc", 1513 "testdebug0", 1514 "testdebug1" 1515 }; 1516 1517 #define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \ 1518 s, \ 1519 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \ 1520 .parents = bcm2835_clock_osc_parents, \ 1521 __VA_ARGS__) 1522 1523 /* main peripherial parent mux */ 1524 static const char *const bcm2835_clock_per_parents[] = { 1525 "gnd", 1526 "xosc", 1527 "testdebug0", 1528 "testdebug1", 1529 "plla_per", 1530 "pllc_per", 1531 "plld_per", 1532 "pllh_aux", 1533 }; 1534 1535 #define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \ 1536 s, \ 1537 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \ 1538 .parents = bcm2835_clock_per_parents, \ 1539 __VA_ARGS__) 1540 1541 /* 1542 * Restrict clock sources for the PCM peripheral to the oscillator and 1543 * PLLD_PER because other source may have varying rates or be switched 1544 * off. 1545 * 1546 * Prevent other sources from being selected by replacing their names in 1547 * the list of potential parents with dummy entries (entry index is 1548 * significant). 1549 */ 1550 static const char *const bcm2835_pcm_per_parents[] = { 1551 "-", 1552 "xosc", 1553 "-", 1554 "-", 1555 "-", 1556 "-", 1557 "plld_per", 1558 "-", 1559 }; 1560 1561 #define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \ 1562 s, \ 1563 .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \ 1564 .parents = bcm2835_pcm_per_parents, \ 1565 __VA_ARGS__) 1566 1567 /* main vpu parent mux */ 1568 static const char *const bcm2835_clock_vpu_parents[] = { 1569 "gnd", 1570 "xosc", 1571 "testdebug0", 1572 "testdebug1", 1573 "plla_core", 1574 "pllc_core0", 1575 "plld_core", 1576 "pllh_aux", 1577 "pllc_core1", 1578 "pllc_core2", 1579 }; 1580 1581 #define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \ 1582 s, \ 1583 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \ 1584 .parents = bcm2835_clock_vpu_parents, \ 1585 __VA_ARGS__) 1586 1587 /* 1588 * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI 1589 * analog PHY. The _inv variants are generated internally to cprman, 1590 * but we don't use them so they aren't hooked up. 1591 */ 1592 static const char *const bcm2835_clock_dsi0_parents[] = { 1593 "gnd", 1594 "xosc", 1595 "testdebug0", 1596 "testdebug1", 1597 "dsi0_ddr", 1598 "dsi0_ddr_inv", 1599 "dsi0_ddr2", 1600 "dsi0_ddr2_inv", 1601 "dsi0_byte", 1602 "dsi0_byte_inv", 1603 }; 1604 1605 static const char *const bcm2835_clock_dsi1_parents[] = { 1606 "gnd", 1607 "xosc", 1608 "testdebug0", 1609 "testdebug1", 1610 "dsi1_ddr", 1611 "dsi1_ddr_inv", 1612 "dsi1_ddr2", 1613 "dsi1_ddr2_inv", 1614 "dsi1_byte", 1615 "dsi1_byte_inv", 1616 }; 1617 1618 #define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \ 1619 s, \ 1620 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \ 1621 .parents = bcm2835_clock_dsi0_parents, \ 1622 __VA_ARGS__) 1623 1624 #define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \ 1625 s, \ 1626 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \ 1627 .parents = bcm2835_clock_dsi1_parents, \ 1628 __VA_ARGS__) 1629 1630 /* 1631 * the real definition of all the pll, pll_dividers and clocks 1632 * these make use of the above REGISTER_* macros 1633 */ 1634 static const struct bcm2835_clk_desc clk_desc_array[] = { 1635 /* the PLL + PLL dividers */ 1636 1637 /* 1638 * PLLA is the auxiliary PLL, used to drive the CCP2 1639 * (Compact Camera Port 2) transmitter clock. 1640 * 1641 * It is in the PX LDO power domain, which is on when the 1642 * AUDIO domain is on. 1643 */ 1644 [BCM2835_PLLA] = REGISTER_PLL( 1645 SOC_ALL, 1646 .name = "plla", 1647 .cm_ctrl_reg = CM_PLLA, 1648 .a2w_ctrl_reg = A2W_PLLA_CTRL, 1649 .frac_reg = A2W_PLLA_FRAC, 1650 .ana_reg_base = A2W_PLLA_ANA0, 1651 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE, 1652 .lock_mask = CM_LOCK_FLOCKA, 1653 1654 .ana = &bcm2835_ana_default, 1655 1656 .min_rate = 600000000u, 1657 .max_rate = 2400000000u, 1658 .max_fb_rate = BCM2835_MAX_FB_RATE), 1659 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV( 1660 SOC_ALL, 1661 .name = "plla_core", 1662 .source_pll = "plla", 1663 .cm_reg = CM_PLLA, 1664 .a2w_reg = A2W_PLLA_CORE, 1665 .load_mask = CM_PLLA_LOADCORE, 1666 .hold_mask = CM_PLLA_HOLDCORE, 1667 .fixed_divider = 1, 1668 .flags = CLK_SET_RATE_PARENT), 1669 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( 1670 SOC_ALL, 1671 .name = "plla_per", 1672 .source_pll = "plla", 1673 .cm_reg = CM_PLLA, 1674 .a2w_reg = A2W_PLLA_PER, 1675 .load_mask = CM_PLLA_LOADPER, 1676 .hold_mask = CM_PLLA_HOLDPER, 1677 .fixed_divider = 1, 1678 .flags = CLK_SET_RATE_PARENT), 1679 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( 1680 SOC_ALL, 1681 .name = "plla_dsi0", 1682 .source_pll = "plla", 1683 .cm_reg = CM_PLLA, 1684 .a2w_reg = A2W_PLLA_DSI0, 1685 .load_mask = CM_PLLA_LOADDSI0, 1686 .hold_mask = CM_PLLA_HOLDDSI0, 1687 .fixed_divider = 1), 1688 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( 1689 SOC_ALL, 1690 .name = "plla_ccp2", 1691 .source_pll = "plla", 1692 .cm_reg = CM_PLLA, 1693 .a2w_reg = A2W_PLLA_CCP2, 1694 .load_mask = CM_PLLA_LOADCCP2, 1695 .hold_mask = CM_PLLA_HOLDCCP2, 1696 .fixed_divider = 1, 1697 .flags = CLK_SET_RATE_PARENT), 1698 1699 /* PLLB is used for the ARM's clock. */ 1700 [BCM2835_PLLB] = REGISTER_PLL( 1701 SOC_ALL, 1702 .name = "pllb", 1703 .cm_ctrl_reg = CM_PLLB, 1704 .a2w_ctrl_reg = A2W_PLLB_CTRL, 1705 .frac_reg = A2W_PLLB_FRAC, 1706 .ana_reg_base = A2W_PLLB_ANA0, 1707 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE, 1708 .lock_mask = CM_LOCK_FLOCKB, 1709 1710 .ana = &bcm2835_ana_default, 1711 1712 .min_rate = 600000000u, 1713 .max_rate = 3000000000u, 1714 .max_fb_rate = BCM2835_MAX_FB_RATE, 1715 .flags = CLK_GET_RATE_NOCACHE), 1716 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV( 1717 SOC_ALL, 1718 .name = "pllb_arm", 1719 .source_pll = "pllb", 1720 .cm_reg = CM_PLLB, 1721 .a2w_reg = A2W_PLLB_ARM, 1722 .load_mask = CM_PLLB_LOADARM, 1723 .hold_mask = CM_PLLB_HOLDARM, 1724 .fixed_divider = 1, 1725 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE), 1726 1727 /* 1728 * PLLC is the core PLL, used to drive the core VPU clock. 1729 * 1730 * It is in the PX LDO power domain, which is on when the 1731 * AUDIO domain is on. 1732 */ 1733 [BCM2835_PLLC] = REGISTER_PLL( 1734 SOC_ALL, 1735 .name = "pllc", 1736 .cm_ctrl_reg = CM_PLLC, 1737 .a2w_ctrl_reg = A2W_PLLC_CTRL, 1738 .frac_reg = A2W_PLLC_FRAC, 1739 .ana_reg_base = A2W_PLLC_ANA0, 1740 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, 1741 .lock_mask = CM_LOCK_FLOCKC, 1742 1743 .ana = &bcm2835_ana_default, 1744 1745 .min_rate = 600000000u, 1746 .max_rate = 3000000000u, 1747 .max_fb_rate = BCM2835_MAX_FB_RATE), 1748 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV( 1749 SOC_ALL, 1750 .name = "pllc_core0", 1751 .source_pll = "pllc", 1752 .cm_reg = CM_PLLC, 1753 .a2w_reg = A2W_PLLC_CORE0, 1754 .load_mask = CM_PLLC_LOADCORE0, 1755 .hold_mask = CM_PLLC_HOLDCORE0, 1756 .fixed_divider = 1, 1757 .flags = CLK_SET_RATE_PARENT), 1758 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( 1759 SOC_ALL, 1760 .name = "pllc_core1", 1761 .source_pll = "pllc", 1762 .cm_reg = CM_PLLC, 1763 .a2w_reg = A2W_PLLC_CORE1, 1764 .load_mask = CM_PLLC_LOADCORE1, 1765 .hold_mask = CM_PLLC_HOLDCORE1, 1766 .fixed_divider = 1, 1767 .flags = CLK_SET_RATE_PARENT), 1768 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( 1769 SOC_ALL, 1770 .name = "pllc_core2", 1771 .source_pll = "pllc", 1772 .cm_reg = CM_PLLC, 1773 .a2w_reg = A2W_PLLC_CORE2, 1774 .load_mask = CM_PLLC_LOADCORE2, 1775 .hold_mask = CM_PLLC_HOLDCORE2, 1776 .fixed_divider = 1, 1777 .flags = CLK_SET_RATE_PARENT), 1778 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( 1779 SOC_ALL, 1780 .name = "pllc_per", 1781 .source_pll = "pllc", 1782 .cm_reg = CM_PLLC, 1783 .a2w_reg = A2W_PLLC_PER, 1784 .load_mask = CM_PLLC_LOADPER, 1785 .hold_mask = CM_PLLC_HOLDPER, 1786 .fixed_divider = 1, 1787 .flags = CLK_SET_RATE_PARENT), 1788 1789 /* 1790 * PLLD is the display PLL, used to drive DSI display panels. 1791 * 1792 * It is in the PX LDO power domain, which is on when the 1793 * AUDIO domain is on. 1794 */ 1795 [BCM2835_PLLD] = REGISTER_PLL( 1796 SOC_ALL, 1797 .name = "plld", 1798 .cm_ctrl_reg = CM_PLLD, 1799 .a2w_ctrl_reg = A2W_PLLD_CTRL, 1800 .frac_reg = A2W_PLLD_FRAC, 1801 .ana_reg_base = A2W_PLLD_ANA0, 1802 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE, 1803 .lock_mask = CM_LOCK_FLOCKD, 1804 1805 .ana = &bcm2835_ana_default, 1806 1807 .min_rate = 600000000u, 1808 .max_rate = 2400000000u, 1809 .max_fb_rate = BCM2835_MAX_FB_RATE), 1810 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV( 1811 SOC_ALL, 1812 .name = "plld_core", 1813 .source_pll = "plld", 1814 .cm_reg = CM_PLLD, 1815 .a2w_reg = A2W_PLLD_CORE, 1816 .load_mask = CM_PLLD_LOADCORE, 1817 .hold_mask = CM_PLLD_HOLDCORE, 1818 .fixed_divider = 1, 1819 .flags = CLK_SET_RATE_PARENT), 1820 /* 1821 * VPU firmware assumes that PLLD_PER isn't disabled by the ARM core. 1822 * Otherwise this could cause firmware lookups. That's why we mark 1823 * it as critical. 1824 */ 1825 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( 1826 SOC_ALL, 1827 .name = "plld_per", 1828 .source_pll = "plld", 1829 .cm_reg = CM_PLLD, 1830 .a2w_reg = A2W_PLLD_PER, 1831 .load_mask = CM_PLLD_LOADPER, 1832 .hold_mask = CM_PLLD_HOLDPER, 1833 .fixed_divider = 1, 1834 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 1835 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( 1836 SOC_ALL, 1837 .name = "plld_dsi0", 1838 .source_pll = "plld", 1839 .cm_reg = CM_PLLD, 1840 .a2w_reg = A2W_PLLD_DSI0, 1841 .load_mask = CM_PLLD_LOADDSI0, 1842 .hold_mask = CM_PLLD_HOLDDSI0, 1843 .fixed_divider = 1), 1844 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( 1845 SOC_ALL, 1846 .name = "plld_dsi1", 1847 .source_pll = "plld", 1848 .cm_reg = CM_PLLD, 1849 .a2w_reg = A2W_PLLD_DSI1, 1850 .load_mask = CM_PLLD_LOADDSI1, 1851 .hold_mask = CM_PLLD_HOLDDSI1, 1852 .fixed_divider = 1), 1853 1854 /* 1855 * PLLH is used to supply the pixel clock or the AUX clock for the 1856 * TV encoder. 1857 * 1858 * It is in the HDMI power domain. 1859 */ 1860 [BCM2835_PLLH] = REGISTER_PLL( 1861 SOC_BCM2835, 1862 "pllh", 1863 .cm_ctrl_reg = CM_PLLH, 1864 .a2w_ctrl_reg = A2W_PLLH_CTRL, 1865 .frac_reg = A2W_PLLH_FRAC, 1866 .ana_reg_base = A2W_PLLH_ANA0, 1867 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, 1868 .lock_mask = CM_LOCK_FLOCKH, 1869 1870 .ana = &bcm2835_ana_pllh, 1871 1872 .min_rate = 600000000u, 1873 .max_rate = 3000000000u, 1874 .max_fb_rate = BCM2835_MAX_FB_RATE), 1875 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV( 1876 SOC_BCM2835, 1877 .name = "pllh_rcal", 1878 .source_pll = "pllh", 1879 .cm_reg = CM_PLLH, 1880 .a2w_reg = A2W_PLLH_RCAL, 1881 .load_mask = CM_PLLH_LOADRCAL, 1882 .hold_mask = 0, 1883 .fixed_divider = 10, 1884 .flags = CLK_SET_RATE_PARENT), 1885 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( 1886 SOC_BCM2835, 1887 .name = "pllh_aux", 1888 .source_pll = "pllh", 1889 .cm_reg = CM_PLLH, 1890 .a2w_reg = A2W_PLLH_AUX, 1891 .load_mask = CM_PLLH_LOADAUX, 1892 .hold_mask = 0, 1893 .fixed_divider = 1, 1894 .flags = CLK_SET_RATE_PARENT), 1895 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( 1896 SOC_BCM2835, 1897 .name = "pllh_pix", 1898 .source_pll = "pllh", 1899 .cm_reg = CM_PLLH, 1900 .a2w_reg = A2W_PLLH_PIX, 1901 .load_mask = CM_PLLH_LOADPIX, 1902 .hold_mask = 0, 1903 .fixed_divider = 10, 1904 .flags = CLK_SET_RATE_PARENT), 1905 1906 /* the clocks */ 1907 1908 /* clocks with oscillator parent mux */ 1909 1910 /* One Time Programmable Memory clock. Maximum 10Mhz. */ 1911 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK( 1912 SOC_ALL, 1913 .name = "otp", 1914 .ctl_reg = CM_OTPCTL, 1915 .div_reg = CM_OTPDIV, 1916 .int_bits = 4, 1917 .frac_bits = 0, 1918 .tcnt_mux = 6), 1919 /* 1920 * Used for a 1Mhz clock for the system clocksource, and also used 1921 * bythe watchdog timer and the camera pulse generator. 1922 */ 1923 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK( 1924 SOC_ALL, 1925 .name = "timer", 1926 .ctl_reg = CM_TIMERCTL, 1927 .div_reg = CM_TIMERDIV, 1928 .int_bits = 6, 1929 .frac_bits = 12), 1930 /* 1931 * Clock for the temperature sensor. 1932 * Generally run at 2Mhz, max 5Mhz. 1933 */ 1934 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK( 1935 SOC_ALL, 1936 .name = "tsens", 1937 .ctl_reg = CM_TSENSCTL, 1938 .div_reg = CM_TSENSDIV, 1939 .int_bits = 5, 1940 .frac_bits = 0), 1941 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK( 1942 SOC_ALL, 1943 .name = "tec", 1944 .ctl_reg = CM_TECCTL, 1945 .div_reg = CM_TECDIV, 1946 .int_bits = 6, 1947 .frac_bits = 0), 1948 1949 /* clocks with vpu parent mux */ 1950 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( 1951 SOC_ALL, 1952 .name = "h264", 1953 .ctl_reg = CM_H264CTL, 1954 .div_reg = CM_H264DIV, 1955 .int_bits = 4, 1956 .frac_bits = 8, 1957 .tcnt_mux = 1), 1958 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK( 1959 SOC_ALL, 1960 .name = "isp", 1961 .ctl_reg = CM_ISPCTL, 1962 .div_reg = CM_ISPDIV, 1963 .int_bits = 4, 1964 .frac_bits = 8, 1965 .tcnt_mux = 2), 1966 1967 /* 1968 * Secondary SDRAM clock. Used for low-voltage modes when the PLL 1969 * in the SDRAM controller can't be used. 1970 */ 1971 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK( 1972 SOC_ALL, 1973 .name = "sdram", 1974 .ctl_reg = CM_SDCCTL, 1975 .div_reg = CM_SDCDIV, 1976 .int_bits = 6, 1977 .frac_bits = 0, 1978 .tcnt_mux = 3), 1979 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( 1980 SOC_ALL, 1981 .name = "v3d", 1982 .ctl_reg = CM_V3DCTL, 1983 .div_reg = CM_V3DDIV, 1984 .int_bits = 4, 1985 .frac_bits = 8, 1986 .tcnt_mux = 4), 1987 /* 1988 * VPU clock. This doesn't have an enable bit, since it drives 1989 * the bus for everything else, and is special so it doesn't need 1990 * to be gated for rate changes. It is also known as "clk_audio" 1991 * in various hardware documentation. 1992 */ 1993 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK( 1994 SOC_ALL, 1995 .name = "vpu", 1996 .ctl_reg = CM_VPUCTL, 1997 .div_reg = CM_VPUDIV, 1998 .int_bits = 12, 1999 .frac_bits = 8, 2000 .flags = CLK_IS_CRITICAL, 2001 .is_vpu_clock = true, 2002 .tcnt_mux = 5), 2003 2004 /* clocks with per parent mux */ 2005 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK( 2006 SOC_ALL, 2007 .name = "aveo", 2008 .ctl_reg = CM_AVEOCTL, 2009 .div_reg = CM_AVEODIV, 2010 .int_bits = 4, 2011 .frac_bits = 0, 2012 .tcnt_mux = 38), 2013 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK( 2014 SOC_ALL, 2015 .name = "cam0", 2016 .ctl_reg = CM_CAM0CTL, 2017 .div_reg = CM_CAM0DIV, 2018 .int_bits = 4, 2019 .frac_bits = 8, 2020 .tcnt_mux = 14), 2021 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK( 2022 SOC_ALL, 2023 .name = "cam1", 2024 .ctl_reg = CM_CAM1CTL, 2025 .div_reg = CM_CAM1DIV, 2026 .int_bits = 4, 2027 .frac_bits = 8, 2028 .tcnt_mux = 15), 2029 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK( 2030 SOC_ALL, 2031 .name = "dft", 2032 .ctl_reg = CM_DFTCTL, 2033 .div_reg = CM_DFTDIV, 2034 .int_bits = 5, 2035 .frac_bits = 0), 2036 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK( 2037 SOC_ALL, 2038 .name = "dpi", 2039 .ctl_reg = CM_DPICTL, 2040 .div_reg = CM_DPIDIV, 2041 .int_bits = 4, 2042 .frac_bits = 8, 2043 .tcnt_mux = 17), 2044 2045 /* Arasan EMMC clock */ 2046 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( 2047 SOC_ALL, 2048 .name = "emmc", 2049 .ctl_reg = CM_EMMCCTL, 2050 .div_reg = CM_EMMCDIV, 2051 .int_bits = 4, 2052 .frac_bits = 8, 2053 .tcnt_mux = 39), 2054 2055 /* EMMC2 clock (only available for BCM2711) */ 2056 [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK( 2057 SOC_BCM2711, 2058 .name = "emmc2", 2059 .ctl_reg = CM_EMMC2CTL, 2060 .div_reg = CM_EMMC2DIV, 2061 .int_bits = 4, 2062 .frac_bits = 8, 2063 .tcnt_mux = 42), 2064 2065 /* General purpose (GPIO) clocks */ 2066 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( 2067 SOC_ALL, 2068 .name = "gp0", 2069 .ctl_reg = CM_GP0CTL, 2070 .div_reg = CM_GP0DIV, 2071 .int_bits = 12, 2072 .frac_bits = 12, 2073 .is_mash_clock = true, 2074 .tcnt_mux = 20), 2075 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK( 2076 SOC_ALL, 2077 .name = "gp1", 2078 .ctl_reg = CM_GP1CTL, 2079 .div_reg = CM_GP1DIV, 2080 .int_bits = 12, 2081 .frac_bits = 12, 2082 .flags = CLK_IS_CRITICAL, 2083 .is_mash_clock = true, 2084 .tcnt_mux = 21), 2085 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK( 2086 SOC_ALL, 2087 .name = "gp2", 2088 .ctl_reg = CM_GP2CTL, 2089 .div_reg = CM_GP2DIV, 2090 .int_bits = 12, 2091 .frac_bits = 12, 2092 .flags = CLK_IS_CRITICAL), 2093 2094 /* HDMI state machine */ 2095 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( 2096 SOC_ALL, 2097 .name = "hsm", 2098 .ctl_reg = CM_HSMCTL, 2099 .div_reg = CM_HSMDIV, 2100 .int_bits = 4, 2101 .frac_bits = 8, 2102 .tcnt_mux = 22), 2103 [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK( 2104 SOC_ALL, 2105 .name = "pcm", 2106 .ctl_reg = CM_PCMCTL, 2107 .div_reg = CM_PCMDIV, 2108 .int_bits = 12, 2109 .frac_bits = 12, 2110 .is_mash_clock = true, 2111 .low_jitter = true, 2112 .tcnt_mux = 23), 2113 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK( 2114 SOC_ALL, 2115 .name = "pwm", 2116 .ctl_reg = CM_PWMCTL, 2117 .div_reg = CM_PWMDIV, 2118 .int_bits = 12, 2119 .frac_bits = 12, 2120 .is_mash_clock = true, 2121 .tcnt_mux = 24), 2122 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK( 2123 SOC_ALL, 2124 .name = "slim", 2125 .ctl_reg = CM_SLIMCTL, 2126 .div_reg = CM_SLIMDIV, 2127 .int_bits = 12, 2128 .frac_bits = 12, 2129 .is_mash_clock = true, 2130 .tcnt_mux = 25), 2131 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK( 2132 SOC_ALL, 2133 .name = "smi", 2134 .ctl_reg = CM_SMICTL, 2135 .div_reg = CM_SMIDIV, 2136 .int_bits = 4, 2137 .frac_bits = 8, 2138 .tcnt_mux = 27), 2139 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK( 2140 SOC_ALL, 2141 .name = "uart", 2142 .ctl_reg = CM_UARTCTL, 2143 .div_reg = CM_UARTDIV, 2144 .int_bits = 10, 2145 .frac_bits = 12, 2146 .tcnt_mux = 28), 2147 2148 /* TV encoder clock. Only operating frequency is 108Mhz. */ 2149 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( 2150 SOC_ALL, 2151 .name = "vec", 2152 .ctl_reg = CM_VECCTL, 2153 .div_reg = CM_VECDIV, 2154 .int_bits = 4, 2155 .frac_bits = 0, 2156 /* 2157 * Allow rate change propagation only on PLLH_AUX which is 2158 * assigned index 7 in the parent array. 2159 */ 2160 .set_rate_parent = BIT(7), 2161 .tcnt_mux = 29), 2162 2163 /* dsi clocks */ 2164 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( 2165 SOC_ALL, 2166 .name = "dsi0e", 2167 .ctl_reg = CM_DSI0ECTL, 2168 .div_reg = CM_DSI0EDIV, 2169 .int_bits = 4, 2170 .frac_bits = 8, 2171 .tcnt_mux = 18), 2172 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK( 2173 SOC_ALL, 2174 .name = "dsi1e", 2175 .ctl_reg = CM_DSI1ECTL, 2176 .div_reg = CM_DSI1EDIV, 2177 .int_bits = 4, 2178 .frac_bits = 8, 2179 .tcnt_mux = 19), 2180 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK( 2181 SOC_ALL, 2182 .name = "dsi0p", 2183 .ctl_reg = CM_DSI0PCTL, 2184 .div_reg = CM_DSI0PDIV, 2185 .int_bits = 0, 2186 .frac_bits = 0, 2187 .tcnt_mux = 12), 2188 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK( 2189 SOC_ALL, 2190 .name = "dsi1p", 2191 .ctl_reg = CM_DSI1PCTL, 2192 .div_reg = CM_DSI1PDIV, 2193 .int_bits = 0, 2194 .frac_bits = 0, 2195 .tcnt_mux = 13), 2196 2197 /* the gates */ 2198 2199 /* 2200 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if 2201 * you have the debug bit set in the power manager, which we 2202 * don't bother exposing) are individual gates off of the 2203 * non-stop vpu clock. 2204 */ 2205 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE( 2206 SOC_ALL, 2207 .name = "peri_image", 2208 .parent = "vpu", 2209 .ctl_reg = CM_PERIICTL), 2210 }; 2211 2212 /* 2213 * Permanently take a reference on the parent of the SDRAM clock. 2214 * 2215 * While the SDRAM is being driven by its dedicated PLL most of the 2216 * time, there is a little loop running in the firmware that 2217 * periodically switches the SDRAM to using our CM clock to do PVT 2218 * recalibration, with the assumption that the previously configured 2219 * SDRAM parent is still enabled and running. 2220 */ 2221 static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) 2222 { 2223 struct clk *parent = clk_get_parent(sdc); 2224 2225 if (IS_ERR(parent)) 2226 return PTR_ERR(parent); 2227 2228 return clk_prepare_enable(parent); 2229 } 2230 2231 static int bcm2835_clk_probe(struct platform_device *pdev) 2232 { 2233 struct device *dev = &pdev->dev; 2234 struct clk_hw **hws; 2235 struct bcm2835_cprman *cprman; 2236 const struct bcm2835_clk_desc *desc; 2237 const size_t asize = ARRAY_SIZE(clk_desc_array); 2238 const struct cprman_plat_data *pdata; 2239 size_t i; 2240 int ret; 2241 2242 pdata = of_device_get_match_data(&pdev->dev); 2243 if (!pdata) 2244 return -ENODEV; 2245 2246 cprman = devm_kzalloc(dev, 2247 struct_size(cprman, onecell.hws, asize), 2248 GFP_KERNEL); 2249 if (!cprman) 2250 return -ENOMEM; 2251 2252 spin_lock_init(&cprman->regs_lock); 2253 cprman->dev = dev; 2254 cprman->regs = devm_platform_ioremap_resource(pdev, 0); 2255 if (IS_ERR(cprman->regs)) 2256 return PTR_ERR(cprman->regs); 2257 2258 memcpy(cprman->real_parent_names, cprman_parent_names, 2259 sizeof(cprman_parent_names)); 2260 of_clk_parent_fill(dev->of_node, cprman->real_parent_names, 2261 ARRAY_SIZE(cprman_parent_names)); 2262 2263 /* 2264 * Make sure the external oscillator has been registered. 2265 * 2266 * The other (DSI) clocks are not present on older device 2267 * trees, which we still need to support for backwards 2268 * compatibility. 2269 */ 2270 if (!cprman->real_parent_names[0]) 2271 return -ENODEV; 2272 2273 platform_set_drvdata(pdev, cprman); 2274 2275 cprman->onecell.num = asize; 2276 cprman->soc = pdata->soc; 2277 hws = cprman->onecell.hws; 2278 2279 for (i = 0; i < asize; i++) { 2280 desc = &clk_desc_array[i]; 2281 if (desc->clk_register && desc->data && 2282 (desc->supported & pdata->soc)) { 2283 hws[i] = desc->clk_register(cprman, desc->data); 2284 } 2285 } 2286 2287 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk); 2288 if (ret) 2289 return ret; 2290 2291 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 2292 &cprman->onecell); 2293 } 2294 2295 static const struct cprman_plat_data cprman_bcm2835_plat_data = { 2296 .soc = SOC_BCM2835, 2297 }; 2298 2299 static const struct cprman_plat_data cprman_bcm2711_plat_data = { 2300 .soc = SOC_BCM2711, 2301 }; 2302 2303 static const struct of_device_id bcm2835_clk_of_match[] = { 2304 { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data }, 2305 { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data }, 2306 {} 2307 }; 2308 MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); 2309 2310 static struct platform_driver bcm2835_clk_driver = { 2311 .driver = { 2312 .name = "bcm2835-clk", 2313 .of_match_table = bcm2835_clk_of_match, 2314 }, 2315 .probe = bcm2835_clk_probe, 2316 }; 2317 2318 builtin_platform_driver(bcm2835_clk_driver); 2319 2320 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 2321 MODULE_DESCRIPTION("BCM2835 clock driver"); 2322 MODULE_LICENSE("GPL"); 2323