1 /* 2 * Copyright (C) 2010,2015 Broadcom 3 * Copyright (C) 2012 Stephen Warren 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 /** 18 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain) 19 * 20 * The clock tree on the 2835 has several levels. There's a root 21 * oscillator running at 19.2Mhz. After the oscillator there are 5 22 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays", 23 * and "HDMI displays". Those 5 PLLs each can divide their output to 24 * produce up to 4 channels. Finally, there is the level of clocks to 25 * be consumed by other hardware components (like "H264" or "HDMI 26 * state machine"), which divide off of some subset of the PLL 27 * channels. 28 * 29 * All of the clocks in the tree are exposed in the DT, because the DT 30 * may want to make assignments of the final layer of clocks to the 31 * PLL channels, and some components of the hardware will actually 32 * skip layers of the tree (for example, the pixel clock comes 33 * directly from the PLLH PIX channel without using a CM_*CTL clock 34 * generator). 35 */ 36 37 #include <linux/clk-provider.h> 38 #include <linux/clkdev.h> 39 #include <linux/clk/bcm2835.h> 40 #include <linux/debugfs.h> 41 #include <linux/module.h> 42 #include <linux/of.h> 43 #include <linux/platform_device.h> 44 #include <linux/slab.h> 45 #include <dt-bindings/clock/bcm2835.h> 46 47 #define CM_PASSWORD 0x5a000000 48 49 #define CM_GNRICCTL 0x000 50 #define CM_GNRICDIV 0x004 51 # define CM_DIV_FRAC_BITS 12 52 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0) 53 54 #define CM_VPUCTL 0x008 55 #define CM_VPUDIV 0x00c 56 #define CM_SYSCTL 0x010 57 #define CM_SYSDIV 0x014 58 #define CM_PERIACTL 0x018 59 #define CM_PERIADIV 0x01c 60 #define CM_PERIICTL 0x020 61 #define CM_PERIIDIV 0x024 62 #define CM_H264CTL 0x028 63 #define CM_H264DIV 0x02c 64 #define CM_ISPCTL 0x030 65 #define CM_ISPDIV 0x034 66 #define CM_V3DCTL 0x038 67 #define CM_V3DDIV 0x03c 68 #define CM_CAM0CTL 0x040 69 #define CM_CAM0DIV 0x044 70 #define CM_CAM1CTL 0x048 71 #define CM_CAM1DIV 0x04c 72 #define CM_CCP2CTL 0x050 73 #define CM_CCP2DIV 0x054 74 #define CM_DSI0ECTL 0x058 75 #define CM_DSI0EDIV 0x05c 76 #define CM_DSI0PCTL 0x060 77 #define CM_DSI0PDIV 0x064 78 #define CM_DPICTL 0x068 79 #define CM_DPIDIV 0x06c 80 #define CM_GP0CTL 0x070 81 #define CM_GP0DIV 0x074 82 #define CM_GP1CTL 0x078 83 #define CM_GP1DIV 0x07c 84 #define CM_GP2CTL 0x080 85 #define CM_GP2DIV 0x084 86 #define CM_HSMCTL 0x088 87 #define CM_HSMDIV 0x08c 88 #define CM_OTPCTL 0x090 89 #define CM_OTPDIV 0x094 90 #define CM_PCMCTL 0x098 91 #define CM_PCMDIV 0x09c 92 #define CM_PWMCTL 0x0a0 93 #define CM_PWMDIV 0x0a4 94 #define CM_SLIMCTL 0x0a8 95 #define CM_SLIMDIV 0x0ac 96 #define CM_SMICTL 0x0b0 97 #define CM_SMIDIV 0x0b4 98 /* no definition for 0x0b8 and 0x0bc */ 99 #define CM_TCNTCTL 0x0c0 100 #define CM_TCNTDIV 0x0c4 101 #define CM_TECCTL 0x0c8 102 #define CM_TECDIV 0x0cc 103 #define CM_TD0CTL 0x0d0 104 #define CM_TD0DIV 0x0d4 105 #define CM_TD1CTL 0x0d8 106 #define CM_TD1DIV 0x0dc 107 #define CM_TSENSCTL 0x0e0 108 #define CM_TSENSDIV 0x0e4 109 #define CM_TIMERCTL 0x0e8 110 #define CM_TIMERDIV 0x0ec 111 #define CM_UARTCTL 0x0f0 112 #define CM_UARTDIV 0x0f4 113 #define CM_VECCTL 0x0f8 114 #define CM_VECDIV 0x0fc 115 #define CM_PULSECTL 0x190 116 #define CM_PULSEDIV 0x194 117 #define CM_SDCCTL 0x1a8 118 #define CM_SDCDIV 0x1ac 119 #define CM_ARMCTL 0x1b0 120 #define CM_AVEOCTL 0x1b8 121 #define CM_AVEODIV 0x1bc 122 #define CM_EMMCCTL 0x1c0 123 #define CM_EMMCDIV 0x1c4 124 125 /* General bits for the CM_*CTL regs */ 126 # define CM_ENABLE BIT(4) 127 # define CM_KILL BIT(5) 128 # define CM_GATE_BIT 6 129 # define CM_GATE BIT(CM_GATE_BIT) 130 # define CM_BUSY BIT(7) 131 # define CM_BUSYD BIT(8) 132 # define CM_FRAC BIT(9) 133 # define CM_SRC_SHIFT 0 134 # define CM_SRC_BITS 4 135 # define CM_SRC_MASK 0xf 136 # define CM_SRC_GND 0 137 # define CM_SRC_OSC 1 138 # define CM_SRC_TESTDEBUG0 2 139 # define CM_SRC_TESTDEBUG1 3 140 # define CM_SRC_PLLA_CORE 4 141 # define CM_SRC_PLLA_PER 4 142 # define CM_SRC_PLLC_CORE0 5 143 # define CM_SRC_PLLC_PER 5 144 # define CM_SRC_PLLC_CORE1 8 145 # define CM_SRC_PLLD_CORE 6 146 # define CM_SRC_PLLD_PER 6 147 # define CM_SRC_PLLH_AUX 7 148 # define CM_SRC_PLLC_CORE1 8 149 # define CM_SRC_PLLC_CORE2 9 150 151 #define CM_OSCCOUNT 0x100 152 153 #define CM_PLLA 0x104 154 # define CM_PLL_ANARST BIT(8) 155 # define CM_PLLA_HOLDPER BIT(7) 156 # define CM_PLLA_LOADPER BIT(6) 157 # define CM_PLLA_HOLDCORE BIT(5) 158 # define CM_PLLA_LOADCORE BIT(4) 159 # define CM_PLLA_HOLDCCP2 BIT(3) 160 # define CM_PLLA_LOADCCP2 BIT(2) 161 # define CM_PLLA_HOLDDSI0 BIT(1) 162 # define CM_PLLA_LOADDSI0 BIT(0) 163 164 #define CM_PLLC 0x108 165 # define CM_PLLC_HOLDPER BIT(7) 166 # define CM_PLLC_LOADPER BIT(6) 167 # define CM_PLLC_HOLDCORE2 BIT(5) 168 # define CM_PLLC_LOADCORE2 BIT(4) 169 # define CM_PLLC_HOLDCORE1 BIT(3) 170 # define CM_PLLC_LOADCORE1 BIT(2) 171 # define CM_PLLC_HOLDCORE0 BIT(1) 172 # define CM_PLLC_LOADCORE0 BIT(0) 173 174 #define CM_PLLD 0x10c 175 # define CM_PLLD_HOLDPER BIT(7) 176 # define CM_PLLD_LOADPER BIT(6) 177 # define CM_PLLD_HOLDCORE BIT(5) 178 # define CM_PLLD_LOADCORE BIT(4) 179 # define CM_PLLD_HOLDDSI1 BIT(3) 180 # define CM_PLLD_LOADDSI1 BIT(2) 181 # define CM_PLLD_HOLDDSI0 BIT(1) 182 # define CM_PLLD_LOADDSI0 BIT(0) 183 184 #define CM_PLLH 0x110 185 # define CM_PLLH_LOADRCAL BIT(2) 186 # define CM_PLLH_LOADAUX BIT(1) 187 # define CM_PLLH_LOADPIX BIT(0) 188 189 #define CM_LOCK 0x114 190 # define CM_LOCK_FLOCKH BIT(12) 191 # define CM_LOCK_FLOCKD BIT(11) 192 # define CM_LOCK_FLOCKC BIT(10) 193 # define CM_LOCK_FLOCKB BIT(9) 194 # define CM_LOCK_FLOCKA BIT(8) 195 196 #define CM_EVENT 0x118 197 #define CM_DSI1ECTL 0x158 198 #define CM_DSI1EDIV 0x15c 199 #define CM_DSI1PCTL 0x160 200 #define CM_DSI1PDIV 0x164 201 #define CM_DFTCTL 0x168 202 #define CM_DFTDIV 0x16c 203 204 #define CM_PLLB 0x170 205 # define CM_PLLB_HOLDARM BIT(1) 206 # define CM_PLLB_LOADARM BIT(0) 207 208 #define A2W_PLLA_CTRL 0x1100 209 #define A2W_PLLC_CTRL 0x1120 210 #define A2W_PLLD_CTRL 0x1140 211 #define A2W_PLLH_CTRL 0x1160 212 #define A2W_PLLB_CTRL 0x11e0 213 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17) 214 # define A2W_PLL_CTRL_PWRDN BIT(16) 215 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000 216 # define A2W_PLL_CTRL_PDIV_SHIFT 12 217 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff 218 # define A2W_PLL_CTRL_NDIV_SHIFT 0 219 220 #define A2W_PLLA_ANA0 0x1010 221 #define A2W_PLLC_ANA0 0x1030 222 #define A2W_PLLD_ANA0 0x1050 223 #define A2W_PLLH_ANA0 0x1070 224 #define A2W_PLLB_ANA0 0x10f0 225 226 #define A2W_PLL_KA_SHIFT 7 227 #define A2W_PLL_KA_MASK GENMASK(9, 7) 228 #define A2W_PLL_KI_SHIFT 19 229 #define A2W_PLL_KI_MASK GENMASK(21, 19) 230 #define A2W_PLL_KP_SHIFT 15 231 #define A2W_PLL_KP_MASK GENMASK(18, 15) 232 233 #define A2W_PLLH_KA_SHIFT 19 234 #define A2W_PLLH_KA_MASK GENMASK(21, 19) 235 #define A2W_PLLH_KI_LOW_SHIFT 22 236 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22) 237 #define A2W_PLLH_KI_HIGH_SHIFT 0 238 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0) 239 #define A2W_PLLH_KP_SHIFT 1 240 #define A2W_PLLH_KP_MASK GENMASK(4, 1) 241 242 #define A2W_XOSC_CTRL 0x1190 243 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7) 244 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6) 245 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5) 246 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4) 247 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3) 248 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2) 249 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1) 250 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0) 251 252 #define A2W_PLLA_FRAC 0x1200 253 #define A2W_PLLC_FRAC 0x1220 254 #define A2W_PLLD_FRAC 0x1240 255 #define A2W_PLLH_FRAC 0x1260 256 #define A2W_PLLB_FRAC 0x12e0 257 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1) 258 # define A2W_PLL_FRAC_BITS 20 259 260 #define A2W_PLL_CHANNEL_DISABLE BIT(8) 261 #define A2W_PLL_DIV_BITS 8 262 #define A2W_PLL_DIV_SHIFT 0 263 264 #define A2W_PLLA_DSI0 0x1300 265 #define A2W_PLLA_CORE 0x1400 266 #define A2W_PLLA_PER 0x1500 267 #define A2W_PLLA_CCP2 0x1600 268 269 #define A2W_PLLC_CORE2 0x1320 270 #define A2W_PLLC_CORE1 0x1420 271 #define A2W_PLLC_PER 0x1520 272 #define A2W_PLLC_CORE0 0x1620 273 274 #define A2W_PLLD_DSI0 0x1340 275 #define A2W_PLLD_CORE 0x1440 276 #define A2W_PLLD_PER 0x1540 277 #define A2W_PLLD_DSI1 0x1640 278 279 #define A2W_PLLH_AUX 0x1360 280 #define A2W_PLLH_RCAL 0x1460 281 #define A2W_PLLH_PIX 0x1560 282 #define A2W_PLLH_STS 0x1660 283 284 #define A2W_PLLH_CTRLR 0x1960 285 #define A2W_PLLH_FRACR 0x1a60 286 #define A2W_PLLH_AUXR 0x1b60 287 #define A2W_PLLH_RCALR 0x1c60 288 #define A2W_PLLH_PIXR 0x1d60 289 #define A2W_PLLH_STSR 0x1e60 290 291 #define A2W_PLLB_ARM 0x13e0 292 #define A2W_PLLB_SP0 0x14e0 293 #define A2W_PLLB_SP1 0x15e0 294 #define A2W_PLLB_SP2 0x16e0 295 296 #define LOCK_TIMEOUT_NS 100000000 297 #define BCM2835_MAX_FB_RATE 1750000000u 298 299 struct bcm2835_cprman { 300 struct device *dev; 301 void __iomem *regs; 302 spinlock_t regs_lock; /* spinlock for all clocks */ 303 const char *osc_name; 304 305 struct clk_onecell_data onecell; 306 struct clk *clks[]; 307 }; 308 309 static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) 310 { 311 writel(CM_PASSWORD | val, cprman->regs + reg); 312 } 313 314 static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg) 315 { 316 return readl(cprman->regs + reg); 317 } 318 319 static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, 320 struct debugfs_reg32 *regs, size_t nregs, 321 struct dentry *dentry) 322 { 323 struct dentry *regdump; 324 struct debugfs_regset32 *regset; 325 326 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL); 327 if (!regset) 328 return -ENOMEM; 329 330 regset->regs = regs; 331 regset->nregs = nregs; 332 regset->base = cprman->regs + base; 333 334 regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry, 335 regset); 336 337 return regdump ? 0 : -ENOMEM; 338 } 339 340 /* 341 * These are fixed clocks. They're probably not all root clocks and it may 342 * be possible to turn them on and off but until this is mapped out better 343 * it's the only way they can be used. 344 */ 345 void __init bcm2835_init_clocks(void) 346 { 347 struct clk *clk; 348 int ret; 349 350 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 126000000); 351 if (IS_ERR(clk)) 352 pr_err("apb_pclk not registered\n"); 353 354 clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, 0, 3000000); 355 if (IS_ERR(clk)) 356 pr_err("uart0_pclk not registered\n"); 357 ret = clk_register_clkdev(clk, NULL, "20201000.uart"); 358 if (ret) 359 pr_err("uart0_pclk alias not registered\n"); 360 361 clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, 0, 125000000); 362 if (IS_ERR(clk)) 363 pr_err("uart1_pclk not registered\n"); 364 ret = clk_register_clkdev(clk, NULL, "20215000.uart"); 365 if (ret) 366 pr_err("uart1_pclk alias not registered\n"); 367 } 368 369 struct bcm2835_pll_data { 370 const char *name; 371 u32 cm_ctrl_reg; 372 u32 a2w_ctrl_reg; 373 u32 frac_reg; 374 u32 ana_reg_base; 375 u32 reference_enable_mask; 376 /* Bit in CM_LOCK to indicate when the PLL has locked. */ 377 u32 lock_mask; 378 379 const struct bcm2835_pll_ana_bits *ana; 380 381 unsigned long min_rate; 382 unsigned long max_rate; 383 /* 384 * Highest rate for the VCO before we have to use the 385 * pre-divide-by-2. 386 */ 387 unsigned long max_fb_rate; 388 }; 389 390 struct bcm2835_pll_ana_bits { 391 u32 mask0; 392 u32 set0; 393 u32 mask1; 394 u32 set1; 395 u32 mask3; 396 u32 set3; 397 u32 fb_prediv_mask; 398 }; 399 400 static const struct bcm2835_pll_ana_bits bcm2835_ana_default = { 401 .mask0 = 0, 402 .set0 = 0, 403 .mask1 = (u32)~(A2W_PLL_KI_MASK | A2W_PLL_KP_MASK), 404 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT), 405 .mask3 = (u32)~A2W_PLL_KA_MASK, 406 .set3 = (2 << A2W_PLL_KA_SHIFT), 407 .fb_prediv_mask = BIT(14), 408 }; 409 410 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = { 411 .mask0 = (u32)~(A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK), 412 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT), 413 .mask1 = (u32)~(A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK), 414 .set1 = (6 << A2W_PLLH_KP_SHIFT), 415 .mask3 = 0, 416 .set3 = 0, 417 .fb_prediv_mask = BIT(11), 418 }; 419 420 struct bcm2835_pll_divider_data { 421 const char *name; 422 const char *source_pll; 423 424 u32 cm_reg; 425 u32 a2w_reg; 426 427 u32 load_mask; 428 u32 hold_mask; 429 u32 fixed_divider; 430 }; 431 432 struct bcm2835_clock_data { 433 const char *name; 434 435 const char *const *parents; 436 int num_mux_parents; 437 438 u32 ctl_reg; 439 u32 div_reg; 440 441 /* Number of integer bits in the divider */ 442 u32 int_bits; 443 /* Number of fractional bits in the divider */ 444 u32 frac_bits; 445 446 bool is_vpu_clock; 447 bool is_mash_clock; 448 }; 449 450 struct bcm2835_gate_data { 451 const char *name; 452 const char *parent; 453 454 u32 ctl_reg; 455 }; 456 457 struct bcm2835_pll { 458 struct clk_hw hw; 459 struct bcm2835_cprman *cprman; 460 const struct bcm2835_pll_data *data; 461 }; 462 463 static int bcm2835_pll_is_on(struct clk_hw *hw) 464 { 465 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 466 struct bcm2835_cprman *cprman = pll->cprman; 467 const struct bcm2835_pll_data *data = pll->data; 468 469 return cprman_read(cprman, data->a2w_ctrl_reg) & 470 A2W_PLL_CTRL_PRST_DISABLE; 471 } 472 473 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate, 474 unsigned long parent_rate, 475 u32 *ndiv, u32 *fdiv) 476 { 477 u64 div; 478 479 div = (u64)rate << A2W_PLL_FRAC_BITS; 480 do_div(div, parent_rate); 481 482 *ndiv = div >> A2W_PLL_FRAC_BITS; 483 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); 484 } 485 486 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate, 487 u32 ndiv, u32 fdiv, u32 pdiv) 488 { 489 u64 rate; 490 491 if (pdiv == 0) 492 return 0; 493 494 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); 495 do_div(rate, pdiv); 496 return rate >> A2W_PLL_FRAC_BITS; 497 } 498 499 static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate, 500 unsigned long *parent_rate) 501 { 502 u32 ndiv, fdiv; 503 504 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); 505 506 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); 507 } 508 509 static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw, 510 unsigned long parent_rate) 511 { 512 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 513 struct bcm2835_cprman *cprman = pll->cprman; 514 const struct bcm2835_pll_data *data = pll->data; 515 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); 516 u32 ndiv, pdiv, fdiv; 517 bool using_prediv; 518 519 if (parent_rate == 0) 520 return 0; 521 522 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; 523 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT; 524 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT; 525 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & 526 data->ana->fb_prediv_mask; 527 528 if (using_prediv) 529 ndiv *= 2; 530 531 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv); 532 } 533 534 static void bcm2835_pll_off(struct clk_hw *hw) 535 { 536 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 537 struct bcm2835_cprman *cprman = pll->cprman; 538 const struct bcm2835_pll_data *data = pll->data; 539 540 spin_lock(&cprman->regs_lock); 541 cprman_write(cprman, data->cm_ctrl_reg, 542 cprman_read(cprman, data->cm_ctrl_reg) | 543 CM_PLL_ANARST); 544 cprman_write(cprman, data->a2w_ctrl_reg, 545 cprman_read(cprman, data->a2w_ctrl_reg) | 546 A2W_PLL_CTRL_PWRDN); 547 spin_unlock(&cprman->regs_lock); 548 } 549 550 static int bcm2835_pll_on(struct clk_hw *hw) 551 { 552 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 553 struct bcm2835_cprman *cprman = pll->cprman; 554 const struct bcm2835_pll_data *data = pll->data; 555 ktime_t timeout; 556 557 cprman_write(cprman, data->a2w_ctrl_reg, 558 cprman_read(cprman, data->a2w_ctrl_reg) & 559 ~A2W_PLL_CTRL_PWRDN); 560 561 /* Take the PLL out of reset. */ 562 cprman_write(cprman, data->cm_ctrl_reg, 563 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); 564 565 /* Wait for the PLL to lock. */ 566 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 567 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { 568 if (ktime_after(ktime_get(), timeout)) { 569 dev_err(cprman->dev, "%s: couldn't lock PLL\n", 570 clk_hw_get_name(hw)); 571 return -ETIMEDOUT; 572 } 573 574 cpu_relax(); 575 } 576 577 return 0; 578 } 579 580 static void 581 bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana) 582 { 583 int i; 584 585 /* 586 * ANA register setup is done as a series of writes to 587 * ANA3-ANA0, in that order. This lets us write all 4 588 * registers as a single cycle of the serdes interface (taking 589 * 100 xosc clocks), whereas if we were to update ana0, 1, and 590 * 3 individually through their partial-write registers, each 591 * would be their own serdes cycle. 592 */ 593 for (i = 3; i >= 0; i--) 594 cprman_write(cprman, ana_reg_base + i * 4, ana[i]); 595 } 596 597 static int bcm2835_pll_set_rate(struct clk_hw *hw, 598 unsigned long rate, unsigned long parent_rate) 599 { 600 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 601 struct bcm2835_cprman *cprman = pll->cprman; 602 const struct bcm2835_pll_data *data = pll->data; 603 bool was_using_prediv, use_fb_prediv, do_ana_setup_first; 604 u32 ndiv, fdiv, a2w_ctl; 605 u32 ana[4]; 606 int i; 607 608 if (rate < data->min_rate || rate > data->max_rate) { 609 dev_err(cprman->dev, "%s: rate out of spec: %lu vs (%lu, %lu)\n", 610 clk_hw_get_name(hw), rate, 611 data->min_rate, data->max_rate); 612 return -EINVAL; 613 } 614 615 if (rate > data->max_fb_rate) { 616 use_fb_prediv = true; 617 rate /= 2; 618 } else { 619 use_fb_prediv = false; 620 } 621 622 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv); 623 624 for (i = 3; i >= 0; i--) 625 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); 626 627 was_using_prediv = ana[1] & data->ana->fb_prediv_mask; 628 629 ana[0] &= ~data->ana->mask0; 630 ana[0] |= data->ana->set0; 631 ana[1] &= ~data->ana->mask1; 632 ana[1] |= data->ana->set1; 633 ana[3] &= ~data->ana->mask3; 634 ana[3] |= data->ana->set3; 635 636 if (was_using_prediv && !use_fb_prediv) { 637 ana[1] &= ~data->ana->fb_prediv_mask; 638 do_ana_setup_first = true; 639 } else if (!was_using_prediv && use_fb_prediv) { 640 ana[1] |= data->ana->fb_prediv_mask; 641 do_ana_setup_first = false; 642 } else { 643 do_ana_setup_first = true; 644 } 645 646 /* Unmask the reference clock from the oscillator. */ 647 cprman_write(cprman, A2W_XOSC_CTRL, 648 cprman_read(cprman, A2W_XOSC_CTRL) | 649 data->reference_enable_mask); 650 651 if (do_ana_setup_first) 652 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); 653 654 /* Set the PLL multiplier from the oscillator. */ 655 cprman_write(cprman, data->frac_reg, fdiv); 656 657 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); 658 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK; 659 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT; 660 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK; 661 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT; 662 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); 663 664 if (!do_ana_setup_first) 665 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); 666 667 return 0; 668 } 669 670 static int bcm2835_pll_debug_init(struct clk_hw *hw, 671 struct dentry *dentry) 672 { 673 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 674 struct bcm2835_cprman *cprman = pll->cprman; 675 const struct bcm2835_pll_data *data = pll->data; 676 struct debugfs_reg32 *regs; 677 678 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); 679 if (!regs) 680 return -ENOMEM; 681 682 regs[0].name = "cm_ctrl"; 683 regs[0].offset = data->cm_ctrl_reg; 684 regs[1].name = "a2w_ctrl"; 685 regs[1].offset = data->a2w_ctrl_reg; 686 regs[2].name = "frac"; 687 regs[2].offset = data->frac_reg; 688 regs[3].name = "ana0"; 689 regs[3].offset = data->ana_reg_base + 0 * 4; 690 regs[4].name = "ana1"; 691 regs[4].offset = data->ana_reg_base + 1 * 4; 692 regs[5].name = "ana2"; 693 regs[5].offset = data->ana_reg_base + 2 * 4; 694 regs[6].name = "ana3"; 695 regs[6].offset = data->ana_reg_base + 3 * 4; 696 697 return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry); 698 } 699 700 static const struct clk_ops bcm2835_pll_clk_ops = { 701 .is_prepared = bcm2835_pll_is_on, 702 .prepare = bcm2835_pll_on, 703 .unprepare = bcm2835_pll_off, 704 .recalc_rate = bcm2835_pll_get_rate, 705 .set_rate = bcm2835_pll_set_rate, 706 .round_rate = bcm2835_pll_round_rate, 707 .debug_init = bcm2835_pll_debug_init, 708 }; 709 710 struct bcm2835_pll_divider { 711 struct clk_divider div; 712 struct bcm2835_cprman *cprman; 713 const struct bcm2835_pll_divider_data *data; 714 }; 715 716 static struct bcm2835_pll_divider * 717 bcm2835_pll_divider_from_hw(struct clk_hw *hw) 718 { 719 return container_of(hw, struct bcm2835_pll_divider, div.hw); 720 } 721 722 static int bcm2835_pll_divider_is_on(struct clk_hw *hw) 723 { 724 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 725 struct bcm2835_cprman *cprman = divider->cprman; 726 const struct bcm2835_pll_divider_data *data = divider->data; 727 728 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); 729 } 730 731 static long bcm2835_pll_divider_round_rate(struct clk_hw *hw, 732 unsigned long rate, 733 unsigned long *parent_rate) 734 { 735 return clk_divider_ops.round_rate(hw, rate, parent_rate); 736 } 737 738 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw, 739 unsigned long parent_rate) 740 { 741 return clk_divider_ops.recalc_rate(hw, parent_rate); 742 } 743 744 static void bcm2835_pll_divider_off(struct clk_hw *hw) 745 { 746 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 747 struct bcm2835_cprman *cprman = divider->cprman; 748 const struct bcm2835_pll_divider_data *data = divider->data; 749 750 spin_lock(&cprman->regs_lock); 751 cprman_write(cprman, data->cm_reg, 752 (cprman_read(cprman, data->cm_reg) & 753 ~data->load_mask) | data->hold_mask); 754 cprman_write(cprman, data->a2w_reg, A2W_PLL_CHANNEL_DISABLE); 755 spin_unlock(&cprman->regs_lock); 756 } 757 758 static int bcm2835_pll_divider_on(struct clk_hw *hw) 759 { 760 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 761 struct bcm2835_cprman *cprman = divider->cprman; 762 const struct bcm2835_pll_divider_data *data = divider->data; 763 764 spin_lock(&cprman->regs_lock); 765 cprman_write(cprman, data->a2w_reg, 766 cprman_read(cprman, data->a2w_reg) & 767 ~A2W_PLL_CHANNEL_DISABLE); 768 769 cprman_write(cprman, data->cm_reg, 770 cprman_read(cprman, data->cm_reg) & ~data->hold_mask); 771 spin_unlock(&cprman->regs_lock); 772 773 return 0; 774 } 775 776 static int bcm2835_pll_divider_set_rate(struct clk_hw *hw, 777 unsigned long rate, 778 unsigned long parent_rate) 779 { 780 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 781 struct bcm2835_cprman *cprman = divider->cprman; 782 const struct bcm2835_pll_divider_data *data = divider->data; 783 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS; 784 785 div = DIV_ROUND_UP_ULL(parent_rate, rate); 786 787 div = min(div, max_div); 788 if (div == max_div) 789 div = 0; 790 791 cprman_write(cprman, data->a2w_reg, div); 792 cm = cprman_read(cprman, data->cm_reg); 793 cprman_write(cprman, data->cm_reg, cm | data->load_mask); 794 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); 795 796 return 0; 797 } 798 799 static int bcm2835_pll_divider_debug_init(struct clk_hw *hw, 800 struct dentry *dentry) 801 { 802 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 803 struct bcm2835_cprman *cprman = divider->cprman; 804 const struct bcm2835_pll_divider_data *data = divider->data; 805 struct debugfs_reg32 *regs; 806 807 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); 808 if (!regs) 809 return -ENOMEM; 810 811 regs[0].name = "cm"; 812 regs[0].offset = data->cm_reg; 813 regs[1].name = "a2w"; 814 regs[1].offset = data->a2w_reg; 815 816 return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry); 817 } 818 819 static const struct clk_ops bcm2835_pll_divider_clk_ops = { 820 .is_prepared = bcm2835_pll_divider_is_on, 821 .prepare = bcm2835_pll_divider_on, 822 .unprepare = bcm2835_pll_divider_off, 823 .recalc_rate = bcm2835_pll_divider_get_rate, 824 .set_rate = bcm2835_pll_divider_set_rate, 825 .round_rate = bcm2835_pll_divider_round_rate, 826 .debug_init = bcm2835_pll_divider_debug_init, 827 }; 828 829 /* 830 * The CM dividers do fixed-point division, so we can't use the 831 * generic integer divider code like the PLL dividers do (and we can't 832 * fake it by having some fixed shifts preceding it in the clock tree, 833 * because we'd run out of bits in a 32-bit unsigned long). 834 */ 835 struct bcm2835_clock { 836 struct clk_hw hw; 837 struct bcm2835_cprman *cprman; 838 const struct bcm2835_clock_data *data; 839 }; 840 841 static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw) 842 { 843 return container_of(hw, struct bcm2835_clock, hw); 844 } 845 846 static int bcm2835_clock_is_on(struct clk_hw *hw) 847 { 848 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 849 struct bcm2835_cprman *cprman = clock->cprman; 850 const struct bcm2835_clock_data *data = clock->data; 851 852 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; 853 } 854 855 static u32 bcm2835_clock_choose_div(struct clk_hw *hw, 856 unsigned long rate, 857 unsigned long parent_rate, 858 bool round_up) 859 { 860 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 861 const struct bcm2835_clock_data *data = clock->data; 862 u32 unused_frac_mask = 863 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; 864 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; 865 u64 rem; 866 u32 div, mindiv, maxdiv; 867 868 rem = do_div(temp, rate); 869 div = temp; 870 871 /* Round up and mask off the unused bits */ 872 if (round_up && ((div & unused_frac_mask) != 0 || rem != 0)) 873 div += unused_frac_mask + 1; 874 div &= ~unused_frac_mask; 875 876 /* different clamping limits apply for a mash clock */ 877 if (data->is_mash_clock) { 878 /* clamp to min divider of 2 */ 879 mindiv = 2 << CM_DIV_FRAC_BITS; 880 /* clamp to the highest possible integer divider */ 881 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; 882 } else { 883 /* clamp to min divider of 1 */ 884 mindiv = 1 << CM_DIV_FRAC_BITS; 885 /* clamp to the highest possible fractional divider */ 886 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, 887 CM_DIV_FRAC_BITS - data->frac_bits); 888 } 889 890 /* apply the clamping limits */ 891 div = max_t(u32, div, mindiv); 892 div = min_t(u32, div, maxdiv); 893 894 return div; 895 } 896 897 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, 898 unsigned long parent_rate, 899 u32 div) 900 { 901 const struct bcm2835_clock_data *data = clock->data; 902 u64 temp; 903 904 /* 905 * The divisor is a 12.12 fixed point field, but only some of 906 * the bits are populated in any given clock. 907 */ 908 div >>= CM_DIV_FRAC_BITS - data->frac_bits; 909 div &= (1 << (data->int_bits + data->frac_bits)) - 1; 910 911 if (div == 0) 912 return 0; 913 914 temp = (u64)parent_rate << data->frac_bits; 915 916 do_div(temp, div); 917 918 return temp; 919 } 920 921 static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, 922 unsigned long parent_rate) 923 { 924 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 925 struct bcm2835_cprman *cprman = clock->cprman; 926 const struct bcm2835_clock_data *data = clock->data; 927 u32 div = cprman_read(cprman, data->div_reg); 928 929 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); 930 } 931 932 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) 933 { 934 struct bcm2835_cprman *cprman = clock->cprman; 935 const struct bcm2835_clock_data *data = clock->data; 936 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 937 938 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { 939 if (ktime_after(ktime_get(), timeout)) { 940 dev_err(cprman->dev, "%s: couldn't lock PLL\n", 941 clk_hw_get_name(&clock->hw)); 942 return; 943 } 944 cpu_relax(); 945 } 946 } 947 948 static void bcm2835_clock_off(struct clk_hw *hw) 949 { 950 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 951 struct bcm2835_cprman *cprman = clock->cprman; 952 const struct bcm2835_clock_data *data = clock->data; 953 954 spin_lock(&cprman->regs_lock); 955 cprman_write(cprman, data->ctl_reg, 956 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); 957 spin_unlock(&cprman->regs_lock); 958 959 /* BUSY will remain high until the divider completes its cycle. */ 960 bcm2835_clock_wait_busy(clock); 961 } 962 963 static int bcm2835_clock_on(struct clk_hw *hw) 964 { 965 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 966 struct bcm2835_cprman *cprman = clock->cprman; 967 const struct bcm2835_clock_data *data = clock->data; 968 969 spin_lock(&cprman->regs_lock); 970 cprman_write(cprman, data->ctl_reg, 971 cprman_read(cprman, data->ctl_reg) | 972 CM_ENABLE | 973 CM_GATE); 974 spin_unlock(&cprman->regs_lock); 975 976 return 0; 977 } 978 979 static int bcm2835_clock_set_rate(struct clk_hw *hw, 980 unsigned long rate, unsigned long parent_rate) 981 { 982 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 983 struct bcm2835_cprman *cprman = clock->cprman; 984 const struct bcm2835_clock_data *data = clock->data; 985 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); 986 u32 ctl; 987 988 spin_lock(&cprman->regs_lock); 989 990 /* 991 * Setting up frac support 992 * 993 * In principle it is recommended to stop/start the clock first, 994 * but as we set CLK_SET_RATE_GATE during registration of the 995 * clock this requirement should be take care of by the 996 * clk-framework. 997 */ 998 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; 999 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; 1000 cprman_write(cprman, data->ctl_reg, ctl); 1001 1002 cprman_write(cprman, data->div_reg, div); 1003 1004 spin_unlock(&cprman->regs_lock); 1005 1006 return 0; 1007 } 1008 1009 static int bcm2835_clock_determine_rate(struct clk_hw *hw, 1010 struct clk_rate_request *req) 1011 { 1012 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1013 struct clk_hw *parent, *best_parent = NULL; 1014 unsigned long rate, best_rate = 0; 1015 unsigned long prate, best_prate = 0; 1016 size_t i; 1017 u32 div; 1018 1019 /* 1020 * Select parent clock that results in the closest but lower rate 1021 */ 1022 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) { 1023 parent = clk_hw_get_parent_by_index(hw, i); 1024 if (!parent) 1025 continue; 1026 prate = clk_hw_get_rate(parent); 1027 div = bcm2835_clock_choose_div(hw, req->rate, prate, true); 1028 rate = bcm2835_clock_rate_from_divisor(clock, prate, div); 1029 if (rate > best_rate && rate <= req->rate) { 1030 best_parent = parent; 1031 best_prate = prate; 1032 best_rate = rate; 1033 } 1034 } 1035 1036 if (!best_parent) 1037 return -EINVAL; 1038 1039 req->best_parent_hw = best_parent; 1040 req->best_parent_rate = best_prate; 1041 1042 req->rate = best_rate; 1043 1044 return 0; 1045 } 1046 1047 static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index) 1048 { 1049 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1050 struct bcm2835_cprman *cprman = clock->cprman; 1051 const struct bcm2835_clock_data *data = clock->data; 1052 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK; 1053 1054 cprman_write(cprman, data->ctl_reg, src); 1055 return 0; 1056 } 1057 1058 static u8 bcm2835_clock_get_parent(struct clk_hw *hw) 1059 { 1060 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1061 struct bcm2835_cprman *cprman = clock->cprman; 1062 const struct bcm2835_clock_data *data = clock->data; 1063 u32 src = cprman_read(cprman, data->ctl_reg); 1064 1065 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; 1066 } 1067 1068 static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = { 1069 { 1070 .name = "ctl", 1071 .offset = 0, 1072 }, 1073 { 1074 .name = "div", 1075 .offset = 4, 1076 }, 1077 }; 1078 1079 static int bcm2835_clock_debug_init(struct clk_hw *hw, 1080 struct dentry *dentry) 1081 { 1082 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1083 struct bcm2835_cprman *cprman = clock->cprman; 1084 const struct bcm2835_clock_data *data = clock->data; 1085 1086 return bcm2835_debugfs_regset( 1087 cprman, data->ctl_reg, 1088 bcm2835_debugfs_clock_reg32, 1089 ARRAY_SIZE(bcm2835_debugfs_clock_reg32), 1090 dentry); 1091 } 1092 1093 static const struct clk_ops bcm2835_clock_clk_ops = { 1094 .is_prepared = bcm2835_clock_is_on, 1095 .prepare = bcm2835_clock_on, 1096 .unprepare = bcm2835_clock_off, 1097 .recalc_rate = bcm2835_clock_get_rate, 1098 .set_rate = bcm2835_clock_set_rate, 1099 .determine_rate = bcm2835_clock_determine_rate, 1100 .set_parent = bcm2835_clock_set_parent, 1101 .get_parent = bcm2835_clock_get_parent, 1102 .debug_init = bcm2835_clock_debug_init, 1103 }; 1104 1105 static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) 1106 { 1107 return true; 1108 } 1109 1110 /* 1111 * The VPU clock can never be disabled (it doesn't have an ENABLE 1112 * bit), so it gets its own set of clock ops. 1113 */ 1114 static const struct clk_ops bcm2835_vpu_clock_clk_ops = { 1115 .is_prepared = bcm2835_vpu_clock_is_on, 1116 .recalc_rate = bcm2835_clock_get_rate, 1117 .set_rate = bcm2835_clock_set_rate, 1118 .determine_rate = bcm2835_clock_determine_rate, 1119 .set_parent = bcm2835_clock_set_parent, 1120 .get_parent = bcm2835_clock_get_parent, 1121 .debug_init = bcm2835_clock_debug_init, 1122 }; 1123 1124 static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman, 1125 const struct bcm2835_pll_data *data) 1126 { 1127 struct bcm2835_pll *pll; 1128 struct clk_init_data init; 1129 1130 memset(&init, 0, sizeof(init)); 1131 1132 /* All of the PLLs derive from the external oscillator. */ 1133 init.parent_names = &cprman->osc_name; 1134 init.num_parents = 1; 1135 init.name = data->name; 1136 init.ops = &bcm2835_pll_clk_ops; 1137 init.flags = CLK_IGNORE_UNUSED; 1138 1139 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1140 if (!pll) 1141 return NULL; 1142 1143 pll->cprman = cprman; 1144 pll->data = data; 1145 pll->hw.init = &init; 1146 1147 return devm_clk_register(cprman->dev, &pll->hw); 1148 } 1149 1150 static struct clk * 1151 bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, 1152 const struct bcm2835_pll_divider_data *data) 1153 { 1154 struct bcm2835_pll_divider *divider; 1155 struct clk_init_data init; 1156 struct clk *clk; 1157 const char *divider_name; 1158 1159 if (data->fixed_divider != 1) { 1160 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, 1161 "%s_prediv", data->name); 1162 if (!divider_name) 1163 return NULL; 1164 } else { 1165 divider_name = data->name; 1166 } 1167 1168 memset(&init, 0, sizeof(init)); 1169 1170 init.parent_names = &data->source_pll; 1171 init.num_parents = 1; 1172 init.name = divider_name; 1173 init.ops = &bcm2835_pll_divider_clk_ops; 1174 init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; 1175 1176 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); 1177 if (!divider) 1178 return NULL; 1179 1180 divider->div.reg = cprman->regs + data->a2w_reg; 1181 divider->div.shift = A2W_PLL_DIV_SHIFT; 1182 divider->div.width = A2W_PLL_DIV_BITS; 1183 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; 1184 divider->div.lock = &cprman->regs_lock; 1185 divider->div.hw.init = &init; 1186 divider->div.table = NULL; 1187 1188 divider->cprman = cprman; 1189 divider->data = data; 1190 1191 clk = devm_clk_register(cprman->dev, ÷r->div.hw); 1192 if (IS_ERR(clk)) 1193 return clk; 1194 1195 /* 1196 * PLLH's channels have a fixed divide by 10 afterwards, which 1197 * is what our consumers are actually using. 1198 */ 1199 if (data->fixed_divider != 1) { 1200 return clk_register_fixed_factor(cprman->dev, data->name, 1201 divider_name, 1202 CLK_SET_RATE_PARENT, 1203 1, 1204 data->fixed_divider); 1205 } 1206 1207 return clk; 1208 } 1209 1210 static struct clk *bcm2835_register_clock(struct bcm2835_cprman *cprman, 1211 const struct bcm2835_clock_data *data) 1212 { 1213 struct bcm2835_clock *clock; 1214 struct clk_init_data init; 1215 const char *parents[1 << CM_SRC_BITS]; 1216 size_t i; 1217 1218 /* 1219 * Replace our "xosc" references with the oscillator's 1220 * actual name. 1221 */ 1222 for (i = 0; i < data->num_mux_parents; i++) { 1223 if (strcmp(data->parents[i], "xosc") == 0) 1224 parents[i] = cprman->osc_name; 1225 else 1226 parents[i] = data->parents[i]; 1227 } 1228 1229 memset(&init, 0, sizeof(init)); 1230 init.parent_names = parents; 1231 init.num_parents = data->num_mux_parents; 1232 init.name = data->name; 1233 init.flags = CLK_IGNORE_UNUSED; 1234 1235 if (data->is_vpu_clock) { 1236 init.ops = &bcm2835_vpu_clock_clk_ops; 1237 } else { 1238 init.ops = &bcm2835_clock_clk_ops; 1239 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; 1240 } 1241 1242 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); 1243 if (!clock) 1244 return NULL; 1245 1246 clock->cprman = cprman; 1247 clock->data = data; 1248 clock->hw.init = &init; 1249 1250 return devm_clk_register(cprman->dev, &clock->hw); 1251 } 1252 1253 static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman, 1254 const struct bcm2835_gate_data *data) 1255 { 1256 return clk_register_gate(cprman->dev, data->name, data->parent, 1257 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 1258 cprman->regs + data->ctl_reg, 1259 CM_GATE_BIT, 0, &cprman->regs_lock); 1260 } 1261 1262 typedef struct clk *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman, 1263 const void *data); 1264 struct bcm2835_clk_desc { 1265 bcm2835_clk_register clk_register; 1266 const void *data; 1267 }; 1268 1269 /* assignment helper macros for different clock types */ 1270 #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \ 1271 .data = __VA_ARGS__ } 1272 #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \ 1273 &(struct bcm2835_pll_data) \ 1274 {__VA_ARGS__}) 1275 #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \ 1276 &(struct bcm2835_pll_divider_data) \ 1277 {__VA_ARGS__}) 1278 #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \ 1279 &(struct bcm2835_clock_data) \ 1280 {__VA_ARGS__}) 1281 #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \ 1282 &(struct bcm2835_gate_data) \ 1283 {__VA_ARGS__}) 1284 1285 /* parent mux arrays plus helper macros */ 1286 1287 /* main oscillator parent mux */ 1288 static const char *const bcm2835_clock_osc_parents[] = { 1289 "gnd", 1290 "xosc", 1291 "testdebug0", 1292 "testdebug1" 1293 }; 1294 1295 #define REGISTER_OSC_CLK(...) REGISTER_CLK( \ 1296 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \ 1297 .parents = bcm2835_clock_osc_parents, \ 1298 __VA_ARGS__) 1299 1300 /* main peripherial parent mux */ 1301 static const char *const bcm2835_clock_per_parents[] = { 1302 "gnd", 1303 "xosc", 1304 "testdebug0", 1305 "testdebug1", 1306 "plla_per", 1307 "pllc_per", 1308 "plld_per", 1309 "pllh_aux", 1310 }; 1311 1312 #define REGISTER_PER_CLK(...) REGISTER_CLK( \ 1313 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \ 1314 .parents = bcm2835_clock_per_parents, \ 1315 __VA_ARGS__) 1316 1317 /* main vpu parent mux */ 1318 static const char *const bcm2835_clock_vpu_parents[] = { 1319 "gnd", 1320 "xosc", 1321 "testdebug0", 1322 "testdebug1", 1323 "plla_core", 1324 "pllc_core0", 1325 "plld_core", 1326 "pllh_aux", 1327 "pllc_core1", 1328 "pllc_core2", 1329 }; 1330 1331 #define REGISTER_VPU_CLK(...) REGISTER_CLK( \ 1332 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \ 1333 .parents = bcm2835_clock_vpu_parents, \ 1334 __VA_ARGS__) 1335 1336 /* 1337 * the real definition of all the pll, pll_dividers and clocks 1338 * these make use of the above REGISTER_* macros 1339 */ 1340 static const struct bcm2835_clk_desc clk_desc_array[] = { 1341 /* the PLL + PLL dividers */ 1342 1343 /* 1344 * PLLA is the auxiliary PLL, used to drive the CCP2 1345 * (Compact Camera Port 2) transmitter clock. 1346 * 1347 * It is in the PX LDO power domain, which is on when the 1348 * AUDIO domain is on. 1349 */ 1350 [BCM2835_PLLA] = REGISTER_PLL( 1351 .name = "plla", 1352 .cm_ctrl_reg = CM_PLLA, 1353 .a2w_ctrl_reg = A2W_PLLA_CTRL, 1354 .frac_reg = A2W_PLLA_FRAC, 1355 .ana_reg_base = A2W_PLLA_ANA0, 1356 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE, 1357 .lock_mask = CM_LOCK_FLOCKA, 1358 1359 .ana = &bcm2835_ana_default, 1360 1361 .min_rate = 600000000u, 1362 .max_rate = 2400000000u, 1363 .max_fb_rate = BCM2835_MAX_FB_RATE), 1364 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV( 1365 .name = "plla_core", 1366 .source_pll = "plla", 1367 .cm_reg = CM_PLLA, 1368 .a2w_reg = A2W_PLLA_CORE, 1369 .load_mask = CM_PLLA_LOADCORE, 1370 .hold_mask = CM_PLLA_HOLDCORE, 1371 .fixed_divider = 1), 1372 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( 1373 .name = "plla_per", 1374 .source_pll = "plla", 1375 .cm_reg = CM_PLLA, 1376 .a2w_reg = A2W_PLLA_PER, 1377 .load_mask = CM_PLLA_LOADPER, 1378 .hold_mask = CM_PLLA_HOLDPER, 1379 .fixed_divider = 1), 1380 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( 1381 .name = "plla_dsi0", 1382 .source_pll = "plla", 1383 .cm_reg = CM_PLLA, 1384 .a2w_reg = A2W_PLLA_DSI0, 1385 .load_mask = CM_PLLA_LOADDSI0, 1386 .hold_mask = CM_PLLA_HOLDDSI0, 1387 .fixed_divider = 1), 1388 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( 1389 .name = "plla_ccp2", 1390 .source_pll = "plla", 1391 .cm_reg = CM_PLLA, 1392 .a2w_reg = A2W_PLLA_CCP2, 1393 .load_mask = CM_PLLA_LOADCCP2, 1394 .hold_mask = CM_PLLA_HOLDCCP2, 1395 .fixed_divider = 1), 1396 1397 /* PLLB is used for the ARM's clock. */ 1398 [BCM2835_PLLB] = REGISTER_PLL( 1399 .name = "pllb", 1400 .cm_ctrl_reg = CM_PLLB, 1401 .a2w_ctrl_reg = A2W_PLLB_CTRL, 1402 .frac_reg = A2W_PLLB_FRAC, 1403 .ana_reg_base = A2W_PLLB_ANA0, 1404 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE, 1405 .lock_mask = CM_LOCK_FLOCKB, 1406 1407 .ana = &bcm2835_ana_default, 1408 1409 .min_rate = 600000000u, 1410 .max_rate = 3000000000u, 1411 .max_fb_rate = BCM2835_MAX_FB_RATE), 1412 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV( 1413 .name = "pllb_arm", 1414 .source_pll = "pllb", 1415 .cm_reg = CM_PLLB, 1416 .a2w_reg = A2W_PLLB_ARM, 1417 .load_mask = CM_PLLB_LOADARM, 1418 .hold_mask = CM_PLLB_HOLDARM, 1419 .fixed_divider = 1), 1420 1421 /* 1422 * PLLC is the core PLL, used to drive the core VPU clock. 1423 * 1424 * It is in the PX LDO power domain, which is on when the 1425 * AUDIO domain is on. 1426 */ 1427 [BCM2835_PLLC] = REGISTER_PLL( 1428 .name = "pllc", 1429 .cm_ctrl_reg = CM_PLLC, 1430 .a2w_ctrl_reg = A2W_PLLC_CTRL, 1431 .frac_reg = A2W_PLLC_FRAC, 1432 .ana_reg_base = A2W_PLLC_ANA0, 1433 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, 1434 .lock_mask = CM_LOCK_FLOCKC, 1435 1436 .ana = &bcm2835_ana_default, 1437 1438 .min_rate = 600000000u, 1439 .max_rate = 3000000000u, 1440 .max_fb_rate = BCM2835_MAX_FB_RATE), 1441 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV( 1442 .name = "pllc_core0", 1443 .source_pll = "pllc", 1444 .cm_reg = CM_PLLC, 1445 .a2w_reg = A2W_PLLC_CORE0, 1446 .load_mask = CM_PLLC_LOADCORE0, 1447 .hold_mask = CM_PLLC_HOLDCORE0, 1448 .fixed_divider = 1), 1449 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( 1450 .name = "pllc_core1", 1451 .source_pll = "pllc", 1452 .cm_reg = CM_PLLC, 1453 .a2w_reg = A2W_PLLC_CORE1, 1454 .load_mask = CM_PLLC_LOADCORE1, 1455 .hold_mask = CM_PLLC_HOLDCORE1, 1456 .fixed_divider = 1), 1457 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( 1458 .name = "pllc_core2", 1459 .source_pll = "pllc", 1460 .cm_reg = CM_PLLC, 1461 .a2w_reg = A2W_PLLC_CORE2, 1462 .load_mask = CM_PLLC_LOADCORE2, 1463 .hold_mask = CM_PLLC_HOLDCORE2, 1464 .fixed_divider = 1), 1465 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( 1466 .name = "pllc_per", 1467 .source_pll = "pllc", 1468 .cm_reg = CM_PLLC, 1469 .a2w_reg = A2W_PLLC_PER, 1470 .load_mask = CM_PLLC_LOADPER, 1471 .hold_mask = CM_PLLC_HOLDPER, 1472 .fixed_divider = 1), 1473 1474 /* 1475 * PLLD is the display PLL, used to drive DSI display panels. 1476 * 1477 * It is in the PX LDO power domain, which is on when the 1478 * AUDIO domain is on. 1479 */ 1480 [BCM2835_PLLD] = REGISTER_PLL( 1481 .name = "plld", 1482 .cm_ctrl_reg = CM_PLLD, 1483 .a2w_ctrl_reg = A2W_PLLD_CTRL, 1484 .frac_reg = A2W_PLLD_FRAC, 1485 .ana_reg_base = A2W_PLLD_ANA0, 1486 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE, 1487 .lock_mask = CM_LOCK_FLOCKD, 1488 1489 .ana = &bcm2835_ana_default, 1490 1491 .min_rate = 600000000u, 1492 .max_rate = 2400000000u, 1493 .max_fb_rate = BCM2835_MAX_FB_RATE), 1494 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV( 1495 .name = "plld_core", 1496 .source_pll = "plld", 1497 .cm_reg = CM_PLLD, 1498 .a2w_reg = A2W_PLLD_CORE, 1499 .load_mask = CM_PLLD_LOADCORE, 1500 .hold_mask = CM_PLLD_HOLDCORE, 1501 .fixed_divider = 1), 1502 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( 1503 .name = "plld_per", 1504 .source_pll = "plld", 1505 .cm_reg = CM_PLLD, 1506 .a2w_reg = A2W_PLLD_PER, 1507 .load_mask = CM_PLLD_LOADPER, 1508 .hold_mask = CM_PLLD_HOLDPER, 1509 .fixed_divider = 1), 1510 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( 1511 .name = "plld_dsi0", 1512 .source_pll = "plld", 1513 .cm_reg = CM_PLLD, 1514 .a2w_reg = A2W_PLLD_DSI0, 1515 .load_mask = CM_PLLD_LOADDSI0, 1516 .hold_mask = CM_PLLD_HOLDDSI0, 1517 .fixed_divider = 1), 1518 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( 1519 .name = "plld_dsi1", 1520 .source_pll = "plld", 1521 .cm_reg = CM_PLLD, 1522 .a2w_reg = A2W_PLLD_DSI1, 1523 .load_mask = CM_PLLD_LOADDSI1, 1524 .hold_mask = CM_PLLD_HOLDDSI1, 1525 .fixed_divider = 1), 1526 1527 /* 1528 * PLLH is used to supply the pixel clock or the AUX clock for the 1529 * TV encoder. 1530 * 1531 * It is in the HDMI power domain. 1532 */ 1533 [BCM2835_PLLH] = REGISTER_PLL( 1534 "pllh", 1535 .cm_ctrl_reg = CM_PLLH, 1536 .a2w_ctrl_reg = A2W_PLLH_CTRL, 1537 .frac_reg = A2W_PLLH_FRAC, 1538 .ana_reg_base = A2W_PLLH_ANA0, 1539 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, 1540 .lock_mask = CM_LOCK_FLOCKH, 1541 1542 .ana = &bcm2835_ana_pllh, 1543 1544 .min_rate = 600000000u, 1545 .max_rate = 3000000000u, 1546 .max_fb_rate = BCM2835_MAX_FB_RATE), 1547 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV( 1548 .name = "pllh_rcal", 1549 .source_pll = "pllh", 1550 .cm_reg = CM_PLLH, 1551 .a2w_reg = A2W_PLLH_RCAL, 1552 .load_mask = CM_PLLH_LOADRCAL, 1553 .hold_mask = 0, 1554 .fixed_divider = 10), 1555 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( 1556 .name = "pllh_aux", 1557 .source_pll = "pllh", 1558 .cm_reg = CM_PLLH, 1559 .a2w_reg = A2W_PLLH_AUX, 1560 .load_mask = CM_PLLH_LOADAUX, 1561 .hold_mask = 0, 1562 .fixed_divider = 10), 1563 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( 1564 .name = "pllh_pix", 1565 .source_pll = "pllh", 1566 .cm_reg = CM_PLLH, 1567 .a2w_reg = A2W_PLLH_PIX, 1568 .load_mask = CM_PLLH_LOADPIX, 1569 .hold_mask = 0, 1570 .fixed_divider = 10), 1571 1572 /* the clocks */ 1573 1574 /* clocks with oscillator parent mux */ 1575 1576 /* One Time Programmable Memory clock. Maximum 10Mhz. */ 1577 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK( 1578 .name = "otp", 1579 .ctl_reg = CM_OTPCTL, 1580 .div_reg = CM_OTPDIV, 1581 .int_bits = 4, 1582 .frac_bits = 0), 1583 /* 1584 * Used for a 1Mhz clock for the system clocksource, and also used 1585 * bythe watchdog timer and the camera pulse generator. 1586 */ 1587 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK( 1588 .name = "timer", 1589 .ctl_reg = CM_TIMERCTL, 1590 .div_reg = CM_TIMERDIV, 1591 .int_bits = 6, 1592 .frac_bits = 12), 1593 /* 1594 * Clock for the temperature sensor. 1595 * Generally run at 2Mhz, max 5Mhz. 1596 */ 1597 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK( 1598 .name = "tsens", 1599 .ctl_reg = CM_TSENSCTL, 1600 .div_reg = CM_TSENSDIV, 1601 .int_bits = 5, 1602 .frac_bits = 0), 1603 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK( 1604 .name = "tec", 1605 .ctl_reg = CM_TECCTL, 1606 .div_reg = CM_TECDIV, 1607 .int_bits = 6, 1608 .frac_bits = 0), 1609 1610 /* clocks with vpu parent mux */ 1611 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( 1612 .name = "h264", 1613 .ctl_reg = CM_H264CTL, 1614 .div_reg = CM_H264DIV, 1615 .int_bits = 4, 1616 .frac_bits = 8), 1617 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK( 1618 .name = "isp", 1619 .ctl_reg = CM_ISPCTL, 1620 .div_reg = CM_ISPDIV, 1621 .int_bits = 4, 1622 .frac_bits = 8), 1623 1624 /* 1625 * Secondary SDRAM clock. Used for low-voltage modes when the PLL 1626 * in the SDRAM controller can't be used. 1627 */ 1628 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK( 1629 .name = "sdram", 1630 .ctl_reg = CM_SDCCTL, 1631 .div_reg = CM_SDCDIV, 1632 .int_bits = 6, 1633 .frac_bits = 0), 1634 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( 1635 .name = "v3d", 1636 .ctl_reg = CM_V3DCTL, 1637 .div_reg = CM_V3DDIV, 1638 .int_bits = 4, 1639 .frac_bits = 8), 1640 /* 1641 * VPU clock. This doesn't have an enable bit, since it drives 1642 * the bus for everything else, and is special so it doesn't need 1643 * to be gated for rate changes. It is also known as "clk_audio" 1644 * in various hardware documentation. 1645 */ 1646 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK( 1647 .name = "vpu", 1648 .ctl_reg = CM_VPUCTL, 1649 .div_reg = CM_VPUDIV, 1650 .int_bits = 12, 1651 .frac_bits = 8, 1652 .is_vpu_clock = true), 1653 1654 /* clocks with per parent mux */ 1655 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK( 1656 .name = "aveo", 1657 .ctl_reg = CM_AVEOCTL, 1658 .div_reg = CM_AVEODIV, 1659 .int_bits = 4, 1660 .frac_bits = 0), 1661 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK( 1662 .name = "cam0", 1663 .ctl_reg = CM_CAM0CTL, 1664 .div_reg = CM_CAM0DIV, 1665 .int_bits = 4, 1666 .frac_bits = 8), 1667 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK( 1668 .name = "cam1", 1669 .ctl_reg = CM_CAM1CTL, 1670 .div_reg = CM_CAM1DIV, 1671 .int_bits = 4, 1672 .frac_bits = 8), 1673 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK( 1674 .name = "dft", 1675 .ctl_reg = CM_DFTCTL, 1676 .div_reg = CM_DFTDIV, 1677 .int_bits = 5, 1678 .frac_bits = 0), 1679 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK( 1680 .name = "dpi", 1681 .ctl_reg = CM_DPICTL, 1682 .div_reg = CM_DPIDIV, 1683 .int_bits = 4, 1684 .frac_bits = 8), 1685 1686 /* Arasan EMMC clock */ 1687 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( 1688 .name = "emmc", 1689 .ctl_reg = CM_EMMCCTL, 1690 .div_reg = CM_EMMCDIV, 1691 .int_bits = 4, 1692 .frac_bits = 8), 1693 1694 /* General purpose (GPIO) clocks */ 1695 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( 1696 .name = "gp0", 1697 .ctl_reg = CM_GP0CTL, 1698 .div_reg = CM_GP0DIV, 1699 .int_bits = 12, 1700 .frac_bits = 12, 1701 .is_mash_clock = true), 1702 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK( 1703 .name = "gp1", 1704 .ctl_reg = CM_GP1CTL, 1705 .div_reg = CM_GP1DIV, 1706 .int_bits = 12, 1707 .frac_bits = 12, 1708 .is_mash_clock = true), 1709 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK( 1710 .name = "gp2", 1711 .ctl_reg = CM_GP2CTL, 1712 .div_reg = CM_GP2DIV, 1713 .int_bits = 12, 1714 .frac_bits = 12), 1715 1716 /* HDMI state machine */ 1717 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( 1718 .name = "hsm", 1719 .ctl_reg = CM_HSMCTL, 1720 .div_reg = CM_HSMDIV, 1721 .int_bits = 4, 1722 .frac_bits = 8), 1723 [BCM2835_CLOCK_PCM] = REGISTER_PER_CLK( 1724 .name = "pcm", 1725 .ctl_reg = CM_PCMCTL, 1726 .div_reg = CM_PCMDIV, 1727 .int_bits = 12, 1728 .frac_bits = 12, 1729 .is_mash_clock = true), 1730 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK( 1731 .name = "pwm", 1732 .ctl_reg = CM_PWMCTL, 1733 .div_reg = CM_PWMDIV, 1734 .int_bits = 12, 1735 .frac_bits = 12, 1736 .is_mash_clock = true), 1737 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK( 1738 .name = "slim", 1739 .ctl_reg = CM_SLIMCTL, 1740 .div_reg = CM_SLIMDIV, 1741 .int_bits = 12, 1742 .frac_bits = 12, 1743 .is_mash_clock = true), 1744 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK( 1745 .name = "smi", 1746 .ctl_reg = CM_SMICTL, 1747 .div_reg = CM_SMIDIV, 1748 .int_bits = 4, 1749 .frac_bits = 8), 1750 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK( 1751 .name = "uart", 1752 .ctl_reg = CM_UARTCTL, 1753 .div_reg = CM_UARTDIV, 1754 .int_bits = 10, 1755 .frac_bits = 12), 1756 1757 /* TV encoder clock. Only operating frequency is 108Mhz. */ 1758 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( 1759 .name = "vec", 1760 .ctl_reg = CM_VECCTL, 1761 .div_reg = CM_VECDIV, 1762 .int_bits = 4, 1763 .frac_bits = 0), 1764 1765 /* dsi clocks */ 1766 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( 1767 .name = "dsi0e", 1768 .ctl_reg = CM_DSI0ECTL, 1769 .div_reg = CM_DSI0EDIV, 1770 .int_bits = 4, 1771 .frac_bits = 8), 1772 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK( 1773 .name = "dsi1e", 1774 .ctl_reg = CM_DSI1ECTL, 1775 .div_reg = CM_DSI1EDIV, 1776 .int_bits = 4, 1777 .frac_bits = 8), 1778 1779 /* the gates */ 1780 1781 /* 1782 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if 1783 * you have the debug bit set in the power manager, which we 1784 * don't bother exposing) are individual gates off of the 1785 * non-stop vpu clock. 1786 */ 1787 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE( 1788 .name = "peri_image", 1789 .parent = "vpu", 1790 .ctl_reg = CM_PERIICTL), 1791 }; 1792 1793 static int bcm2835_clk_probe(struct platform_device *pdev) 1794 { 1795 struct device *dev = &pdev->dev; 1796 struct clk **clks; 1797 struct bcm2835_cprman *cprman; 1798 struct resource *res; 1799 const struct bcm2835_clk_desc *desc; 1800 const size_t asize = ARRAY_SIZE(clk_desc_array); 1801 size_t i; 1802 1803 cprman = devm_kzalloc(dev, 1804 sizeof(*cprman) + asize * sizeof(*clks), 1805 GFP_KERNEL); 1806 if (!cprman) 1807 return -ENOMEM; 1808 1809 spin_lock_init(&cprman->regs_lock); 1810 cprman->dev = dev; 1811 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1812 cprman->regs = devm_ioremap_resource(dev, res); 1813 if (IS_ERR(cprman->regs)) 1814 return PTR_ERR(cprman->regs); 1815 1816 cprman->osc_name = of_clk_get_parent_name(dev->of_node, 0); 1817 if (!cprman->osc_name) 1818 return -ENODEV; 1819 1820 platform_set_drvdata(pdev, cprman); 1821 1822 cprman->onecell.clk_num = asize; 1823 cprman->onecell.clks = cprman->clks; 1824 clks = cprman->clks; 1825 1826 for (i = 0; i < asize; i++) { 1827 desc = &clk_desc_array[i]; 1828 if (desc->clk_register && desc->data) 1829 clks[i] = desc->clk_register(cprman, desc->data); 1830 } 1831 1832 return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, 1833 &cprman->onecell); 1834 } 1835 1836 static const struct of_device_id bcm2835_clk_of_match[] = { 1837 { .compatible = "brcm,bcm2835-cprman", }, 1838 {} 1839 }; 1840 MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); 1841 1842 static struct platform_driver bcm2835_clk_driver = { 1843 .driver = { 1844 .name = "bcm2835-clk", 1845 .of_match_table = bcm2835_clk_of_match, 1846 }, 1847 .probe = bcm2835_clk_probe, 1848 }; 1849 1850 builtin_platform_driver(bcm2835_clk_driver); 1851 1852 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 1853 MODULE_DESCRIPTION("BCM2835 clock driver"); 1854 MODULE_LICENSE("GPL v2"); 1855