1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/clk-provider.h> 3 #include <linux/mfd/syscon.h> 4 #include <linux/slab.h> 5 6 #include <dt-bindings/clock/at91.h> 7 8 #include "pmc.h" 9 10 static DEFINE_SPINLOCK(pmc_pll_lock); 11 static DEFINE_SPINLOCK(mck_lock); 12 13 static const struct clk_master_characteristics mck_characteristics = { 14 .output = { .min = 140000000, .max = 200000000 }, 15 .divisors = { 1, 2, 4, 3 }, 16 .have_div3_pres = 1, 17 }; 18 19 static const struct clk_master_layout sam9x60_master_layout = { 20 .mask = 0x373, 21 .pres_shift = 4, 22 .offset = 0x28, 23 }; 24 25 static const struct clk_range plla_outputs[] = { 26 { .min = 2343750, .max = 1200000000 }, 27 }; 28 29 /* Fractional PLL core output range. */ 30 static const struct clk_range core_outputs[] = { 31 { .min = 600000000, .max = 1200000000 }, 32 }; 33 34 static const struct clk_pll_characteristics plla_characteristics = { 35 .input = { .min = 12000000, .max = 48000000 }, 36 .num_output = ARRAY_SIZE(plla_outputs), 37 .output = plla_outputs, 38 .core_output = core_outputs, 39 .acr = UL(0x00020010), 40 }; 41 42 static const struct clk_range upll_outputs[] = { 43 { .min = 300000000, .max = 500000000 }, 44 }; 45 46 static const struct clk_pll_characteristics upll_characteristics = { 47 .input = { .min = 12000000, .max = 48000000 }, 48 .num_output = ARRAY_SIZE(upll_outputs), 49 .output = upll_outputs, 50 .core_output = core_outputs, 51 .upll = true, 52 .acr = UL(0x12023010), /* fIN = [18 MHz, 32 MHz]*/ 53 }; 54 55 static const struct clk_pll_layout pll_frac_layout = { 56 .mul_mask = GENMASK(31, 24), 57 .frac_mask = GENMASK(21, 0), 58 .mul_shift = 24, 59 .frac_shift = 0, 60 }; 61 62 static const struct clk_pll_layout pll_div_layout = { 63 .div_mask = GENMASK(7, 0), 64 .endiv_mask = BIT(29), 65 .div_shift = 0, 66 .endiv_shift = 29, 67 }; 68 69 static const struct clk_programmable_layout sam9x60_programmable_layout = { 70 .pres_mask = 0xff, 71 .pres_shift = 8, 72 .css_mask = 0x1f, 73 .have_slck_mck = 0, 74 .is_pres_direct = 1, 75 }; 76 77 static const struct clk_pcr_layout sam9x60_pcr_layout = { 78 .offset = 0x88, 79 .cmd = BIT(31), 80 .gckcss_mask = GENMASK(12, 8), 81 .pid_mask = GENMASK(6, 0), 82 }; 83 84 static const struct { 85 char *n; 86 char *p; 87 unsigned long flags; 88 u8 id; 89 } sam9x60_systemck[] = { 90 /* 91 * ddrck feeds DDR controller and is enabled by bootloader thus we need 92 * to keep it enabled in case there is no Linux consumer for it. 93 */ 94 { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, 95 { .n = "uhpck", .p = "usbck", .id = 6 }, 96 { .n = "pck0", .p = "prog0", .id = 8 }, 97 { .n = "pck1", .p = "prog1", .id = 9 }, 98 { .n = "qspick", .p = "masterck_div", .id = 19 }, 99 }; 100 101 static const struct { 102 char *n; 103 unsigned long flags; 104 u8 id; 105 } sam9x60_periphck[] = { 106 { .n = "pioA_clk", .id = 2, }, 107 { .n = "pioB_clk", .id = 3, }, 108 { .n = "pioC_clk", .id = 4, }, 109 { .n = "flex0_clk", .id = 5, }, 110 { .n = "flex1_clk", .id = 6, }, 111 { .n = "flex2_clk", .id = 7, }, 112 { .n = "flex3_clk", .id = 8, }, 113 { .n = "flex6_clk", .id = 9, }, 114 { .n = "flex7_clk", .id = 10, }, 115 { .n = "flex8_clk", .id = 11, }, 116 { .n = "sdmmc0_clk", .id = 12, }, 117 { .n = "flex4_clk", .id = 13, }, 118 { .n = "flex5_clk", .id = 14, }, 119 { .n = "flex9_clk", .id = 15, }, 120 { .n = "flex10_clk", .id = 16, }, 121 { .n = "tcb0_clk", .id = 17, }, 122 { .n = "pwm_clk", .id = 18, }, 123 { .n = "adc_clk", .id = 19, }, 124 { .n = "dma0_clk", .id = 20, }, 125 { .n = "matrix_clk", .id = 21, }, 126 { .n = "uhphs_clk", .id = 22, }, 127 { .n = "udphs_clk", .id = 23, }, 128 { .n = "macb0_clk", .id = 24, }, 129 { .n = "lcd_clk", .id = 25, }, 130 { .n = "sdmmc1_clk", .id = 26, }, 131 { .n = "macb1_clk", .id = 27, }, 132 { .n = "ssc_clk", .id = 28, }, 133 { .n = "can0_clk", .id = 29, }, 134 { .n = "can1_clk", .id = 30, }, 135 { .n = "flex11_clk", .id = 32, }, 136 { .n = "flex12_clk", .id = 33, }, 137 { .n = "i2s_clk", .id = 34, }, 138 { .n = "qspi_clk", .id = 35, }, 139 { .n = "gfx2d_clk", .id = 36, }, 140 { .n = "pit64b_clk", .id = 37, }, 141 { .n = "trng_clk", .id = 38, }, 142 { .n = "aes_clk", .id = 39, }, 143 { .n = "tdes_clk", .id = 40, }, 144 { .n = "sha_clk", .id = 41, }, 145 { .n = "classd_clk", .id = 42, }, 146 { .n = "isi_clk", .id = 43, }, 147 { .n = "pioD_clk", .id = 44, }, 148 { .n = "tcb1_clk", .id = 45, }, 149 { .n = "dbgu_clk", .id = 47, }, 150 /* 151 * mpddr_clk feeds DDR controller and is enabled by bootloader thus we 152 * need to keep it enabled in case there is no Linux consumer for it. 153 */ 154 { .n = "mpddr_clk", .id = 49, .flags = CLK_IS_CRITICAL }, 155 }; 156 157 static const struct { 158 char *n; 159 u8 id; 160 struct clk_range r; 161 } sam9x60_gck[] = { 162 { .n = "flex0_gclk", .id = 5, }, 163 { .n = "flex1_gclk", .id = 6, }, 164 { .n = "flex2_gclk", .id = 7, }, 165 { .n = "flex3_gclk", .id = 8, }, 166 { .n = "flex6_gclk", .id = 9, }, 167 { .n = "flex7_gclk", .id = 10, }, 168 { .n = "flex8_gclk", .id = 11, }, 169 { .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, }, 170 { .n = "flex4_gclk", .id = 13, }, 171 { .n = "flex5_gclk", .id = 14, }, 172 { .n = "flex9_gclk", .id = 15, }, 173 { .n = "flex10_gclk", .id = 16, }, 174 { .n = "tcb0_gclk", .id = 17, }, 175 { .n = "adc_gclk", .id = 19, }, 176 { .n = "lcd_gclk", .id = 25, .r = { .min = 0, .max = 140000000 }, }, 177 { .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, }, 178 { .n = "flex11_gclk", .id = 32, }, 179 { .n = "flex12_gclk", .id = 33, }, 180 { .n = "i2s_gclk", .id = 34, .r = { .min = 0, .max = 105000000 }, }, 181 { .n = "pit64b_gclk", .id = 37, }, 182 { .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 }, }, 183 { .n = "tcb1_gclk", .id = 45, }, 184 { .n = "dbgu_gclk", .id = 47, }, 185 }; 186 187 static void __init sam9x60_pmc_setup(struct device_node *np) 188 { 189 struct clk_range range = CLK_RANGE(0, 0); 190 const char *td_slck_name, *md_slck_name, *mainxtal_name; 191 struct pmc_data *sam9x60_pmc; 192 const char *parent_names[6]; 193 struct clk_hw *main_osc_hw; 194 struct regmap *regmap; 195 struct clk_hw *hw; 196 int i; 197 198 i = of_property_match_string(np, "clock-names", "td_slck"); 199 if (i < 0) 200 return; 201 202 td_slck_name = of_clk_get_parent_name(np, i); 203 204 i = of_property_match_string(np, "clock-names", "md_slck"); 205 if (i < 0) 206 return; 207 208 md_slck_name = of_clk_get_parent_name(np, i); 209 210 i = of_property_match_string(np, "clock-names", "main_xtal"); 211 if (i < 0) 212 return; 213 mainxtal_name = of_clk_get_parent_name(np, i); 214 215 regmap = device_node_to_regmap(np); 216 if (IS_ERR(regmap)) 217 return; 218 219 sam9x60_pmc = pmc_data_allocate(PMC_PLLACK + 1, 220 nck(sam9x60_systemck), 221 nck(sam9x60_periphck), 222 nck(sam9x60_gck), 8); 223 if (!sam9x60_pmc) 224 return; 225 226 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 227 50000000); 228 if (IS_ERR(hw)) 229 goto err_free; 230 231 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0); 232 if (IS_ERR(hw)) 233 goto err_free; 234 main_osc_hw = hw; 235 236 parent_names[0] = "main_rc_osc"; 237 parent_names[1] = "main_osc"; 238 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2); 239 if (IS_ERR(hw)) 240 goto err_free; 241 242 sam9x60_pmc->chws[PMC_MAIN] = hw; 243 244 hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck", 245 "mainck", sam9x60_pmc->chws[PMC_MAIN], 246 0, &plla_characteristics, 247 &pll_frac_layout, 248 /* 249 * This feeds pllack_divck which 250 * feeds CPU. It should not be 251 * disabled. 252 */ 253 CLK_IS_CRITICAL | CLK_SET_RATE_GATE); 254 if (IS_ERR(hw)) 255 goto err_free; 256 257 hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck", 258 "pllack_fracck", NULL, 0, &plla_characteristics, 259 &pll_div_layout, 260 /* 261 * This feeds CPU. It should not 262 * be disabled. 263 */ 264 CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0); 265 if (IS_ERR(hw)) 266 goto err_free; 267 268 sam9x60_pmc->chws[PMC_PLLACK] = hw; 269 270 hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck", 271 "main_osc", main_osc_hw, 1, 272 &upll_characteristics, 273 &pll_frac_layout, CLK_SET_RATE_GATE); 274 if (IS_ERR(hw)) 275 goto err_free; 276 277 hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck", 278 "upllck_fracck", NULL, 1, &upll_characteristics, 279 &pll_div_layout, 280 CLK_SET_RATE_GATE | 281 CLK_SET_PARENT_GATE | 282 CLK_SET_RATE_PARENT, 0); 283 if (IS_ERR(hw)) 284 goto err_free; 285 286 sam9x60_pmc->chws[PMC_UTMI] = hw; 287 288 parent_names[0] = md_slck_name; 289 parent_names[1] = "mainck"; 290 parent_names[2] = "pllack_divck"; 291 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3, 292 parent_names, NULL, &sam9x60_master_layout, 293 &mck_characteristics, &mck_lock); 294 if (IS_ERR(hw)) 295 goto err_free; 296 297 hw = at91_clk_register_master_div(regmap, "masterck_div", 298 "masterck_pres", NULL, &sam9x60_master_layout, 299 &mck_characteristics, &mck_lock, 300 CLK_SET_RATE_GATE, 0); 301 if (IS_ERR(hw)) 302 goto err_free; 303 304 sam9x60_pmc->chws[PMC_MCK] = hw; 305 306 parent_names[0] = "pllack_divck"; 307 parent_names[1] = "upllck_divck"; 308 parent_names[2] = "main_osc"; 309 hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); 310 if (IS_ERR(hw)) 311 goto err_free; 312 313 parent_names[0] = md_slck_name; 314 parent_names[1] = td_slck_name; 315 parent_names[2] = "mainck"; 316 parent_names[3] = "masterck_div"; 317 parent_names[4] = "pllack_divck"; 318 parent_names[5] = "upllck_divck"; 319 for (i = 0; i < 2; i++) { 320 char name[6]; 321 322 snprintf(name, sizeof(name), "prog%d", i); 323 324 hw = at91_clk_register_programmable(regmap, name, 325 parent_names, NULL, 6, i, 326 &sam9x60_programmable_layout, 327 NULL); 328 if (IS_ERR(hw)) 329 goto err_free; 330 331 sam9x60_pmc->pchws[i] = hw; 332 } 333 334 for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) { 335 hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n, 336 sam9x60_systemck[i].p, NULL, 337 sam9x60_systemck[i].id, 338 sam9x60_systemck[i].flags); 339 if (IS_ERR(hw)) 340 goto err_free; 341 342 sam9x60_pmc->shws[sam9x60_systemck[i].id] = hw; 343 } 344 345 for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) { 346 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, 347 &sam9x60_pcr_layout, 348 sam9x60_periphck[i].n, 349 "masterck_div", NULL, 350 sam9x60_periphck[i].id, 351 &range, INT_MIN, 352 sam9x60_periphck[i].flags); 353 if (IS_ERR(hw)) 354 goto err_free; 355 356 sam9x60_pmc->phws[sam9x60_periphck[i].id] = hw; 357 } 358 359 for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) { 360 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, 361 &sam9x60_pcr_layout, 362 sam9x60_gck[i].n, 363 parent_names, NULL, NULL, 6, 364 sam9x60_gck[i].id, 365 &sam9x60_gck[i].r, INT_MIN); 366 if (IS_ERR(hw)) 367 goto err_free; 368 369 sam9x60_pmc->ghws[sam9x60_gck[i].id] = hw; 370 } 371 372 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x60_pmc); 373 374 return; 375 376 err_free: 377 kfree(sam9x60_pmc); 378 } 379 /* Some clks are used for a clocksource */ 380 CLK_OF_DECLARE(sam9x60_pmc, "microchip,sam9x60-pmc", sam9x60_pmc_setup); 381