xref: /linux/drivers/clk/at91/sam9x60.c (revision 2c97b5ae83dca56718774e7b4bf9640f05d11867)
1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/mfd/syscon.h>
4 #include <linux/slab.h>
5 
6 #include <dt-bindings/clock/at91.h>
7 
8 #include "pmc.h"
9 
10 static DEFINE_SPINLOCK(pmc_pll_lock);
11 
12 static const struct clk_master_characteristics mck_characteristics = {
13 	.output = { .min = 140000000, .max = 200000000 },
14 	.divisors = { 1, 2, 4, 3 },
15 	.have_div3_pres = 1,
16 };
17 
18 static const struct clk_master_layout sam9x60_master_layout = {
19 	.mask = 0x373,
20 	.pres_shift = 4,
21 	.offset = 0x28,
22 };
23 
24 static const struct clk_range plla_outputs[] = {
25 	{ .min = 300000000, .max = 600000000 },
26 };
27 
28 static const struct clk_pll_characteristics plla_characteristics = {
29 	.input = { .min = 12000000, .max = 48000000 },
30 	.num_output = ARRAY_SIZE(plla_outputs),
31 	.output = plla_outputs,
32 };
33 
34 static const struct clk_range upll_outputs[] = {
35 	{ .min = 300000000, .max = 500000000 },
36 };
37 
38 static const struct clk_pll_characteristics upll_characteristics = {
39 	.input = { .min = 12000000, .max = 48000000 },
40 	.num_output = ARRAY_SIZE(upll_outputs),
41 	.output = upll_outputs,
42 	.upll = true,
43 };
44 
45 static const struct clk_programmable_layout sam9x60_programmable_layout = {
46 	.pres_mask = 0xff,
47 	.pres_shift = 8,
48 	.css_mask = 0x1f,
49 	.have_slck_mck = 0,
50 };
51 
52 static const struct clk_pcr_layout sam9x60_pcr_layout = {
53 	.offset = 0x88,
54 	.cmd = BIT(31),
55 	.gckcss_mask = GENMASK(12, 8),
56 	.pid_mask = GENMASK(6, 0),
57 };
58 
59 static const struct {
60 	char *n;
61 	char *p;
62 	u8 id;
63 } sam9x60_systemck[] = {
64 	{ .n = "ddrck",  .p = "masterck", .id = 2 },
65 	{ .n = "uhpck",  .p = "usbck",    .id = 6 },
66 	{ .n = "pck0",   .p = "prog0",    .id = 8 },
67 	{ .n = "pck1",   .p = "prog1",    .id = 9 },
68 	{ .n = "qspick", .p = "masterck", .id = 19 },
69 };
70 
71 static const struct {
72 	char *n;
73 	u8 id;
74 } sam9x60_periphck[] = {
75 	{ .n = "pioA_clk",   .id = 2, },
76 	{ .n = "pioB_clk",   .id = 3, },
77 	{ .n = "pioC_clk",   .id = 4, },
78 	{ .n = "flex0_clk",  .id = 5, },
79 	{ .n = "flex1_clk",  .id = 6, },
80 	{ .n = "flex2_clk",  .id = 7, },
81 	{ .n = "flex3_clk",  .id = 8, },
82 	{ .n = "flex6_clk",  .id = 9, },
83 	{ .n = "flex7_clk",  .id = 10, },
84 	{ .n = "flex8_clk",  .id = 11, },
85 	{ .n = "sdmmc0_clk", .id = 12, },
86 	{ .n = "flex4_clk",  .id = 13, },
87 	{ .n = "flex5_clk",  .id = 14, },
88 	{ .n = "flex9_clk",  .id = 15, },
89 	{ .n = "flex10_clk", .id = 16, },
90 	{ .n = "tcb0_clk",   .id = 17, },
91 	{ .n = "pwm_clk",    .id = 18, },
92 	{ .n = "adc_clk",    .id = 19, },
93 	{ .n = "dma0_clk",   .id = 20, },
94 	{ .n = "matrix_clk", .id = 21, },
95 	{ .n = "uhphs_clk",  .id = 22, },
96 	{ .n = "udphs_clk",  .id = 23, },
97 	{ .n = "macb0_clk",  .id = 24, },
98 	{ .n = "lcd_clk",    .id = 25, },
99 	{ .n = "sdmmc1_clk", .id = 26, },
100 	{ .n = "macb1_clk",  .id = 27, },
101 	{ .n = "ssc_clk",    .id = 28, },
102 	{ .n = "can0_clk",   .id = 29, },
103 	{ .n = "can1_clk",   .id = 30, },
104 	{ .n = "flex11_clk", .id = 32, },
105 	{ .n = "flex12_clk", .id = 33, },
106 	{ .n = "i2s_clk",    .id = 34, },
107 	{ .n = "qspi_clk",   .id = 35, },
108 	{ .n = "gfx2d_clk",  .id = 36, },
109 	{ .n = "pit64b_clk", .id = 37, },
110 	{ .n = "trng_clk",   .id = 38, },
111 	{ .n = "aes_clk",    .id = 39, },
112 	{ .n = "tdes_clk",   .id = 40, },
113 	{ .n = "sha_clk",    .id = 41, },
114 	{ .n = "classd_clk", .id = 42, },
115 	{ .n = "isi_clk",    .id = 43, },
116 	{ .n = "pioD_clk",   .id = 44, },
117 	{ .n = "tcb1_clk",   .id = 45, },
118 	{ .n = "dbgu_clk",   .id = 47, },
119 	{ .n = "mpddr_clk",  .id = 49, },
120 };
121 
122 static const struct {
123 	char *n;
124 	u8 id;
125 	struct clk_range r;
126 	bool pll;
127 } sam9x60_gck[] = {
128 	{ .n = "flex0_gclk",  .id = 5, },
129 	{ .n = "flex1_gclk",  .id = 6, },
130 	{ .n = "flex2_gclk",  .id = 7, },
131 	{ .n = "flex3_gclk",  .id = 8, },
132 	{ .n = "flex6_gclk",  .id = 9, },
133 	{ .n = "flex7_gclk",  .id = 10, },
134 	{ .n = "flex8_gclk",  .id = 11, },
135 	{ .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, },
136 	{ .n = "flex4_gclk",  .id = 13, },
137 	{ .n = "flex5_gclk",  .id = 14, },
138 	{ .n = "flex9_gclk",  .id = 15, },
139 	{ .n = "flex10_gclk", .id = 16, },
140 	{ .n = "tcb0_gclk",   .id = 17, },
141 	{ .n = "adc_gclk",    .id = 19, },
142 	{ .n = "lcd_gclk",    .id = 25, .r = { .min = 0, .max = 140000000 }, },
143 	{ .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, },
144 	{ .n = "flex11_gclk", .id = 32, },
145 	{ .n = "flex12_gclk", .id = 33, },
146 	{ .n = "i2s_gclk",    .id = 34, .r = { .min = 0, .max = 105000000 },
147 		.pll = true, },
148 	{ .n = "pit64b_gclk", .id = 37, },
149 	{ .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 },
150 		.pll = true, },
151 	{ .n = "tcb1_gclk",   .id = 45, },
152 	{ .n = "dbgu_gclk",   .id = 47, },
153 };
154 
155 static void __init sam9x60_pmc_setup(struct device_node *np)
156 {
157 	struct clk_range range = CLK_RANGE(0, 0);
158 	const char *td_slck_name, *md_slck_name, *mainxtal_name;
159 	struct pmc_data *sam9x60_pmc;
160 	const char *parent_names[6];
161 	struct regmap *regmap;
162 	struct clk_hw *hw;
163 	int i;
164 	bool bypass;
165 
166 	i = of_property_match_string(np, "clock-names", "td_slck");
167 	if (i < 0)
168 		return;
169 
170 	td_slck_name = of_clk_get_parent_name(np, i);
171 
172 	i = of_property_match_string(np, "clock-names", "md_slck");
173 	if (i < 0)
174 		return;
175 
176 	md_slck_name = of_clk_get_parent_name(np, i);
177 
178 	i = of_property_match_string(np, "clock-names", "main_xtal");
179 	if (i < 0)
180 		return;
181 	mainxtal_name = of_clk_get_parent_name(np, i);
182 
183 	regmap = syscon_node_to_regmap(np);
184 	if (IS_ERR(regmap))
185 		return;
186 
187 	sam9x60_pmc = pmc_data_allocate(PMC_MAIN + 1,
188 					nck(sam9x60_systemck),
189 					nck(sam9x60_periphck),
190 					nck(sam9x60_gck));
191 	if (!sam9x60_pmc)
192 		return;
193 
194 	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 24000000,
195 					   50000000);
196 	if (IS_ERR(hw))
197 		goto err_free;
198 
199 	bypass = of_property_read_bool(np, "atmel,osc-bypass");
200 
201 	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
202 					bypass);
203 	if (IS_ERR(hw))
204 		goto err_free;
205 
206 	parent_names[0] = "main_rc_osc";
207 	parent_names[1] = "main_osc";
208 	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
209 	if (IS_ERR(hw))
210 		goto err_free;
211 
212 	sam9x60_pmc->chws[PMC_MAIN] = hw;
213 
214 	hw = sam9x60_clk_register_pll(regmap, &pmc_pll_lock, "pllack",
215 				      "mainck", 0, &plla_characteristics);
216 	if (IS_ERR(hw))
217 		goto err_free;
218 
219 	hw = sam9x60_clk_register_pll(regmap, &pmc_pll_lock, "upllck",
220 				      "main_osc", 1, &upll_characteristics);
221 	if (IS_ERR(hw))
222 		goto err_free;
223 
224 	sam9x60_pmc->chws[PMC_UTMI] = hw;
225 
226 	parent_names[0] = md_slck_name;
227 	parent_names[1] = "mainck";
228 	parent_names[2] = "pllack";
229 	hw = at91_clk_register_master(regmap, "masterck", 3, parent_names,
230 				      &sam9x60_master_layout,
231 				      &mck_characteristics);
232 	if (IS_ERR(hw))
233 		goto err_free;
234 
235 	sam9x60_pmc->chws[PMC_MCK] = hw;
236 
237 	parent_names[0] = "pllack";
238 	parent_names[1] = "upllck";
239 	parent_names[2] = "mainck";
240 	parent_names[3] = "mainck";
241 	hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 4);
242 	if (IS_ERR(hw))
243 		goto err_free;
244 
245 	parent_names[0] = md_slck_name;
246 	parent_names[1] = td_slck_name;
247 	parent_names[2] = "mainck";
248 	parent_names[3] = "masterck";
249 	parent_names[4] = "pllack";
250 	parent_names[5] = "upllck";
251 	for (i = 0; i < 8; i++) {
252 		char name[6];
253 
254 		snprintf(name, sizeof(name), "prog%d", i);
255 
256 		hw = at91_clk_register_programmable(regmap, name,
257 						    parent_names, 6, i,
258 						    &sam9x60_programmable_layout);
259 		if (IS_ERR(hw))
260 			goto err_free;
261 	}
262 
263 	for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) {
264 		hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n,
265 					      sam9x60_systemck[i].p,
266 					      sam9x60_systemck[i].id);
267 		if (IS_ERR(hw))
268 			goto err_free;
269 
270 		sam9x60_pmc->shws[sam9x60_systemck[i].id] = hw;
271 	}
272 
273 	for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) {
274 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
275 							 &sam9x60_pcr_layout,
276 							 sam9x60_periphck[i].n,
277 							 "masterck",
278 							 sam9x60_periphck[i].id,
279 							 &range);
280 		if (IS_ERR(hw))
281 			goto err_free;
282 
283 		sam9x60_pmc->phws[sam9x60_periphck[i].id] = hw;
284 	}
285 
286 	for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) {
287 		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
288 						 &sam9x60_pcr_layout,
289 						 sam9x60_gck[i].n,
290 						 parent_names, 6,
291 						 sam9x60_gck[i].id,
292 						 sam9x60_gck[i].pll,
293 						 &sam9x60_gck[i].r);
294 		if (IS_ERR(hw))
295 			goto err_free;
296 
297 		sam9x60_pmc->ghws[sam9x60_gck[i].id] = hw;
298 	}
299 
300 	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x60_pmc);
301 
302 	return;
303 
304 err_free:
305 	pmc_data_free(sam9x60_pmc);
306 }
307 /* Some clks are used for a clocksource */
308 CLK_OF_DECLARE(sam9x60_pmc, "microchip,sam9x60-pmc", sam9x60_pmc_setup);
309