1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/clk-provider.h> 3 #include <linux/clk/at91_pmc.h> 4 #include <linux/of.h> 5 #include <linux/of_address.h> 6 #include <linux/mfd/syscon.h> 7 #include <linux/regmap.h> 8 #include <linux/slab.h> 9 10 #include "pmc.h" 11 12 #define MASTER_SOURCE_MAX 4 13 14 #define PERIPHERAL_AT91RM9200 0 15 #define PERIPHERAL_AT91SAM9X5 1 16 17 #define PERIPHERAL_MAX 64 18 19 #define PERIPHERAL_ID_MIN 2 20 21 #define PROG_SOURCE_MAX 5 22 #define PROG_ID_MAX 7 23 24 #define SYSTEM_MAX_ID 31 25 26 #define GCK_INDEX_DT_AUDIO_PLL 5 27 28 static DEFINE_SPINLOCK(mck_lock); 29 30 #ifdef CONFIG_HAVE_AT91_AUDIO_PLL 31 static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np) 32 { 33 struct clk_hw *hw; 34 const char *name = np->name; 35 const char *parent_name; 36 struct regmap *regmap; 37 struct device_node *parent_np; 38 39 parent_np = of_get_parent(np); 40 regmap = syscon_node_to_regmap(parent_np); 41 of_node_put(parent_np); 42 if (IS_ERR(regmap)) 43 return; 44 45 parent_name = of_clk_get_parent_name(np, 0); 46 47 hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name); 48 if (IS_ERR(hw)) 49 return; 50 51 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 52 } 53 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup, 54 "atmel,sama5d2-clk-audio-pll-frac", 55 of_sama5d2_clk_audio_pll_frac_setup); 56 57 static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np) 58 { 59 struct clk_hw *hw; 60 const char *name = np->name; 61 const char *parent_name; 62 struct regmap *regmap; 63 struct device_node *parent_np; 64 65 parent_np = of_get_parent(np); 66 regmap = syscon_node_to_regmap(parent_np); 67 of_node_put(parent_np); 68 if (IS_ERR(regmap)) 69 return; 70 71 parent_name = of_clk_get_parent_name(np, 0); 72 73 hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name); 74 if (IS_ERR(hw)) 75 return; 76 77 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 78 } 79 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup, 80 "atmel,sama5d2-clk-audio-pll-pad", 81 of_sama5d2_clk_audio_pll_pad_setup); 82 83 static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np) 84 { 85 struct clk_hw *hw; 86 const char *name = np->name; 87 const char *parent_name; 88 struct regmap *regmap; 89 struct device_node *parent_np; 90 91 parent_np = of_get_parent(np); 92 regmap = syscon_node_to_regmap(parent_np); 93 of_node_put(parent_np); 94 if (IS_ERR(regmap)) 95 return; 96 97 parent_name = of_clk_get_parent_name(np, 0); 98 99 hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name); 100 if (IS_ERR(hw)) 101 return; 102 103 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 104 } 105 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup, 106 "atmel,sama5d2-clk-audio-pll-pmc", 107 of_sama5d2_clk_audio_pll_pmc_setup); 108 #endif /* CONFIG_HAVE_AT91_AUDIO_PLL */ 109 110 static const struct clk_pcr_layout dt_pcr_layout = { 111 .offset = 0x10c, 112 .cmd = BIT(12), 113 .pid_mask = GENMASK(5, 0), 114 .div_mask = GENMASK(17, 16), 115 .gckcss_mask = GENMASK(10, 8), 116 }; 117 118 #ifdef CONFIG_HAVE_AT91_GENERATED_CLK 119 #define GENERATED_SOURCE_MAX 6 120 121 #define GCK_ID_I2S0 54 122 #define GCK_ID_I2S1 55 123 #define GCK_ID_CLASSD 59 124 125 static void __init of_sama5d2_clk_generated_setup(struct device_node *np) 126 { 127 int num; 128 u32 id; 129 const char *name; 130 struct clk_hw *hw; 131 unsigned int num_parents; 132 const char *parent_names[GENERATED_SOURCE_MAX]; 133 struct device_node *gcknp, *parent_np; 134 struct clk_range range = CLK_RANGE(0, 0); 135 struct regmap *regmap; 136 137 num_parents = of_clk_get_parent_count(np); 138 if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX) 139 return; 140 141 of_clk_parent_fill(np, parent_names, num_parents); 142 143 num = of_get_child_count(np); 144 if (!num || num > PERIPHERAL_MAX) 145 return; 146 147 parent_np = of_get_parent(np); 148 regmap = syscon_node_to_regmap(parent_np); 149 of_node_put(parent_np); 150 if (IS_ERR(regmap)) 151 return; 152 153 for_each_child_of_node(np, gcknp) { 154 int chg_pid = INT_MIN; 155 156 if (of_property_read_u32(gcknp, "reg", &id)) 157 continue; 158 159 if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX) 160 continue; 161 162 if (of_property_read_string(np, "clock-output-names", &name)) 163 name = gcknp->name; 164 165 of_at91_get_clk_range(gcknp, "atmel,clk-output-range", 166 &range); 167 168 if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") && 169 (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 || 170 id == GCK_ID_CLASSD)) 171 chg_pid = GCK_INDEX_DT_AUDIO_PLL; 172 173 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, 174 &dt_pcr_layout, name, 175 parent_names, NULL, NULL, 176 num_parents, id, &range, 177 chg_pid); 178 if (IS_ERR(hw)) 179 continue; 180 181 of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw); 182 } 183 } 184 CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated", 185 of_sama5d2_clk_generated_setup); 186 #endif /* CONFIG_HAVE_AT91_GENERATED_CLK */ 187 188 #ifdef CONFIG_HAVE_AT91_H32MX 189 static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np) 190 { 191 struct clk_hw *hw; 192 const char *name = np->name; 193 const char *parent_name; 194 struct regmap *regmap; 195 struct device_node *parent_np; 196 197 parent_np = of_get_parent(np); 198 regmap = syscon_node_to_regmap(parent_np); 199 of_node_put(parent_np); 200 if (IS_ERR(regmap)) 201 return; 202 203 parent_name = of_clk_get_parent_name(np, 0); 204 205 hw = at91_clk_register_h32mx(regmap, name, parent_name); 206 if (IS_ERR(hw)) 207 return; 208 209 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 210 } 211 CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx", 212 of_sama5d4_clk_h32mx_setup); 213 #endif /* CONFIG_HAVE_AT91_H32MX */ 214 215 #ifdef CONFIG_HAVE_AT91_I2S_MUX_CLK 216 #define I2S_BUS_NR 2 217 218 static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np) 219 { 220 struct regmap *regmap_sfr; 221 u64 bus_id; 222 const char *parent_names[2]; 223 struct device_node *i2s_mux_np; 224 struct clk_hw *hw; 225 int ret; 226 227 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr"); 228 if (IS_ERR(regmap_sfr)) 229 return; 230 231 for_each_child_of_node(np, i2s_mux_np) { 232 if (of_property_read_reg(i2s_mux_np, 0, &bus_id, NULL)) 233 continue; 234 235 if (bus_id > I2S_BUS_NR) 236 continue; 237 238 ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2); 239 if (ret != 2) 240 continue; 241 242 hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name, 243 parent_names, 2, bus_id); 244 if (IS_ERR(hw)) 245 continue; 246 247 of_clk_add_hw_provider(i2s_mux_np, of_clk_hw_simple_get, hw); 248 } 249 } 250 CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux", 251 of_sama5d2_clk_i2s_mux_setup); 252 #endif /* CONFIG_HAVE_AT91_I2S_MUX_CLK */ 253 254 static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np) 255 { 256 struct clk_hw *hw; 257 const char *name = np->name; 258 const char *parent_name; 259 struct regmap *regmap; 260 bool bypass; 261 struct device_node *parent_np; 262 263 of_property_read_string(np, "clock-output-names", &name); 264 bypass = of_property_read_bool(np, "atmel,osc-bypass"); 265 parent_name = of_clk_get_parent_name(np, 0); 266 267 parent_np = of_get_parent(np); 268 regmap = syscon_node_to_regmap(parent_np); 269 of_node_put(parent_np); 270 if (IS_ERR(regmap)) 271 return; 272 273 hw = at91_clk_register_main_osc(regmap, name, parent_name, NULL, bypass); 274 if (IS_ERR(hw)) 275 return; 276 277 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 278 } 279 CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc", 280 of_at91rm9200_clk_main_osc_setup); 281 282 static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np) 283 { 284 struct clk_hw *hw; 285 u32 frequency = 0; 286 u32 accuracy = 0; 287 const char *name = np->name; 288 struct regmap *regmap; 289 struct device_node *parent_np; 290 291 of_property_read_string(np, "clock-output-names", &name); 292 of_property_read_u32(np, "clock-frequency", &frequency); 293 of_property_read_u32(np, "clock-accuracy", &accuracy); 294 295 parent_np = of_get_parent(np); 296 regmap = syscon_node_to_regmap(parent_np); 297 of_node_put(parent_np); 298 if (IS_ERR(regmap)) 299 return; 300 301 hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy); 302 if (IS_ERR(hw)) 303 return; 304 305 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 306 } 307 CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc", 308 of_at91sam9x5_clk_main_rc_osc_setup); 309 310 static void __init of_at91rm9200_clk_main_setup(struct device_node *np) 311 { 312 struct clk_hw *hw; 313 const char *parent_name; 314 const char *name = np->name; 315 struct regmap *regmap; 316 struct device_node *parent_np; 317 318 parent_name = of_clk_get_parent_name(np, 0); 319 of_property_read_string(np, "clock-output-names", &name); 320 321 parent_np = of_get_parent(np); 322 regmap = syscon_node_to_regmap(parent_np); 323 of_node_put(parent_np); 324 if (IS_ERR(regmap)) 325 return; 326 327 hw = at91_clk_register_rm9200_main(regmap, name, parent_name, NULL); 328 if (IS_ERR(hw)) 329 return; 330 331 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 332 } 333 CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main", 334 of_at91rm9200_clk_main_setup); 335 336 static void __init of_at91sam9x5_clk_main_setup(struct device_node *np) 337 { 338 struct clk_hw *hw; 339 const char *parent_names[2]; 340 unsigned int num_parents; 341 const char *name = np->name; 342 struct regmap *regmap; 343 struct device_node *parent_np; 344 345 num_parents = of_clk_get_parent_count(np); 346 if (num_parents == 0 || num_parents > 2) 347 return; 348 349 of_clk_parent_fill(np, parent_names, num_parents); 350 parent_np = of_get_parent(np); 351 regmap = syscon_node_to_regmap(parent_np); 352 of_node_put(parent_np); 353 if (IS_ERR(regmap)) 354 return; 355 356 of_property_read_string(np, "clock-output-names", &name); 357 358 hw = at91_clk_register_sam9x5_main(regmap, name, parent_names, NULL, 359 num_parents); 360 if (IS_ERR(hw)) 361 return; 362 363 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 364 } 365 CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main", 366 of_at91sam9x5_clk_main_setup); 367 368 static struct clk_master_characteristics * __init 369 of_at91_clk_master_get_characteristics(struct device_node *np) 370 { 371 struct clk_master_characteristics *characteristics; 372 373 characteristics = kzalloc_obj(*characteristics); 374 if (!characteristics) 375 return NULL; 376 377 if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output)) 378 goto out_free_characteristics; 379 380 of_property_read_u32_array(np, "atmel,clk-divisors", 381 characteristics->divisors, 4); 382 383 characteristics->have_div3_pres = 384 of_property_read_bool(np, "atmel,master-clk-have-div3-pres"); 385 386 return characteristics; 387 388 out_free_characteristics: 389 kfree(characteristics); 390 return NULL; 391 } 392 393 static void __init 394 of_at91_clk_master_setup(struct device_node *np, 395 const struct clk_master_layout *layout) 396 { 397 struct clk_hw *hw; 398 unsigned int num_parents; 399 const char *parent_names[MASTER_SOURCE_MAX]; 400 const char *name = np->name; 401 struct clk_master_characteristics *characteristics; 402 struct regmap *regmap; 403 struct device_node *parent_np; 404 405 num_parents = of_clk_get_parent_count(np); 406 if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX) 407 return; 408 409 of_clk_parent_fill(np, parent_names, num_parents); 410 411 of_property_read_string(np, "clock-output-names", &name); 412 413 characteristics = of_at91_clk_master_get_characteristics(np); 414 if (!characteristics) 415 return; 416 417 parent_np = of_get_parent(np); 418 regmap = syscon_node_to_regmap(parent_np); 419 of_node_put(parent_np); 420 if (IS_ERR(regmap)) 421 return; 422 423 hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents, 424 parent_names, NULL, layout, 425 characteristics, &mck_lock); 426 if (IS_ERR(hw)) 427 goto out_free_characteristics; 428 429 hw = at91_clk_register_master_div(regmap, name, "masterck_pres", NULL, 430 layout, characteristics, 431 &mck_lock, CLK_SET_RATE_GATE, 0); 432 if (IS_ERR(hw)) 433 goto out_free_characteristics; 434 435 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 436 return; 437 438 out_free_characteristics: 439 kfree(characteristics); 440 } 441 442 static void __init of_at91rm9200_clk_master_setup(struct device_node *np) 443 { 444 of_at91_clk_master_setup(np, &at91rm9200_master_layout); 445 } 446 CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master", 447 of_at91rm9200_clk_master_setup); 448 449 static void __init of_at91sam9x5_clk_master_setup(struct device_node *np) 450 { 451 of_at91_clk_master_setup(np, &at91sam9x5_master_layout); 452 } 453 CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master", 454 of_at91sam9x5_clk_master_setup); 455 456 static void __init 457 of_at91_clk_periph_setup(struct device_node *np, u8 type) 458 { 459 int num; 460 u32 id; 461 struct clk_hw *hw; 462 const char *parent_name; 463 const char *name; 464 struct device_node *periphclknp; 465 struct regmap *regmap; 466 struct device_node *parent_np; 467 468 parent_name = of_clk_get_parent_name(np, 0); 469 if (!parent_name) 470 return; 471 472 num = of_get_child_count(np); 473 if (!num || num > PERIPHERAL_MAX) 474 return; 475 476 parent_np = of_get_parent(np); 477 regmap = syscon_node_to_regmap(parent_np); 478 of_node_put(parent_np); 479 if (IS_ERR(regmap)) 480 return; 481 482 for_each_child_of_node(np, periphclknp) { 483 if (of_property_read_u32(periphclknp, "reg", &id)) 484 continue; 485 486 if (id >= PERIPHERAL_MAX) 487 continue; 488 489 if (of_property_read_string(np, "clock-output-names", &name)) 490 name = periphclknp->name; 491 492 if (type == PERIPHERAL_AT91RM9200) { 493 hw = at91_clk_register_peripheral(regmap, name, 494 parent_name, NULL, id); 495 } else { 496 struct clk_range range = CLK_RANGE(0, 0); 497 unsigned long flags = 0; 498 499 of_at91_get_clk_range(periphclknp, 500 "atmel,clk-output-range", 501 &range); 502 503 /* 504 * mpddr_clk feed DDR controller and is enabled by 505 * bootloader thus we need to keep it enabled in case 506 * there is no Linux consumer for it. 507 */ 508 if (!strcmp(periphclknp->name, "mpddr_clk")) 509 flags = CLK_IS_CRITICAL; 510 511 hw = at91_clk_register_sam9x5_peripheral(regmap, 512 &pmc_pcr_lock, 513 &dt_pcr_layout, 514 name, 515 parent_name, 516 NULL, 517 id, &range, 518 INT_MIN, 519 flags); 520 } 521 522 if (IS_ERR(hw)) 523 continue; 524 525 of_clk_add_hw_provider(periphclknp, of_clk_hw_simple_get, hw); 526 } 527 } 528 529 static void __init of_at91rm9200_clk_periph_setup(struct device_node *np) 530 { 531 of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200); 532 } 533 CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral", 534 of_at91rm9200_clk_periph_setup); 535 536 static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np) 537 { 538 of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5); 539 } 540 CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral", 541 of_at91sam9x5_clk_periph_setup); 542 543 static struct clk_pll_characteristics * __init 544 of_at91_clk_pll_get_characteristics(struct device_node *np) 545 { 546 int i; 547 int offset; 548 u32 tmp; 549 int num_output; 550 u32 num_cells; 551 struct clk_range input; 552 struct clk_range *output; 553 u8 *out = NULL; 554 u16 *icpll = NULL; 555 struct clk_pll_characteristics *characteristics; 556 557 if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input)) 558 return NULL; 559 560 if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells", 561 &num_cells)) 562 return NULL; 563 564 if (num_cells < 2 || num_cells > 4) 565 return NULL; 566 567 num_output = of_property_count_u32_elems(np, "atmel,pll-clk-output-ranges"); 568 if (num_output <= 0) 569 return NULL; 570 num_output /= num_cells; 571 572 characteristics = kzalloc_obj(*characteristics); 573 if (!characteristics) 574 return NULL; 575 576 output = kzalloc_objs(*output, num_output); 577 if (!output) 578 goto out_free_characteristics; 579 580 if (num_cells > 2) { 581 out = kcalloc(num_output, sizeof(*out), GFP_KERNEL); 582 if (!out) 583 goto out_free_output; 584 } 585 586 if (num_cells > 3) { 587 icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL); 588 if (!icpll) 589 goto out_free_output; 590 } 591 592 for (i = 0; i < num_output; i++) { 593 offset = i * num_cells; 594 if (of_property_read_u32_index(np, 595 "atmel,pll-clk-output-ranges", 596 offset, &tmp)) 597 goto out_free_output; 598 output[i].min = tmp; 599 if (of_property_read_u32_index(np, 600 "atmel,pll-clk-output-ranges", 601 offset + 1, &tmp)) 602 goto out_free_output; 603 output[i].max = tmp; 604 605 if (num_cells == 2) 606 continue; 607 608 if (of_property_read_u32_index(np, 609 "atmel,pll-clk-output-ranges", 610 offset + 2, &tmp)) 611 goto out_free_output; 612 out[i] = tmp; 613 614 if (num_cells == 3) 615 continue; 616 617 if (of_property_read_u32_index(np, 618 "atmel,pll-clk-output-ranges", 619 offset + 3, &tmp)) 620 goto out_free_output; 621 icpll[i] = tmp; 622 } 623 624 characteristics->input = input; 625 characteristics->num_output = num_output; 626 characteristics->output = output; 627 characteristics->out = out; 628 characteristics->icpll = icpll; 629 return characteristics; 630 631 out_free_output: 632 kfree(icpll); 633 kfree(out); 634 kfree(output); 635 out_free_characteristics: 636 kfree(characteristics); 637 return NULL; 638 } 639 640 static void __init 641 of_at91_clk_pll_setup(struct device_node *np, 642 const struct clk_pll_layout *layout) 643 { 644 u32 id; 645 struct clk_hw *hw; 646 struct regmap *regmap; 647 const char *parent_name; 648 const char *name = np->name; 649 struct device_node *parent_np; 650 struct clk_pll_characteristics *characteristics; 651 652 if (of_property_read_u32(np, "reg", &id)) 653 return; 654 655 parent_name = of_clk_get_parent_name(np, 0); 656 657 of_property_read_string(np, "clock-output-names", &name); 658 659 parent_np = of_get_parent(np); 660 regmap = syscon_node_to_regmap(parent_np); 661 of_node_put(parent_np); 662 if (IS_ERR(regmap)) 663 return; 664 665 characteristics = of_at91_clk_pll_get_characteristics(np); 666 if (!characteristics) 667 return; 668 669 hw = at91_clk_register_pll(regmap, name, parent_name, id, layout, 670 characteristics); 671 if (IS_ERR(hw)) 672 goto out_free_characteristics; 673 674 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 675 return; 676 677 out_free_characteristics: 678 kfree(characteristics); 679 } 680 681 static void __init of_at91rm9200_clk_pll_setup(struct device_node *np) 682 { 683 of_at91_clk_pll_setup(np, &at91rm9200_pll_layout); 684 } 685 CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll", 686 of_at91rm9200_clk_pll_setup); 687 688 static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np) 689 { 690 of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout); 691 } 692 CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll", 693 of_at91sam9g45_clk_pll_setup); 694 695 static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np) 696 { 697 of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout); 698 } 699 CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb", 700 of_at91sam9g20_clk_pllb_setup); 701 702 static void __init of_sama5d3_clk_pll_setup(struct device_node *np) 703 { 704 of_at91_clk_pll_setup(np, &sama5d3_pll_layout); 705 } 706 CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll", 707 of_sama5d3_clk_pll_setup); 708 709 static void __init 710 of_at91sam9x5_clk_plldiv_setup(struct device_node *np) 711 { 712 struct clk_hw *hw; 713 const char *parent_name; 714 const char *name = np->name; 715 struct regmap *regmap; 716 struct device_node *parent_np; 717 718 parent_name = of_clk_get_parent_name(np, 0); 719 720 of_property_read_string(np, "clock-output-names", &name); 721 722 parent_np = of_get_parent(np); 723 regmap = syscon_node_to_regmap(parent_np); 724 of_node_put(parent_np); 725 if (IS_ERR(regmap)) 726 return; 727 728 hw = at91_clk_register_plldiv(regmap, name, parent_name); 729 if (IS_ERR(hw)) 730 return; 731 732 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 733 } 734 CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv", 735 of_at91sam9x5_clk_plldiv_setup); 736 737 static void __init 738 of_at91_clk_prog_setup(struct device_node *np, 739 const struct clk_programmable_layout *layout, 740 u32 *mux_table) 741 { 742 int num; 743 u32 id; 744 struct clk_hw *hw; 745 unsigned int num_parents; 746 const char *parent_names[PROG_SOURCE_MAX]; 747 const char *name; 748 struct device_node *progclknp, *parent_np; 749 struct regmap *regmap; 750 751 num_parents = of_clk_get_parent_count(np); 752 if (num_parents == 0 || num_parents > PROG_SOURCE_MAX) 753 return; 754 755 of_clk_parent_fill(np, parent_names, num_parents); 756 757 num = of_get_child_count(np); 758 if (!num || num > (PROG_ID_MAX + 1)) 759 return; 760 761 parent_np = of_get_parent(np); 762 regmap = syscon_node_to_regmap(parent_np); 763 of_node_put(parent_np); 764 if (IS_ERR(regmap)) 765 return; 766 767 for_each_child_of_node(np, progclknp) { 768 if (of_property_read_u32(progclknp, "reg", &id)) 769 continue; 770 771 if (of_property_read_string(np, "clock-output-names", &name)) 772 name = progclknp->name; 773 774 hw = at91_clk_register_programmable(regmap, name, 775 parent_names, NULL, num_parents, 776 id, layout, mux_table); 777 if (IS_ERR(hw)) 778 continue; 779 780 of_clk_add_hw_provider(progclknp, of_clk_hw_simple_get, hw); 781 } 782 } 783 784 static void __init of_at91rm9200_clk_prog_setup(struct device_node *np) 785 { 786 of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout, NULL); 787 } 788 CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable", 789 of_at91rm9200_clk_prog_setup); 790 791 static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np) 792 { 793 of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout, NULL); 794 } 795 CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable", 796 of_at91sam9g45_clk_prog_setup); 797 798 static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np) 799 { 800 of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout, NULL); 801 } 802 CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable", 803 of_at91sam9x5_clk_prog_setup); 804 805 static void __init of_at91sam9260_clk_slow_setup(struct device_node *np) 806 { 807 struct clk_hw *hw; 808 const char *parent_names[2]; 809 unsigned int num_parents; 810 const char *name = np->name; 811 struct regmap *regmap; 812 struct device_node *parent_np; 813 814 num_parents = of_clk_get_parent_count(np); 815 if (num_parents != 2) 816 return; 817 818 of_clk_parent_fill(np, parent_names, num_parents); 819 parent_np = of_get_parent(np); 820 regmap = syscon_node_to_regmap(parent_np); 821 of_node_put(parent_np); 822 if (IS_ERR(regmap)) 823 return; 824 825 of_property_read_string(np, "clock-output-names", &name); 826 827 hw = at91_clk_register_sam9260_slow(regmap, name, parent_names, 828 num_parents); 829 if (IS_ERR(hw)) 830 return; 831 832 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 833 } 834 CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow", 835 of_at91sam9260_clk_slow_setup); 836 837 #ifdef CONFIG_HAVE_AT91_SMD 838 #define SMD_SOURCE_MAX 2 839 840 static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np) 841 { 842 struct clk_hw *hw; 843 unsigned int num_parents; 844 const char *parent_names[SMD_SOURCE_MAX]; 845 const char *name = np->name; 846 struct regmap *regmap; 847 struct device_node *parent_np; 848 849 num_parents = of_clk_get_parent_count(np); 850 if (num_parents == 0 || num_parents > SMD_SOURCE_MAX) 851 return; 852 853 of_clk_parent_fill(np, parent_names, num_parents); 854 855 of_property_read_string(np, "clock-output-names", &name); 856 857 parent_np = of_get_parent(np); 858 regmap = syscon_node_to_regmap(parent_np); 859 of_node_put(parent_np); 860 if (IS_ERR(regmap)) 861 return; 862 863 hw = at91sam9x5_clk_register_smd(regmap, name, parent_names, 864 num_parents); 865 if (IS_ERR(hw)) 866 return; 867 868 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 869 } 870 CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd", 871 of_at91sam9x5_clk_smd_setup); 872 #endif /* CONFIG_HAVE_AT91_SMD */ 873 874 static void __init of_at91rm9200_clk_sys_setup(struct device_node *np) 875 { 876 int num; 877 u32 id; 878 struct clk_hw *hw; 879 const char *name; 880 struct device_node *sysclknp, *parent_np; 881 const char *parent_name; 882 struct regmap *regmap; 883 884 num = of_get_child_count(np); 885 if (num > (SYSTEM_MAX_ID + 1)) 886 return; 887 888 parent_np = of_get_parent(np); 889 regmap = syscon_node_to_regmap(parent_np); 890 of_node_put(parent_np); 891 if (IS_ERR(regmap)) 892 return; 893 894 for_each_child_of_node(np, sysclknp) { 895 unsigned long flags = 0; 896 897 if (of_property_read_u32(sysclknp, "reg", &id)) 898 continue; 899 900 if (of_property_read_string(np, "clock-output-names", &name)) 901 name = sysclknp->name; 902 903 parent_name = of_clk_get_parent_name(sysclknp, 0); 904 905 /* 906 * ddrck feeds DDR controller and is enabled by bootloader thus 907 * we need to keep it enabled in case there is no Linux consumer 908 * for it. 909 */ 910 if (!strcmp(sysclknp->name, "ddrck")) 911 flags = CLK_IS_CRITICAL; 912 913 hw = at91_clk_register_system(regmap, name, parent_name, NULL, 914 id, flags); 915 if (IS_ERR(hw)) 916 continue; 917 918 of_clk_add_hw_provider(sysclknp, of_clk_hw_simple_get, hw); 919 } 920 } 921 CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system", 922 of_at91rm9200_clk_sys_setup); 923 924 #ifdef CONFIG_HAVE_AT91_USB_CLK 925 #define USB_SOURCE_MAX 2 926 927 static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np) 928 { 929 struct clk_hw *hw; 930 unsigned int num_parents; 931 const char *parent_names[USB_SOURCE_MAX]; 932 const char *name = np->name; 933 struct regmap *regmap; 934 struct device_node *parent_np; 935 936 num_parents = of_clk_get_parent_count(np); 937 if (num_parents == 0 || num_parents > USB_SOURCE_MAX) 938 return; 939 940 of_clk_parent_fill(np, parent_names, num_parents); 941 942 of_property_read_string(np, "clock-output-names", &name); 943 944 parent_np = of_get_parent(np); 945 regmap = syscon_node_to_regmap(parent_np); 946 of_node_put(parent_np); 947 if (IS_ERR(regmap)) 948 return; 949 950 hw = at91sam9x5_clk_register_usb(regmap, name, parent_names, 951 num_parents); 952 if (IS_ERR(hw)) 953 return; 954 955 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 956 } 957 CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb", 958 of_at91sam9x5_clk_usb_setup); 959 960 static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np) 961 { 962 struct clk_hw *hw; 963 const char *parent_name; 964 const char *name = np->name; 965 struct regmap *regmap; 966 struct device_node *parent_np; 967 968 parent_name = of_clk_get_parent_name(np, 0); 969 if (!parent_name) 970 return; 971 972 of_property_read_string(np, "clock-output-names", &name); 973 974 parent_np = of_get_parent(np); 975 regmap = syscon_node_to_regmap(parent_np); 976 of_node_put(parent_np); 977 if (IS_ERR(regmap)) 978 return; 979 980 hw = at91sam9n12_clk_register_usb(regmap, name, parent_name); 981 if (IS_ERR(hw)) 982 return; 983 984 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 985 } 986 CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb", 987 of_at91sam9n12_clk_usb_setup); 988 989 static void __init of_at91rm9200_clk_usb_setup(struct device_node *np) 990 { 991 struct clk_hw *hw; 992 const char *parent_name; 993 const char *name = np->name; 994 u32 divisors[4] = {0, 0, 0, 0}; 995 struct regmap *regmap; 996 struct device_node *parent_np; 997 998 parent_name = of_clk_get_parent_name(np, 0); 999 if (!parent_name) 1000 return; 1001 1002 of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4); 1003 if (!divisors[0]) 1004 return; 1005 1006 of_property_read_string(np, "clock-output-names", &name); 1007 1008 parent_np = of_get_parent(np); 1009 regmap = syscon_node_to_regmap(parent_np); 1010 of_node_put(parent_np); 1011 if (IS_ERR(regmap)) 1012 return; 1013 hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors); 1014 if (IS_ERR(hw)) 1015 return; 1016 1017 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 1018 } 1019 CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb", 1020 of_at91rm9200_clk_usb_setup); 1021 #endif /* CONFIG_HAVE_AT91_USB_CLK */ 1022 1023 #ifdef CONFIG_HAVE_AT91_UTMI 1024 static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np) 1025 { 1026 struct clk_hw *hw; 1027 const char *parent_name; 1028 const char *name = np->name; 1029 struct regmap *regmap_pmc, *regmap_sfr; 1030 struct device_node *parent_np; 1031 1032 parent_name = of_clk_get_parent_name(np, 0); 1033 1034 of_property_read_string(np, "clock-output-names", &name); 1035 1036 parent_np = of_get_parent(np); 1037 regmap_pmc = syscon_node_to_regmap(parent_np); 1038 of_node_put(parent_np); 1039 if (IS_ERR(regmap_pmc)) 1040 return; 1041 1042 /* 1043 * If the device supports different mainck rates, this value has to be 1044 * set in the UTMI Clock Trimming register. 1045 * - 9x5: mainck supports several rates but it is indicated that a 1046 * 12 MHz is needed in case of USB. 1047 * - sama5d3 and sama5d2: mainck supports several rates. Configuring 1048 * the FREQ field of the UTMI Clock Trimming register is mandatory. 1049 * - sama5d4: mainck is at 12 MHz. 1050 * 1051 * We only need to retrieve sama5d3 or sama5d2 sfr regmap. 1052 */ 1053 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr"); 1054 if (IS_ERR(regmap_sfr)) { 1055 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr"); 1056 if (IS_ERR(regmap_sfr)) 1057 regmap_sfr = NULL; 1058 } 1059 1060 hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name, NULL); 1061 if (IS_ERR(hw)) 1062 return; 1063 1064 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 1065 } 1066 CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi", 1067 of_at91sam9x5_clk_utmi_setup); 1068 #endif /* CONFIG_HAVE_AT91_UTMI */ 1069