1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018-2019 SiFive, Inc. 4 * Wesley Terpstra 5 * Paul Walmsley 6 * 7 * This library supports configuration parsing and reprogramming of 8 * the CLN28HPC variant of the Analog Bits Wide Range PLL. The 9 * intention is for this library to be reusable for any device that 10 * integrates this PLL; thus the register structure and programming 11 * details are expected to be provided by a separate IP block driver. 12 * 13 * The bulk of this code is primarily useful for clock configurations 14 * that must operate at arbitrary rates, as opposed to clock configurations 15 * that are restricted by software or manufacturer guidance to a small, 16 * pre-determined set of performance points. 17 * 18 * References: 19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01 20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset" 21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf 22 */ 23 24 #include <linux/bug.h> 25 #include <linux/err.h> 26 #include <linux/limits.h> 27 #include <linux/log2.h> 28 #include <linux/math64.h> 29 #include <linux/math.h> 30 #include <linux/minmax.h> 31 32 #include <linux/clk/analogbits-wrpll-cln28hpc.h> 33 34 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */ 35 #define MIN_INPUT_FREQ 7000000 36 37 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */ 38 #define MAX_INPUT_FREQ 600000000 39 40 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */ 41 #define MIN_POST_DIVR_FREQ 7000000 42 43 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */ 44 #define MAX_POST_DIVR_FREQ 200000000 45 46 /* MIN_VCO_FREQ: minimum VCO frequency, in Hz (Fvco_min) */ 47 #define MIN_VCO_FREQ 2400000000UL 48 49 /* MAX_VCO_FREQ: maximum VCO frequency, in Hz (Fvco_max) */ 50 #define MAX_VCO_FREQ 4800000000ULL 51 52 /* MAX_DIVQ_DIVISOR: maximum output divisor. Selected by DIVQ = 6 */ 53 #define MAX_DIVQ_DIVISOR 64 54 55 /* MAX_DIVR_DIVISOR: maximum reference divisor. Selected by DIVR = 63 */ 56 #define MAX_DIVR_DIVISOR 64 57 58 /* MAX_LOCK_US: maximum PLL lock time, in microseconds (tLOCK_max) */ 59 #define MAX_LOCK_US 70 60 61 /* 62 * ROUND_SHIFT: number of bits to shift to avoid precision loss in the rounding 63 * algorithm 64 */ 65 #define ROUND_SHIFT 20 66 67 /* 68 * Private functions 69 */ 70 71 /** 72 * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth 73 * @post_divr_freq: input clock rate after the R divider 74 * 75 * Select the value to be presented to the PLL RANGE input signals, based 76 * on the input clock frequency after the post-R-divider @post_divr_freq. 77 * This code follows the recommendations in the PLL datasheet for filter 78 * range selection. 79 * 80 * Return: The RANGE value to be presented to the PLL configuration inputs, 81 * or a negative return code upon error. 82 */ 83 static int __wrpll_calc_filter_range(unsigned long post_divr_freq) 84 { 85 if (post_divr_freq < MIN_POST_DIVR_FREQ || 86 post_divr_freq > MAX_POST_DIVR_FREQ) { 87 WARN(1, "%s: post-divider reference freq out of range: %lu", 88 __func__, post_divr_freq); 89 return -ERANGE; 90 } 91 92 switch (post_divr_freq) { 93 case 0 ... 10999999: 94 return 1; 95 case 11000000 ... 17999999: 96 return 2; 97 case 18000000 ... 29999999: 98 return 3; 99 case 30000000 ... 49999999: 100 return 4; 101 case 50000000 ... 79999999: 102 return 5; 103 case 80000000 ... 129999999: 104 return 6; 105 } 106 107 return 7; 108 } 109 110 /** 111 * __wrpll_calc_fbdiv() - return feedback fixed divide value 112 * @c: ptr to a struct wrpll_cfg record to read from 113 * 114 * The internal feedback path includes a fixed by-two divider; the 115 * external feedback path does not. Return the appropriate divider 116 * value (2 or 1) depending on whether internal or external feedback 117 * is enabled. This code doesn't test for invalid configurations 118 * (e.g. both or neither of WRPLL_FLAGS_*_FEEDBACK are set); it relies 119 * on the caller to do so. 120 * 121 * Context: Any context. Caller must protect the memory pointed to by 122 * @c from simultaneous modification. 123 * 124 * Return: 2 if internal feedback is enabled or 1 if external feedback 125 * is enabled. 126 */ 127 static u8 __wrpll_calc_fbdiv(const struct wrpll_cfg *c) 128 { 129 return (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK) ? 2 : 1; 130 } 131 132 /** 133 * __wrpll_calc_divq() - determine DIVQ based on target PLL output clock rate 134 * @target_rate: target PLL output clock rate 135 * @vco_rate: pointer to a u64 to store the computed VCO rate into 136 * 137 * Determine a reasonable value for the PLL Q post-divider, based on the 138 * target output rate @target_rate for the PLL. Along with returning the 139 * computed Q divider value as the return value, this function stores the 140 * desired target VCO rate into the variable pointed to by @vco_rate. 141 * 142 * Context: Any context. Caller must protect the memory pointed to by 143 * @vco_rate from simultaneous access or modification. 144 * 145 * Return: a positive integer DIVQ value to be programmed into the hardware 146 * upon success, or 0 upon error (since 0 is an invalid DIVQ value) 147 */ 148 static u8 __wrpll_calc_divq(u32 target_rate, u64 *vco_rate) 149 { 150 u64 s; 151 u8 divq = 0; 152 153 if (!vco_rate) { 154 WARN_ON(1); 155 goto wcd_out; 156 } 157 158 s = div_u64(MAX_VCO_FREQ, target_rate); 159 if (s <= 1) { 160 divq = 1; 161 *vco_rate = MAX_VCO_FREQ; 162 } else if (s > MAX_DIVQ_DIVISOR) { 163 divq = ilog2(MAX_DIVQ_DIVISOR); 164 *vco_rate = MIN_VCO_FREQ; 165 } else { 166 divq = ilog2(s); 167 *vco_rate = (u64)target_rate << divq; 168 } 169 170 wcd_out: 171 return divq; 172 } 173 174 /** 175 * __wrpll_update_parent_rate() - update PLL data when parent rate changes 176 * @c: ptr to a struct wrpll_cfg record to write PLL data to 177 * @parent_rate: PLL input refclk rate (pre-R-divider) 178 * 179 * Pre-compute some data used by the PLL configuration algorithm when 180 * the PLL's reference clock rate changes. The intention is to avoid 181 * computation when the parent rate remains constant - expected to be 182 * the common case. 183 * 184 * Returns: 0 upon success or -ERANGE if the reference clock rate is 185 * out of range. 186 */ 187 static int __wrpll_update_parent_rate(struct wrpll_cfg *c, 188 unsigned long parent_rate) 189 { 190 u8 max_r_for_parent; 191 192 if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ) 193 return -ERANGE; 194 195 c->parent_rate = parent_rate; 196 max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ); 197 c->max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent); 198 199 c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ); 200 201 return 0; 202 } 203 204 /** 205 * wrpll_configure_for_rate() - compute PLL configuration for a target rate 206 * @c: ptr to a struct wrpll_cfg record to write into 207 * @target_rate: target PLL output clock rate (post-Q-divider) 208 * @parent_rate: PLL input refclk rate (pre-R-divider) 209 * 210 * Compute the appropriate PLL signal configuration values and store 211 * in PLL context @c. PLL reprogramming is not glitchless, so the 212 * caller should switch any downstream logic to a different clock 213 * source or clock-gate it before presenting these values to the PLL 214 * configuration signals. 215 * 216 * The caller must pass this function a pre-initialized struct 217 * wrpll_cfg record: either initialized to zero (with the 218 * exception of the .name and .flags fields) or read from the PLL. 219 * 220 * Context: Any context. Caller must protect the memory pointed to by @c 221 * from simultaneous access or modification. 222 * 223 * Return: 0 upon success; anything else upon failure. 224 */ 225 int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, 226 unsigned long parent_rate) 227 { 228 unsigned long ratio; 229 u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre; 230 u32 best_f, f, post_divr_freq; 231 u8 fbdiv, divq, best_r, r; 232 int range; 233 234 if (c->flags == 0) { 235 WARN(1, "%s called with uninitialized PLL config", __func__); 236 return -EINVAL; 237 } 238 239 /* Initialize rounding data if it hasn't been initialized already */ 240 if (parent_rate != c->parent_rate) { 241 if (__wrpll_update_parent_rate(c, parent_rate)) { 242 pr_err("%s: PLL input rate is out of range\n", 243 __func__); 244 return -ERANGE; 245 } 246 } 247 248 c->flags &= ~WRPLL_FLAGS_RESET_MASK; 249 250 /* Put the PLL into bypass if the user requests the parent clock rate */ 251 if (target_rate == parent_rate) { 252 c->flags |= WRPLL_FLAGS_BYPASS_MASK; 253 return 0; 254 } 255 256 c->flags &= ~WRPLL_FLAGS_BYPASS_MASK; 257 258 /* Calculate the Q shift and target VCO rate */ 259 divq = __wrpll_calc_divq(target_rate, &target_vco_rate); 260 if (!divq) 261 return -1; 262 c->divq = divq; 263 264 /* Precalculate the pre-Q divider target ratio */ 265 ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate); 266 267 fbdiv = __wrpll_calc_fbdiv(c); 268 best_r = 0; 269 best_f = 0; 270 best_delta = MAX_VCO_FREQ; 271 272 /* 273 * Consider all values for R which land within 274 * [MIN_POST_DIVR_FREQ, MAX_POST_DIVR_FREQ]; prefer smaller R 275 */ 276 for (r = c->init_r; r <= c->max_r; ++r) { 277 f_pre_div = ratio * r; 278 f = (f_pre_div + (1 << ROUND_SHIFT)) >> ROUND_SHIFT; 279 f >>= (fbdiv - 1); 280 281 post_divr_freq = div_u64(parent_rate, r); 282 vco_pre = fbdiv * post_divr_freq; 283 vco = vco_pre * f; 284 285 /* Ensure rounding didn't take us out of range */ 286 if (vco > target_vco_rate) { 287 --f; 288 vco = vco_pre * f; 289 } else if (vco < MIN_VCO_FREQ) { 290 ++f; 291 vco = vco_pre * f; 292 } 293 294 delta = abs(target_rate - vco); 295 if (delta < best_delta) { 296 best_delta = delta; 297 best_r = r; 298 best_f = f; 299 } 300 } 301 302 c->divr = best_r - 1; 303 c->divf = best_f - 1; 304 305 post_divr_freq = div_u64(parent_rate, best_r); 306 307 /* Pick the best PLL jitter filter */ 308 range = __wrpll_calc_filter_range(post_divr_freq); 309 if (range < 0) 310 return range; 311 c->range = range; 312 313 return 0; 314 } 315 316 /** 317 * wrpll_calc_output_rate() - calculate the PLL's target output rate 318 * @c: ptr to a struct wrpll_cfg record to read from 319 * @parent_rate: PLL refclk rate 320 * 321 * Given a pointer to the PLL's current input configuration @c and the 322 * PLL's input reference clock rate @parent_rate (before the R 323 * pre-divider), calculate the PLL's output clock rate (after the Q 324 * post-divider). 325 * 326 * Context: Any context. Caller must protect the memory pointed to by @c 327 * from simultaneous modification. 328 * 329 * Return: the PLL's output clock rate, in Hz. The return value from 330 * this function is intended to be convenient to pass directly 331 * to the Linux clock framework; thus there is no explicit 332 * error return value. 333 */ 334 unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c, 335 unsigned long parent_rate) 336 { 337 u8 fbdiv; 338 u64 n; 339 340 if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) { 341 WARN(1, "external feedback mode not yet supported"); 342 return ULONG_MAX; 343 } 344 345 fbdiv = __wrpll_calc_fbdiv(c); 346 n = parent_rate * fbdiv * (c->divf + 1); 347 n = div_u64(n, c->divr + 1); 348 n >>= c->divq; 349 350 return n; 351 } 352 353 /** 354 * wrpll_calc_max_lock_us() - return the time for the PLL to lock 355 * @c: ptr to a struct wrpll_cfg record to read from 356 * 357 * Return the minimum amount of time (in microseconds) that the caller 358 * must wait after reprogramming the PLL to ensure that it is locked 359 * to the input frequency and stable. This is likely to depend on the DIVR 360 * value; this is under discussion with the manufacturer. 361 * 362 * Return: the minimum amount of time the caller must wait for the PLL 363 * to lock (in microseconds) 364 */ 365 unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c) 366 { 367 return MAX_LOCK_US; 368 } 369